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| author | Brian Silver <bsilver@us.ibm.com> | 2016-04-25 09:24:34 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-03 16:02:32 -0500 |
| commit | 877f139a1b5bf76169969c44c8591892d08d6c47 (patch) | |
| tree | 21d6345cc3d8cf89f4b3ca36bc7321beabd4ca68 /src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | |
| parent | eda8334232da07a02f60b07fe4ccf9ee678e6581 (diff) | |
| download | talos-hostboot-877f139a1b5bf76169969c44c8591892d08d6c47.tar.gz talos-hostboot-877f139a1b5bf76169969c44c8591892d08d6c47.zip | |
Add 8Gb DRAM support
Change-Id: I781b4c4993cfb09aab2031d1cd8258502a468223
Original-Change-Id: Ia2ba89169b1bdfe746bce29f5e6c32ef14b2e11c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23720
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37393
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 57924e363..296bfddf4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -100,8 +100,6 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE // Get the translation array, based on this specific DIMM's config dimm::kind l_dimm(d); - // TK: Get the information from the translation table for this DIMM. - FAPI_DBG("address translation for DIMM %s %dR %dgbx%d in slot %d", mss::c_str(d), l_dimm.iv_master_ranks, l_dimm.iv_dram_density, l_dimm.iv_dram_width, l_slot); @@ -148,20 +146,26 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE } - // Tell the MC which of the row bits are valid. + // Tell the MC which of the row bits are valid, and map the DIMM selector if (l_dimm.iv_rows >= 16) { l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + l_slot_offset); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R15_BIT_MAP, MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN>(0b00110); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00101); } if (l_dimm.iv_rows >= 17) { l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + l_slot_offset); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R16_BIT_MAP, MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN>(0b00101); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00100); } if (l_dimm.iv_rows >= 18) { l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + l_slot_offset); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R17_BIT_MAP, MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN>(0b00100); + l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00011); } } @@ -178,8 +182,7 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE // Master rank 0, 1 bit maps are ignored. // Row 16,17 bit maps are ignored. // Row 15 maps to Port Address bit 6 - l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00101); - l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R15_BIT_MAP, MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN>(0b00110); + // Drop down the column assignments l_xlate1.insertFromRight<MCS_PORT02_MCP0XLT1_COL4_BIT_MAP, |
