diff options
| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-07-13 15:06:13 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-07-26 10:29:10 -0400 |
| commit | fd029f5afa54473a055a9b938d53da2e556b5a75 (patch) | |
| tree | 87215911f0c9d138c74abe760334dd20a5864856 /src | |
| parent | 135d297bcee4f80451c3fd5e4061f1010fe4f6d6 (diff) | |
| download | talos-hostboot-fd029f5afa54473a055a9b938d53da2e556b5a75.tar.gz talos-hostboot-fd029f5afa54473a055a9b938d53da2e556b5a75.zip | |
L3 draminit and mss_lib
Change-Id: If5cae63291864da0b87d6a1e82407da9358d62d2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43121
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43278
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src')
48 files changed, 586 insertions, 644 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C index 521bd0a87..d93885fec 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C @@ -27,10 +27,10 @@ /// @file ccs.C /// @brief Run and manage the CCS engine /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -55,7 +55,7 @@ namespace ccs /// @return FAPI2_RC_SUCCESS iff success /// template<> -fapi2::ReturnCode start_stop( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, bool i_start_stop ) +fapi2::ReturnCode start_stop( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, const bool i_start_stop ) { typedef ccsTraits<TARGET_TYPE_MCBIST> TT; @@ -73,7 +73,6 @@ fapi_try_exit: /// /// @brief Determine the CCS failure type -/// @tparam T the fapi2 target type of the target for this error /// @param[in] i_target MCBIST target /// @param[in] i_type the failure type /// @param[in] i_mca The port the CCS instruction is training @@ -90,16 +89,20 @@ fapi2::ReturnCode fail_type( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, FAPI_ASSERT(STAT_READ_MISCOMPARE != i_type, fapi2::MSS_CCS_READ_MISCOMPARE() .set_MCBIST_TARGET(i_target) + .set_FAIL_TYPE(i_type) .set_MCA_TARGET(i_mca), "%s CCS FAIL Read Miscompare", mss::c_str(i_mca)); // This error is likely due to a bad CCS engine/ MCBIST FAPI_ASSERT(STAT_UE_SUE != i_type, - fapi2::MSS_CCS_UE_SUE().set_MCBIST_TARGET(i_target), + fapi2::MSS_CCS_UE_SUE() + .set_FAIL_TYPE(i_type) + .set_MCBIST_TARGET(i_target), "%s CCS FAIL UE or SUE Error", mss::c_str(i_target)); FAPI_ASSERT(STAT_CAL_TIMEOUT != i_type, fapi2::MSS_CCS_CAL_TIMEOUT() + .set_FAIL_TYPE(i_type) .set_MCBIST_TARGET(i_target) .set_MCA_TARGET(i_mca), "%s CCS FAIL Calibration Operation Time Out", mss::c_str(i_mca)); @@ -128,7 +131,7 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<TARGET_TYPE_MCBIST>& i_ fapi2::buffer<uint64_t> status; - FAPI_TRY(start_stop(i_target, mss::START)); + FAPI_TRY(start_stop(i_target, mss::START), "%s Error in execute_inst_array", mss::c_str(i_port) ); mss::poll(i_target, TT::STATQ_REG, i_program.iv_poll, [&status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool @@ -142,13 +145,14 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<TARGET_TYPE_MCBIST>& i_ // Check for done and success. DONE being the only bit set. if (status == STAT_QUERY_SUCCESS) { - FAPI_INF("CCS Executed Successfully."); + FAPI_INF("%s CCS Executed Successfully.", mss::c_str(i_port) ); goto fapi_try_exit; } // So we failed or we're still in progress. Mask off the fail bits // and run this through the FFDC generator. - FAPI_TRY( fail_type(i_target, status & 0x1C00000000000000, i_port) ); + // TK: Put the const below into a traits class? -- JLH + FAPI_TRY( fail_type(i_target, status & 0x1C00000000000000, i_port), "Error in execute_inst_array" ); fapi_try_exit: return fapi2::current_err; @@ -181,15 +185,14 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, auto l_inst_iter = i_program.iv_instructions.begin(); // Stop the CCS engine just for giggles - it might be running ... - FAPI_TRY( start_stop(i_target, mss::states::STOP) ); + FAPI_TRY( start_stop(i_target, mss::states::STOP), "Error in ccs::execute" ); FAPI_ASSERT( mss::poll(i_target, TT::STATQ_REG, poll_parameters(), [](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool { FAPI_INF("ccs statq (stop) 0x%llx, remaining: %d", stat_reg, poll_remaining); return stat_reg.getBit<TT::CCS_IN_PROGRESS>() != 1; }), - fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target), - "CCS appears hung (trying to stop)"); + fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target)); while (l_inst_iter != i_program.iv_instructions.end()) { @@ -207,8 +210,8 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, // simple (straight line) CCS programs. Anything with a loop or such will need another mechanism. l_inst_iter->arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_GOTO_CMD, MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN>(l_inst_count + 1); - FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0) ); - FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1) ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0), "Error in ccs::execute" ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1), "Error in ccs::execute" ); // arr1 contains a specification of the delay and repeat after this instruction, as well // as a repeat. Total up the delays as we go so we know how long to wait before polling @@ -244,8 +247,8 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, // here as an instruction forces the CCS engine to wait the delay specified in // the last instruction in this array (which it otherwise doesn't do.) l_des.arr1.setBit<MCBIST_CCS_INST_ARR1_00_END>(); - FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0) ); - FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1) ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0), "Error in ccs::execute" ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1), "Error in ccs::execute" ); FAPI_INF("css inst %d fixup: 0x%016lX 0x%016lX (0x%lx, 0x%lx) %s", l_inst_count, l_des.arr0, l_des.arr1, @@ -255,8 +258,8 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, for (const auto& p : i_ports) { FAPI_INF("executing CCS array for port %d (%s)", mss::relative_pos<TARGET_TYPE_MCBIST>(p), mss::c_str(p)); - FAPI_TRY( select_ports( i_target, mss::relative_pos<TARGET_TYPE_MCBIST>(p)) ); - FAPI_TRY( execute_inst_array(i_target, i_program, p) ); + FAPI_TRY( select_ports( i_target, mss::relative_pos<TARGET_TYPE_MCBIST>(p)), "Error in ccs execute" ); + FAPI_TRY( execute_inst_array(i_target, i_program, p), "Error in ccs execute" ); } } @@ -267,8 +270,6 @@ fapi_try_exit: /// /// @brief Nimbus specialization for modeq_copy_cke_to_spare_cke -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the ccsTraits associated with T - derived /// @param[in] fapi2::Target<TARGET_TYPE_MCBIST>& the target to effect /// @param[in,out] the buffer representing the mode register /// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H index c3a680790..56fa05e99 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H @@ -27,7 +27,7 @@ /// @file ccs.H /// @brief Run and manage the CCS engine /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 @@ -174,6 +174,9 @@ namespace mss namespace ccs { +/// +/// @brief Enums for CCS return codes +/// enum { // Success is defined as done-bit set, no others. @@ -324,7 +327,6 @@ class program /// @tparam T the target type of the chiplet which executes the CCS instruction /// @tparam TT the CCS traits of the chiplet which executes the CCS instruction /// @param[in,out] i_arr0 fapi2::buffer<uint64_t> representing the ARR0 of the instruction -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > static void mrs_rcd_helper( fapi2::buffer<uint64_t>& i_arr0 ) @@ -679,7 +681,6 @@ inline instruction_t<T> precharge_all_command( const fapi2::Target<fapi2::TARGET /// @tparam TT the CCS traits of the chiplet which executes the CCS instruction /// @param[in] i_target the target to effect /// @param[in] i_ports the buffer representing the ports -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > inline fapi2::ReturnCode select_ports( const fapi2::Target<T>& i_target, uint64_t i_ports) @@ -706,7 +707,6 @@ fapi_try_exit: /// @param[in] the target to effect /// @param[in,out] io_buffer the buffer representing the mode register /// @param[in] i_value true iff stop whenever failure occurs. -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > inline void stop_on_err( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value) @@ -720,7 +720,6 @@ inline void stop_on_err( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_bu /// @tparam TT the CCS traits of the chiplet which executes the CCS instruction /// @param[in] the target to effect /// @param[in,out] io_buffer the buffer representing the mode register -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > inline void disable_ecc( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer) @@ -737,7 +736,6 @@ inline void disable_ecc( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_bu /// @param[in] the target to effect /// @param[in,out] io_buffer the buffer representing the mode register /// @param[in] i_value true iff ignore any array ue or sue errors. -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > inline void ue_disable( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value) @@ -752,7 +750,6 @@ inline void ue_disable( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buf /// @param[in] the target to effect /// @param[in,out] io_buffer the buffer representing the mode register /// @param[in] i_value mss::ON iff delay parity a cycle -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > inline void parity_after_cmd( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value) @@ -768,7 +765,6 @@ inline void parity_after_cmd( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& /// @param[in,out] io_buffer the buffer representing the mode register /// @param[in] i_count the count to wait for DDR cal to complete. /// @param[in] i_mult the DDR calibration time multiplaction factor -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > inline void cal_count( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, @@ -790,7 +786,6 @@ inline void cal_count( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buff /// @param[in,out] io_buffer the buffer representing the mode register /// @param[in] i_value mss::ON iff Copy CKE signals to CKE Spare on both ports /// @note no-op for p9n -/// @return void /// template< fapi2::TargetType T, typename TT = ccsTraits<T> > void copy_cke_to_spare_cke( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C index 05693080b..ae62be201 100755 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,9 +28,9 @@ /// @brief Run and manage the RCD_LOAD engine /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -70,13 +70,13 @@ fapi2::ReturnCode bcw_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_ for (const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(p)) { FAPI_DBG("bcw load for %s", mss::c_str(d)); - FAPI_TRY( perform_bcw_load(d, l_program.iv_instructions) ); + FAPI_TRY( perform_bcw_load(d, l_program.iv_instructions), "Failed BCW load %s", mss::c_str(d) ); } // We have to configure the CCS engine to let it know which port these instructions are // going out (or whether it's broadcast ...) so lets execute the instructions we presently // have so that we kind of do this by port - FAPI_TRY( ccs::execute(i_target, l_program, p) ); + FAPI_TRY( ccs::execute(i_target, l_program, p), "Failed executing ccs engine load %s", mss::c_str(i_target)); } fapi_try_exit: @@ -96,8 +96,8 @@ fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYP uint8_t l_type = 0; uint8_t l_gen = 0; - FAPI_TRY( mss::eff_dimm_type(i_target, l_type) ); - FAPI_TRY( mss::eff_dram_gen(i_target, l_gen) ); + FAPI_TRY( mss::eff_dimm_type(i_target, l_type), "Error in perform_bcw_load" ); + FAPI_TRY( mss::eff_dram_gen(i_target, l_gen), "Error in perform_bcw_load" ); // If we're here, we have a problem. The DIMM kind (type and/or generation) wasn't known // to our dispatcher. We have a DIMM plugged in we don't know how to deal with. @@ -124,7 +124,7 @@ fapi2::ReturnCode perform_bcw_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) { FAPI_DBG("perform bcw_load for %s [expecting lrdimm (ddr4)]", mss::c_str(i_target)); - FAPI_TRY( bcw_load_ddr4(i_target, io_inst) ); + FAPI_TRY( bcw_load_ddr4(i_target, io_inst), "Failed bcw load for lrdimm %s", mss::c_str(i_target)); fapi_try_exit: return fapi2::current_err; @@ -157,8 +157,8 @@ fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_T uint8_t l_type = 0; uint8_t l_gen = 0; - FAPI_TRY( mss::eff_dimm_type(i_target, l_type) ); - FAPI_TRY( mss::eff_dram_gen(i_target, l_gen) ); + FAPI_TRY( mss::eff_dimm_type(i_target, l_type), "Error in perform_bcw_load" ); + FAPI_TRY( mss::eff_dram_gen(i_target, l_gen), "Error in perform_bcw_load" ); return perform_bcw_load_dispatch<FORCE_DISPATCH>(dimm_kind( l_type, l_gen ), i_target, io_inst); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H index 6c94019f3..be5f1bfc5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H @@ -28,9 +28,9 @@ /// @brief Code to support bcw_loads /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_BCW_LOAD_H_ @@ -96,12 +96,12 @@ struct perform_bcw_load_overload< KIND_LRDIMM_DDR4 > static constexpr bool available = true; }; -/// -/// Define the default case for overloaded calls. enable_if states that -/// if there is a DEFAULT_KIND overload for this TargetType, then this -/// entry point will be defined. Note the general case below is enabled if -/// there is no overload defined for this TargetType -/// +// +// Define the default case for overloaded calls. enable_if states that +// if there is a DEFAULT_KIND overload for this TargetType, then this +// entry point will be defined. Note the general case below is enabled if +// there is no overload defined for this TargetType +// /// /// @brief Perform the bcw_load operations @@ -149,8 +149,9 @@ fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR /// @brief Perform the bcw_load operations /// @tparam K the kind of DIMM we're operating on (derived) /// @tparam B boolean that enables API from K dimm kind +/// @param[in] i_kind the dimm kind struct for the i_target /// @param[in] i_target, a fapi2::Target<fapi2::TARGET_TYPE_DIMM> -/// @param[in,out] a vector of CCS instructions we should add to +/// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// template< kind_t K, bool B = perform_bcw_load_overload<K>::available > @@ -170,7 +171,14 @@ inline fapi2::ReturnCode perform_bcw_load_dispatch( const kind_t& i_kind, return perform_bcw_load<K>(i_target, io_inst); } -// DEFAULT_KIND is 0 so this is the end of the recursion +/// +/// @brief Perform the bcw_load operations +/// @param[in] i_kind the dimm kind struct for the i_target +/// @param[in] i_target, a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in,out] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note DEFAULT_KIND is 0 so this is the end of the recursion +/// template<> inline fapi2::ReturnCode perform_bcw_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C index 73521b8d9..7075f597a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C @@ -28,9 +28,9 @@ /// @brief Run and manage the DDR4 bcw loading /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -56,7 +56,7 @@ namespace mss { /// -/// @brief Perform the bcw_load_ddr4 operations - TARGET_TYPE_DIMM specialization +/// @brief Perform the bcw_load_ddr4 operations /// @param[in] i_target a DIMM target /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok @@ -68,7 +68,7 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // Per DDR4BC01 uint64_t l_tDLLK = 0; - FAPI_TRY( tdllk(i_target, l_tDLLK), "Failed to get tDLLK for %s", mss::c_str(i_target) ); + FAPI_TRY( tdllk(i_target, l_tDLLK), "Failed to get tDLLK for %s in bcw_load_ddr4", mss::c_str(i_target) ); { static const std::vector< cw_data > l_bcw_4bit_data = @@ -101,8 +101,9 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // We set the 4-bit buffer control words first (they live in function space 0 // hw is supposed to default to function space 0 but Just.In.Case. - FAPI_TRY( ddr4::function_space_select<0>(i_target, io_inst) ); - FAPI_TRY( control_word_engine<BCW_4BIT>(i_target, l_bcw_4bit_data, io_inst) ); + FAPI_TRY( ddr4::function_space_select<0>(i_target, io_inst), "Failed function space select 0", mss::c_str(i_target)); + FAPI_TRY( control_word_engine<BCW_4BIT>(i_target, l_bcw_4bit_data, io_inst) , "Failed control_word_engine", + mss::c_str(i_target)); // We set our 8-bit buffer control words but have to switch function space // number for different control words. So it doesn't fit cleanly into a @@ -110,19 +111,21 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // (feels like we should be initializing more control word....) { cw_data l_data(FUNC_SPACE_6, BUFF_TRAIN_CONFIG_CW, eff_dimm_ddr4_f6bc4x, mss::tmrc()); - FAPI_TRY( ddr4::function_space_select<6>(i_target, io_inst) ); - FAPI_TRY( control_word_engine<BCW_8BIT>(i_target, l_data, io_inst) ); + FAPI_TRY( ddr4::function_space_select<6>(i_target, io_inst), "Failed function space select 6", mss::c_str(i_target) ); + FAPI_TRY( control_word_engine<BCW_8BIT>(i_target, l_data, io_inst), "Failed control_word_engine", + mss::c_str(i_target) ); } { cw_data l_data(FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, mss::tmrc()); - FAPI_TRY( ddr4::function_space_select<5>(i_target, io_inst) ); - FAPI_TRY( control_word_engine<BCW_8BIT>(i_target, l_data, io_inst) ); + FAPI_TRY( ddr4::function_space_select<5>(i_target, io_inst), "Failed function space select 5", mss::c_str(i_target) ); + FAPI_TRY( control_word_engine<BCW_8BIT>(i_target, l_data, io_inst), "Failed control_word_engine", + mss::c_str(i_target) ); } // Its recommended to always return to the function space // "pointer" back to 0 so we always know where we are starting from - FAPI_TRY( ddr4::function_space_select<0>(i_target, io_inst) ); + FAPI_TRY( ddr4::function_space_select<0>(i_target, io_inst), "Error in bcw_load_ddr4 for function space select 0" ); } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H index 526588d97..1ff2d9e10 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,9 +28,9 @@ /// @brief Code to support bcw_load_ddr4 /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_BCW_LOAD_DDR4_H_ @@ -44,7 +44,7 @@ namespace mss { /// -/// @brief Perform the bcw_load_ddr4 operations - TARGET_TYPE_DIMM specialization +/// @brief Perform the bcw_load_ddr4 operations /// @param[in] i_target a DIMM target /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H index 60e39e58b..281d1dd06 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C index cc96e9253..def06a0df 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB Memory #include <vector> @@ -59,7 +59,7 @@ namespace ddr4 /// fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, - const uint64_t& i_rank, + const uint64_t i_rank, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) { // JEDEC has a 3 step latching process for WR VREF @@ -73,15 +73,18 @@ fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_ // Add both to the CCS program - JEDEC step 1 enable_vref_train_enable(l_mr_override); - FAPI_TRY( mrs_engine(i_target, l_mr_override, i_rank, mss::tvrefdqe(i_target), io_inst) ); + FAPI_TRY( mrs_engine(i_target, l_mr_override, i_rank, mss::tvrefdqe(i_target), io_inst), + "Error in add_latch_wr_vref_commands" ); // Add both to the CCS program - JEDEC step 2 - FAPI_TRY( mrs_engine(i_target, l_mr_override, i_rank, mss::tvrefdqe(i_target), io_inst) ); + FAPI_TRY( mrs_engine(i_target, l_mr_override, i_rank, mss::tvrefdqe(i_target), io_inst), + "Error in add_latch_wr_vref_commands" ); // Hits VREFDQ train disable - putting the DRAM's back in mainline mode // Add both to the CCS program - JEDEC step 3 disable_vref_train_enable(l_mr_override); - FAPI_TRY( mrs_engine(i_target, l_mr_override, i_rank, mss::tvrefdqe(i_target), io_inst) ); + FAPI_TRY( mrs_engine(i_target, l_mr_override, i_rank, mss::tvrefdqe(i_target), io_inst), + "Error in add_latch_wr_vref_commands" ); fapi_try_exit: return fapi2::current_err; @@ -97,9 +100,9 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const uint64_t& i_rank_pair, - const uint8_t& i_train_range, - const uint8_t& i_train_value) + const uint64_t i_rank_pair, + const uint8_t i_train_range, + const uint8_t i_train_value) { // Declares variables const auto l_mcbist = find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); @@ -109,7 +112,9 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2 std::vector<uint64_t> l_ranks; // Gets the ranks on which to latch the VREF's - FAPI_TRY(mss::rank::get_ranks_in_pair( i_target, i_rank_pair, l_ranks)); + FAPI_TRY(mss::rank::get_ranks_in_pair( i_target, i_rank_pair, l_ranks), + "Failed get_ranks_in_pair in latch_wr_vref_commands_by_rank_pair %s", + mss::c_str(i_target)); // Adds in latching commands for all ranks for (const auto& l_rank : l_ranks) @@ -121,18 +126,22 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2 } // Ensures we get a valid DIMM target / rank combo - FAPI_TRY( mss::rank::get_dimm_target_from_rank(i_target, l_rank, l_dimm) ); + FAPI_TRY( mss::rank::get_dimm_target_from_rank(i_target, l_rank, l_dimm), + "%s Failed get_dimm_target_from_rank in latch_wr_vref_commands_by_rank_pair", + mss::c_str(i_target)); // Adds the latching commands to the CCS program for this current rank FAPI_TRY(setup_latch_wr_vref_commands_by_rank(l_dimm, l_rank, i_train_range, i_train_value, - l_program.iv_instructions)); + l_program.iv_instructions), + "%s Failed setup_latch_wr_vref_commands_by_rank in latch_wr_vref_commands_by_rank_pair", + mss::c_str(i_target)); } // Executes the CCS commands - FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target) ); + FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "Failed ccs execute %s", mss::c_str(i_target) ); fapi_try_exit: return fapi2::current_err; @@ -148,14 +157,14 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t& i_rank, - const uint8_t& i_train_range, - const uint8_t& i_train_value, + const uint64_t i_rank, + const uint8_t i_train_range, + const uint8_t i_train_value, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) { // Check to make sure our ctor worked ok mrs06_data l_mrs06( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS06 data from attributes"); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS06 data from attributes", mss::c_str(i_target)); // Setup training range if the value is not the default if(i_train_range != wr_vref_override::USE_DEFAULT_WR_VREF_SETTINGS) @@ -187,7 +196,9 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi FAPI_TRY(add_latch_wr_vref_commands(i_target, l_mrs06, i_rank, - io_inst)); + io_inst), + "%s Failed add_latch_wr_vref_commands in setup_latch_wr_vref_commands_by_rank", + mss::c_str(i_target) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H index 6c95f1280..39536d566 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB Memory #ifndef _LATCH_WR_VREF_H_ @@ -64,7 +64,7 @@ enum wr_vref_override : uint8_t /// fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, - const uint64_t& i_rank, + const uint64_t i_rank, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); /// @@ -77,9 +77,9 @@ fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_ /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const uint64_t& i_rank_pair, - const uint8_t& i_train_range, - const uint8_t& i_train_value); + const uint64_t i_rank_pair, + const uint8_t i_train_range, + const uint8_t i_train_value); /// /// @brief enables VREF train enable in an MRS06 class @@ -117,9 +117,9 @@ inline void disable_vref_train_enable(mrs06_data& io_mrs06) /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t& i_rank, - const uint8_t& i_train_range, - const uint8_t& i_train_value, + const uint64_t i_rank, + const uint8_t i_train_range, + const uint8_t i_train_value, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); } // close namespace DDR4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index 45333a724..71deb5bbe 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -27,10 +27,10 @@ /// @file mrs00.C /// @brief Run and manage the DDR4 MRS00 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -64,21 +64,22 @@ mrs00_data::mrs00_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_write_recovery(0), iv_cas_latency(0) { - FAPI_TRY( mss::eff_dram_rbt(i_target, iv_read_burst_type) ); - FAPI_TRY( mss::eff_dram_cl(i_target, iv_cas_latency) ); - FAPI_TRY( mss::eff_dram_dll_reset(i_target, iv_dll_reset) ); - FAPI_TRY( mss::eff_dram_tm(i_target, iv_test_mode) ); - FAPI_TRY( mss::eff_dram_twr(i_target, iv_write_recovery) ); + FAPI_TRY( mss::eff_dram_rbt(i_target, iv_read_burst_type), "Error in mrs00_data()" ); + FAPI_TRY( mss::eff_dram_cl(i_target, iv_cas_latency), "Error in mrs00_data()" ); + FAPI_TRY( mss::eff_dram_dll_reset(i_target, iv_dll_reset), "Error in mrs00_data()" ); + FAPI_TRY( mss::eff_dram_tm(i_target, iv_test_mode), "Error in mrs00_data()" ); + FAPI_TRY( mss::eff_dram_twr(i_target, iv_write_recovery), "Error in mrs00_data()" ); - FAPI_INF("MR0 Attributes: BL: 0x%x, RBT: 0x%x, CL: 0x%x, TM: 0x%x, DLL_RESET: 0x%x, WR: 0x%x", - iv_burst_length, iv_read_burst_type, iv_cas_latency, iv_test_mode, iv_dll_reset, iv_write_recovery); + FAPI_INF("%s MR0 Attributes: BL: 0x%x, RBT: 0x%x, CL: 0x%x, TM: 0x%x, DLL_RESET: 0x%x, WR: 0x%x", + mss::c_str(i_target), iv_burst_length, iv_read_burst_type, iv_cas_latency, iv_test_mode, iv_dll_reset, + iv_write_recovery); o_rc = fapi2::FAPI2_RC_SUCCESS; return; fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs00", mss::c_str(i_target)); return; } @@ -95,7 +96,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs00_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS00 data from attributes"); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS00 data from attributes", mss::c_str(i_target) ); FAPI_TRY( mrs00(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -147,7 +148,9 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, .set_PARAMETER(WRITE_RECOVERY) .set_PARAMETER_VALUE(i_data.iv_write_recovery) .set_DIMM_IN_ERROR(i_target), - "Bad value for Write Recovery: %d (%s)", i_data.iv_write_recovery, mss::c_str(i_target)); + "Bad value for Write Recovery: %d (%s)", + i_data.iv_write_recovery, + mss::c_str(i_target)); FAPI_ASSERT((i_data.iv_cas_latency >= LOWEST_CL) && (i_data.iv_cas_latency < (LOWEST_CL + CL_COUNT)), fapi2::MSS_BAD_MR_PARAMETER() @@ -155,7 +158,9 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, .set_PARAMETER(CAS_LATENCY) .set_PARAMETER_VALUE(i_data.iv_cas_latency) .set_DIMM_IN_ERROR(i_target), - "Bad value for CAS Latency: %d (%s)", i_data.iv_cas_latency, mss::c_str(i_target)); + "Bad value for CAS Latency: %d (%s)", + i_data.iv_cas_latency, + mss::c_str(i_target)); io_inst.arr0.insertFromRight<A0, 2>(i_data.iv_burst_length); io_inst.arr0.writeBit<A3>(i_data.iv_read_burst_type); @@ -177,7 +182,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, io_inst.arr0.writeBit<A10>(l_wr.getBit<6>()); io_inst.arr0.writeBit<A9>(l_wr.getBit<7>()); - FAPI_INF("MR0: 0x%016llx", uint64_t(io_inst.arr0)); + FAPI_INF("%s MR0: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C index 19e4c71a1..3fd08b8a0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C @@ -27,10 +27,10 @@ /// @file mrs01.C /// @brief Run and manage the DDR4 MRS01 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -61,20 +61,20 @@ mrs01_data::mrs01_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_tdqs(0), iv_qoff(0) { - FAPI_TRY( mss::eff_dram_dll_enable(i_target, iv_dll_enable) ); - FAPI_TRY( mss::vpd_mt_dram_drv_imp_dq_dqs(i_target, &(iv_odic[0])) ); - FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency) ); - FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable) ); - FAPI_TRY( mss::eff_dram_rtt_nom(i_target, &(iv_rtt_nom[0])) ); - FAPI_TRY( mss::eff_dram_tdqs(i_target, iv_tdqs) ); - FAPI_TRY( mss::eff_dram_output_buffer(i_target, iv_qoff) ); + FAPI_TRY( mss::eff_dram_dll_enable(i_target, iv_dll_enable), "Error in mrs01_data()" ); + FAPI_TRY( mss::vpd_mt_dram_drv_imp_dq_dqs(i_target, &(iv_odic[0])), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_rtt_nom(i_target, &(iv_rtt_nom[0])), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_tdqs(i_target, iv_tdqs), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_output_buffer(i_target, iv_qoff), "Error in mrs01_data()" ); o_rc = fapi2::FAPI2_RC_SUCCESS; return; fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs01"); return; } @@ -91,7 +91,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs01_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS01 data from attributes"); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS01 data from attributes", mss::c_str(i_target) ); FAPI_TRY( mrs01(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -139,7 +139,9 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, .set_PARAMETER(OUTPUT_IMPEDANCE) .set_PARAMETER_VALUE(i_data.iv_odic[mss::index(i_rank)]) .set_DIMM_IN_ERROR(i_target), - "Bad value for output driver impedance: %d (%s)", i_data.iv_odic[mss::index(i_rank)], mss::c_str(i_target)); + "Bad value for output driver impedance: %d (%s)", + i_data.iv_odic[mss::index(i_rank)], + mss::c_str(i_target)); // Map from impedance to bits in MRS1 l_odic_buffer = (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) ? @@ -149,10 +151,11 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, l_rtt_nom_buffer = i_data.iv_rtt_nom[mss::index(i_rank)]; // Print this here as opposed to the MRS01 ctor as we want to see the specific rtt now information - FAPI_INF("MR1 rank %d attributes: DLL_ENABLE: 0x%x, ODIC: 0x%x(0x%x), AL: 0x%x, WLE: 0x%x, " - "RTT_NOM:0x%x, TDQS: 0x%x, QOFF: 0x%x", i_rank, - i_data.iv_dll_enable, i_data.iv_odic[mss::index(i_rank)], uint8_t(l_odic_buffer), uint8_t(l_additive_latency), - i_data.iv_wl_enable, + FAPI_INF("%s MR1 rank %d attributes: DLL_ENABLE: 0x%x, ODIC: 0x%x(0x%x), AL: 0x%x, WLE: 0x%x, " + "RTT_NOM:0x%x, TDQS: 0x%x, QOFF: 0x%x", + mss::c_str(i_target), i_rank, i_data.iv_dll_enable, + i_data.iv_odic[mss::index(i_rank)], uint8_t(l_odic_buffer), + uint8_t(l_additive_latency), i_data.iv_wl_enable, uint8_t(l_rtt_nom_buffer), i_data.iv_tdqs, i_data.iv_qoff); io_inst.arr0.writeBit<A0>(i_data.iv_dll_enable); @@ -164,7 +167,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, io_inst.arr0.writeBit<A11>(i_data.iv_tdqs); io_inst.arr0.writeBit<A12>(i_data.iv_qoff); - FAPI_INF("MR1: 0x%016llx", uint64_t(io_inst.arr0)); + FAPI_INF("%s MR1: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); return fapi2::FAPI2_RC_SUCCESS; @@ -209,9 +212,9 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS mss::swizzle<5, 3, A10>(i_inst.arr0, o_rtt_nom); FAPI_INF("MR1 rank %d decode: DLL_ENABLE: 0x%x, ODIC: 0x%x, AL: 0x%x, WLE: 0x%x, " - "RTT_NOM: 0x%x, TDQS: 0x%x, QOFF: 0x%x", i_rank, - o_dll_enable, uint8_t(o_odic), uint8_t(o_additive_latency), o_wrl_enable, uint8_t(o_rtt_nom), - o_tdqs, o_qoff); + "RTT_NOM: 0x%x, TDQS: 0x%x, QOFF: 0x%x", + i_rank, o_dll_enable, uint8_t(o_odic), uint8_t(o_additive_latency), + o_wrl_enable, uint8_t(o_rtt_nom), o_tdqs, o_qoff); return FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C index 1c86e63e5..fe819814b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C @@ -27,10 +27,10 @@ /// @file mrs02.C /// @brief Run and manage the DDR4 MRS02 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -59,17 +59,17 @@ mrs02_data::mrs02_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_cwl(0), iv_write_crc(0) { - FAPI_TRY( mss::eff_dram_lpasr(i_target, iv_lpasr) ); - FAPI_TRY( mss::eff_dram_cwl(i_target, iv_cwl) ); - FAPI_TRY( mss::eff_dram_rtt_wr(i_target, &(iv_dram_rtt_wr[0])) ); - FAPI_TRY( mss::eff_write_crc(i_target, iv_write_crc) ); + FAPI_TRY( mss::eff_dram_lpasr(i_target, iv_lpasr), "Error in mrs02_data()" ); + FAPI_TRY( mss::eff_dram_cwl(i_target, iv_cwl), "Error in mrs02_data()" ); + FAPI_TRY( mss::eff_dram_rtt_wr(i_target, &(iv_dram_rtt_wr[0])), "Error in mrs02_data()" ); + FAPI_TRY( mss::eff_write_crc(i_target, iv_write_crc), "Error in mrs02_data()" ); o_rc = fapi2::FAPI2_RC_SUCCESS; return; fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs02", mss::c_str(i_target)); return; } @@ -86,7 +86,9 @@ fapi2::ReturnCode mrs02(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs02_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS02 data from attributes"); + FAPI_TRY( fapi2::current_err, + "%s Unable to construct MRS02 data from attributes", + mss::c_str(i_target) ); FAPI_TRY( mrs02(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -138,9 +140,9 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, // Printed here as opposed to the ctor as it uses the rank information - FAPI_INF("MR2 rank %d attributes: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x(0x%x), WRITE_CRC: 0x%x", i_rank, - uint8_t(i_data.iv_lpasr), i_data.iv_cwl, uint8_t(l_cwl_buffer), - uint8_t(l_rtt_wr_buffer), i_data.iv_write_crc); + FAPI_INF("%s MR2 rank %d attributes: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x(0x%x), WRITE_CRC: 0x%x", + mss::c_str(i_target), i_rank, uint8_t(i_data.iv_lpasr), i_data.iv_cwl, + uint8_t(l_cwl_buffer), uint8_t(l_rtt_wr_buffer), i_data.iv_write_crc); mss::swizzle<A3, CWL_LENGTH, CWL_START>(l_cwl_buffer, io_inst.arr0); @@ -184,8 +186,8 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS mss::swizzle<6, 2, A7>(i_inst.arr0, o_lpasr); mss::swizzle<5, 3, A11>(i_inst.arr0, o_rtt_wr); - FAPI_INF("MR2 rank %d deocode: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x, WRITE_CRC: 0x%x", i_rank, - uint8_t(o_lpasr), uint8_t(o_cwl), uint8_t(o_rtt_wr), o_write_crc); + FAPI_INF("MR2 rank %d deocode: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x, WRITE_CRC: 0x%x", + i_rank, uint8_t(o_lpasr), uint8_t(o_cwl), uint8_t(o_rtt_wr), o_write_crc); return FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C index a24421be3..06b9eb88c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C @@ -25,12 +25,12 @@ /// /// @file mrs03.C -/// @brief Run and manage the DDR4 DDR4 loading +/// @brief Run and manage mrs03 /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -75,26 +75,26 @@ mrs03_data::mrs03_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_fine_refresh(0), iv_read_format(fapi2::ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL) { - FAPI_TRY( mss::eff_mpr_mode(i_target, iv_mpr_mode) ); - FAPI_TRY( mss::eff_mpr_page(i_target, iv_mpr_page) ); - FAPI_TRY( mss::eff_geardown_mode(i_target, iv_geardown) ); - FAPI_TRY( mss::eff_per_dram_access(i_target, iv_pda) ); - FAPI_TRY( mss::eff_temp_readout(i_target, iv_temp_readout) ); - FAPI_TRY( mss::mrw_fine_refresh_mode(iv_fine_refresh) ); - FAPI_TRY( mss::eff_crc_wr_latency(i_target, iv_crc_wr_latency) ); - FAPI_TRY( mss::eff_mpr_rd_format(i_target, iv_read_format) ); - - FAPI_INF("MR3 attributes: MPR_MODE: 0x%x, MPR_PAGE: 0x%x, GD: 0x%x, PDA: 0x%x, " + FAPI_TRY( mss::eff_mpr_mode(i_target, iv_mpr_mode), "Error in mrs03_data()" ); + FAPI_TRY( mss::eff_mpr_page(i_target, iv_mpr_page), "Error in mrs03_data()" ); + FAPI_TRY( mss::eff_geardown_mode(i_target, iv_geardown), "Error in mrs03_data()" ); + FAPI_TRY( mss::eff_per_dram_access(i_target, iv_pda), "Error in mrs03_data()" ); + FAPI_TRY( mss::eff_temp_readout(i_target, iv_temp_readout), "Error in mrs03_data()" ); + FAPI_TRY( mss::mrw_fine_refresh_mode(iv_fine_refresh), "Error in mrs03_data()" ); + FAPI_TRY( mss::eff_crc_wr_latency(i_target, iv_crc_wr_latency), "Error in mrs03_data()" ); + FAPI_TRY( mss::eff_mpr_rd_format(i_target, iv_read_format), "Error in mrs03_data()" ); + + FAPI_INF("%s MR3 attributes: MPR_MODE: 0x%x, MPR_PAGE: 0x%x, GD: 0x%x, PDA: 0x%x, " "TEMP: 0x%x FR: 0x%x, CRC_WL: 0x%x, RF: 0x%x", - iv_mpr_mode, iv_mpr_page, iv_geardown, iv_pda, iv_temp_readout, - iv_fine_refresh, iv_crc_wr_latency, iv_read_format); + mss::c_str(i_target), iv_mpr_mode, iv_mpr_page, iv_geardown, iv_pda, + iv_temp_readout, iv_fine_refresh, iv_crc_wr_latency, iv_read_format); o_rc = fapi2::FAPI2_RC_SUCCESS; return; fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs03"); return; } @@ -111,7 +111,9 @@ fapi2::ReturnCode mrs03(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs03_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS03 data from attributes"); + FAPI_TRY( fapi2::current_err, + "%s Unable to construct MRS03 data from attributes", + mss::c_str(i_target) ); FAPI_TRY( mrs03(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -139,13 +141,16 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::buffer<uint8_t> l_crc_wr_latency_buffer; - FAPI_ASSERT((i_data.iv_crc_wr_latency >= LOWEST_WL) && (i_data.iv_crc_wr_latency < (LOWEST_WL + WL_COUNT)), + FAPI_ASSERT((i_data.iv_crc_wr_latency >= LOWEST_WL) && + (i_data.iv_crc_wr_latency < (LOWEST_WL + WL_COUNT)), fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(3) .set_PARAMETER(WRITE_CMD_LATENCY) .set_PARAMETER_VALUE(i_data.iv_crc_wr_latency) .set_DIMM_IN_ERROR(i_target), - "Bad value for Write CMD Latency: %d (%s)", i_data.iv_crc_wr_latency, mss::c_str(i_target)); + "Bad value for Write CMD Latency: %d (%s)", + i_data.iv_crc_wr_latency, + mss::c_str(i_target)); l_crc_wr_latency_buffer = crc_wr_latency_map[i_data.iv_crc_wr_latency - LOWEST_WL]; @@ -159,7 +164,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, mss::swizzle<A9, CRC_WR_LATENCY_LENGTH, CRC_WR_LATENCY_START>(l_crc_wr_latency_buffer, io_inst.arr0); mss::swizzle<A11, READ_FORMAT_LENGTH, READ_FORMAT_START>(fapi2::buffer<uint8_t>(i_data.iv_read_format), io_inst.arr0); - FAPI_INF("MR3: 0x%016llx", uint64_t(io_inst.arr0)); + FAPI_INF("%s MR3: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index 50db08756..b28dae69e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -27,10 +27,10 @@ /// @file mrs04.C /// @brief Run and manage the DDR4 MRS04 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -70,20 +70,20 @@ mrs04_data::mrs04_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, // From DDR4 Spec: 3.3 RESET and Initialization Procedure // PPR and soft PPR must be disabled during initialization // so we don't call the attribute accessor for them - FAPI_TRY( mss::eff_max_powerdown_mode(i_target, iv_max_pd_mode) ); - FAPI_TRY( mss::mrw_temp_refresh_range(iv_temp_refresh_range) ); - FAPI_TRY( mss::mrw_temp_refresh_mode(iv_temp_ref_mode) ); - FAPI_TRY( mss::eff_internal_vref_monitor(i_target, iv_vref_mon) ); - FAPI_TRY( mss::eff_cs_cmd_latency(i_target, iv_cs_cmd_latency) ); - FAPI_TRY( mss::eff_self_ref_abort(i_target, iv_ref_abort) ); - FAPI_TRY( mss::eff_rd_preamble_train(i_target, iv_rd_pre_train_mode) ); - FAPI_TRY( mss::eff_rd_preamble(i_target, iv_rd_preamble) ); - FAPI_TRY( mss::eff_wr_preamble(i_target, iv_wr_preamble) ); - - FAPI_INF("MR4 attributes: MAX_PD: 0x%x, TEMP_REFRESH_RANGE: 0x%x, TEMP_REF_MODE: 0x%x " + FAPI_TRY( mss::eff_max_powerdown_mode(i_target, iv_max_pd_mode), "Error in mrs04_data()" ); + FAPI_TRY( mss::mrw_temp_refresh_range(iv_temp_refresh_range), "Error in mrs04_data()" ); + FAPI_TRY( mss::mrw_temp_refresh_mode(iv_temp_ref_mode), "Error in mrs04_data()" ); + FAPI_TRY( mss::eff_internal_vref_monitor(i_target, iv_vref_mon), "Error in mrs04_data()" ); + FAPI_TRY( mss::eff_cs_cmd_latency(i_target, iv_cs_cmd_latency), "Error in mrs04_data()" ); + FAPI_TRY( mss::eff_self_ref_abort(i_target, iv_ref_abort), "Error in mrs04_data()" ); + FAPI_TRY( mss::eff_rd_preamble_train(i_target, iv_rd_pre_train_mode), "Error in mrs04_data()" ); + FAPI_TRY( mss::eff_rd_preamble(i_target, iv_rd_preamble), "Error in mrs04_data()" ); + FAPI_TRY( mss::eff_wr_preamble(i_target, iv_wr_preamble), "Error in mrs04_data()" ); + + FAPI_INF("%s MR4 attributes: MAX_PD: 0x%x, TEMP_REFRESH_RANGE: 0x%x, TEMP_REF_MODE: 0x%x " "VREF_MON: 0x%x, CSL: 0x%x, REF_ABORT: 0x%x, RD_PTM: 0x%x, RD_PRE: 0x%x, " "WR_PRE: 0x%x, PPR: 0x%x, SOFT PPR: 0x%x", - iv_max_pd_mode, iv_temp_refresh_range, iv_temp_ref_mode, iv_vref_mon, + mss::c_str(i_target), iv_max_pd_mode, iv_temp_refresh_range, iv_temp_ref_mode, iv_vref_mon, iv_cs_cmd_latency, iv_ref_abort, iv_rd_pre_train_mode, iv_rd_preamble, iv_wr_preamble, iv_ppr, iv_soft_ppr); @@ -93,7 +93,7 @@ mrs04_data::mrs04_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs04", mss::c_str(i_target)); return; } @@ -110,7 +110,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs04_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS04 data from attributes"); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS04 data from attributes", mss::c_str(i_target) ); FAPI_TRY( mrs04(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -162,7 +162,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, io_inst.arr0.writeBit<A12>(i_data.iv_wr_preamble); io_inst.arr0.writeBit<A13>(i_data.iv_ppr); - FAPI_INF("MR4: 0x%016llx", uint64_t(io_inst.arr0)); + FAPI_INF("%s MR4: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); return fapi2::FAPI2_RC_SUCCESS; @@ -217,9 +217,9 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS FAPI_INF("MR4 rank %d decode: MAX_PD: 0x%x, TEMP_REFRESH_RANGE: 0x%x, TEMP_REF_MODE: 0x%x " "VREF_MON: 0x%x, CSL: 0x%x, REF_ABORT: 0x%x, RD_PTM: 0x%x, RD_PRE: 0x%x, " - "WR_PRE: 0x%x, PPR: 0x%x", i_rank, - o_max_pd_mode, o_temp_refresh_range, o_temp_ref_mode, o_vref_mon, - uint8_t(o_cs_cmd_latency_buffer), o_ref_abort, + "WR_PRE: 0x%x, PPR: 0x%x", + i_rank, o_max_pd_mode, o_temp_refresh_range, o_temp_ref_mode, + o_vref_mon, uint8_t(o_cs_cmd_latency_buffer), o_ref_abort, o_rd_pre_train_mode, o_rd_preamble, o_wr_preamble, o_ppr); return FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index 23831968a..a4c5be8c6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -27,10 +27,10 @@ /// @file mrs05.C /// @brief Run and manage the DDR4 MRS05 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -64,22 +64,22 @@ mrs05_data::mrs05_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_write_dbi(fapi2::ENUM_ATTR_EFF_WRITE_DBI_DISABLE), iv_read_dbi(fapi2::ENUM_ATTR_EFF_READ_DBI_DISABLE) { - FAPI_TRY( mss::eff_ca_parity_latency(i_target, iv_ca_parity_latency) ); - FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear) ); - FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status) ); - FAPI_TRY( mss::eff_odt_input_buff(i_target, iv_odt_input_buffer) ); - FAPI_TRY( mss::eff_dram_rtt_park(i_target, &(iv_rtt_park[0])) ); - FAPI_TRY( mss::eff_ca_parity(i_target, iv_ca_parity) ); - FAPI_TRY( mss::eff_data_mask(i_target, iv_data_mask) ); - FAPI_TRY( mss::eff_write_dbi(i_target, iv_write_dbi) ); - FAPI_TRY( mss::eff_read_dbi(i_target, iv_read_dbi) ); + FAPI_TRY( mss::eff_ca_parity_latency(i_target, iv_ca_parity_latency), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_odt_input_buff(i_target, iv_odt_input_buffer), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_dram_rtt_park(i_target, &(iv_rtt_park[0])), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_ca_parity(i_target, iv_ca_parity), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_data_mask(i_target, iv_data_mask), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_write_dbi(i_target, iv_write_dbi), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_read_dbi(i_target, iv_read_dbi), "Error in mrs05_data()" ); o_rc = fapi2::FAPI2_RC_SUCCESS; return; fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs05", mss::c_str(i_target)); return; } @@ -96,7 +96,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs05_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS05 data from attributes"); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS05 data from attributes", mss::c_str(i_target) ); FAPI_TRY( mrs05(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -148,10 +148,10 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, l_ca_parity_latency_buffer = ca_parity_latency_map[i_data.iv_ca_parity_latency]; - FAPI_INF("MR5 rank %d attributes: CAPL: 0x%x(0x%x), CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x " - "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank, - i_data.iv_ca_parity_latency, uint8_t(l_ca_parity_latency_buffer), i_data.iv_crc_error_clear, - i_data.iv_ca_parity_error_status, i_data.iv_odt_input_buffer, + FAPI_INF("%s MR5 rank %d attributes: CAPL: 0x%x(0x%x), CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x " + "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", + mss::c_str(i_target), i_rank, i_data.iv_ca_parity_latency, uint8_t(l_ca_parity_latency_buffer), + i_data.iv_crc_error_clear, i_data.iv_ca_parity_error_status, i_data.iv_odt_input_buffer, uint8_t(l_rtt_park_buffer), i_data.iv_ca_parity, i_data.iv_data_mask, i_data.iv_write_dbi, i_data.iv_read_dbi); @@ -165,7 +165,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, io_inst.arr0.writeBit<A11>(i_data.iv_write_dbi); io_inst.arr0.writeBit<A12>(i_data.iv_read_dbi); - FAPI_INF("MR5: 0x%016llx", uint64_t(io_inst.arr0)); + FAPI_INF("%s MR5: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); return fapi2::FAPI2_RC_SUCCESS; @@ -216,8 +216,8 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS o_read_dbi = i_inst.arr0.getBit<A12>(); FAPI_INF("MR5 rank %d decode: CAPL: 0x%x, CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x " - "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank, - uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status, + "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", + i_rank, uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status, o_odt_input_buffer, uint8_t(o_rtt_park_buffer), o_ca_parity, o_data_mask, o_write_dbi, o_read_dbi); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C index 3064909f3..bfc1fc885 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C @@ -27,10 +27,10 @@ /// @file mrs06.C /// @brief Run and manage the DDR4 MRS06 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -57,17 +57,17 @@ namespace ddr4 mrs06_data::mrs06_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ): iv_tccd_l(0) { - FAPI_TRY( mss::eff_vref_dq_train_value(i_target, &(iv_vrefdq_train_value[0])) ); - FAPI_TRY( mss::eff_vref_dq_train_range(i_target, &(iv_vrefdq_train_range[0])) ); - FAPI_TRY( mss::eff_vref_dq_train_enable(i_target, &(iv_vrefdq_train_enable[0])) ); - FAPI_TRY( mss::eff_dram_tccd_l(i_target, iv_tccd_l) ); + FAPI_TRY( mss::eff_vref_dq_train_value(i_target, &(iv_vrefdq_train_value[0])), "Error in mrs06_data()" ); + FAPI_TRY( mss::eff_vref_dq_train_range(i_target, &(iv_vrefdq_train_range[0])), "Error in mrs06_data()" ); + FAPI_TRY( mss::eff_vref_dq_train_enable(i_target, &(iv_vrefdq_train_enable[0])), "Error in mrs06_data()" ); + FAPI_TRY( mss::eff_dram_tccd_l(i_target, iv_tccd_l), "Error in mrs06_data()" ); o_rc = fapi2::FAPI2_RC_SUCCESS; return; fapi_try_exit: o_rc = fapi2::current_err; - FAPI_ERR("unable to get attributes for mrs0"); + FAPI_ERR("%s unable to get attributes for mrs06", mss::c_str(i_target)); return; } @@ -84,7 +84,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { // Check to make sure our ctor worked ok mrs06_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "Unable to construct MRS06 data from attributes"); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS06 data from attributes", mss::c_str(i_target) ); FAPI_TRY( mrs06(i_target, l_data, io_inst, i_rank) ); fapi_try_exit: @@ -124,14 +124,16 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, .set_PARAMETER(TCCD) .set_PARAMETER_VALUE(i_data.iv_tccd_l) .set_DIMM_IN_ERROR(i_target), - "Bad value for TCCD: %d (%s)", i_data.iv_tccd_l, mss::c_str(i_target)); + "Bad value for TCCD: %d (%s)", + i_data.iv_tccd_l, + mss::c_str(i_target)); l_tccd_l_buffer = tccd_l_map[i_data.iv_tccd_l - LOWEST_TCCD]; l_vrefdq_train_value_buffer = i_data.iv_vrefdq_train_value[mss::index(i_rank)]; - FAPI_INF("MR6 rank %d attributes: TRAIN_V: 0x%x(0x%x), TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x(0x%x)", i_rank, - i_data.iv_vrefdq_train_value[mss::index(i_rank)], uint8_t(l_vrefdq_train_value_buffer), - i_data.iv_vrefdq_train_range[mss::index(i_rank)], + FAPI_INF("%s MR6 rank %d attributes: TRAIN_V: 0x%x(0x%x), TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x(0x%x)", + mss::c_str(i_target), i_rank, i_data.iv_vrefdq_train_value[mss::index(i_rank)], + uint8_t(l_vrefdq_train_value_buffer), i_data.iv_vrefdq_train_range[mss::index(i_rank)], i_data.iv_vrefdq_train_enable[mss::index(i_rank)], i_data.iv_tccd_l, uint8_t(l_tccd_l_buffer)); mss::swizzle<A0, VREFDQ_TRAIN_LENGTH, VREFDQ_TRAIN_START>(l_vrefdq_train_value_buffer, io_inst.arr0); @@ -139,7 +141,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, io_inst.arr0.writeBit<A7>(i_data.iv_vrefdq_train_enable[mss::index(i_rank)]); mss::swizzle<A10, TCCD_L_LENGTH, TCCD_L_START>(l_tccd_l_buffer, io_inst.arr0); - FAPI_INF("MR6: 0x%016llx", uint64_t(io_inst.arr0)); + FAPI_INF("%s MR6: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); return fapi2::FAPI2_RC_SUCCESS; @@ -172,8 +174,8 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS o_vrefdq_train_enable = i_inst.arr0.getBit<A7>(); mss::swizzle<5, 3, A12>(i_inst.arr0, o_tccd_l_buffer); - FAPI_INF("MR6 rank %d decode: TRAIN_V: 0x%x, TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x", i_rank, - uint8_t(o_vrefdq_train_value_buffer), o_vrefdq_train_range, + FAPI_INF("MR6 rank %d decode: TRAIN_V: 0x%x, TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x", + i_rank, uint8_t(o_vrefdq_train_value_buffer), o_vrefdq_train_range, o_vrefdq_train_enable, uint8_t(o_tccd_l_buffer)); return FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index 22bd97ff7..a9196951b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -27,7 +27,7 @@ /// @file mrs_load_ddr4.C /// @brief Run and manage the DDR4 mrs loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 @@ -110,6 +110,8 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_t // Set this to good in case no dimms and we're running unit tests fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + o_is_needed = false; + // Loop over the DIMMs and see if A17 is needed for one of them // If so, we enable the parity bit in the PHY for (const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) @@ -119,10 +121,7 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_t bool l_temp = false; FAPI_TRY( is_a17_needed( l_dimm, l_temp), "%s Failed to get a17 boolean", mss::c_str(l_dimm) ); - if (l_temp == true) - { - o_is_needed = true; - } + o_is_needed = o_is_needed | l_temp; } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index 92e576610..d14ecc34e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_MRS_LOAD_DDR4_H_ @@ -1061,16 +1061,23 @@ inline fapi2::ReturnCode set_dram_mpr_mode(const fapi2::Target<fapi2::TARGET_TYP { constexpr uint64_t MAX_MPR_MODE = 0b1; - if(i_mode > MAX_MPR_MODE) - { - FAPI_ERR("Invalid MPR Mode recieved: %d. Max encoding allowed: %d.", i_mode, MAX_MPR_MODE); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_mode <= MAX_MPR_MODE, + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(MRS_LOAD) + .set_PARAMETER(MPR_MODE) + .set_PARAMETER_VALUE(i_mode) + .set_DIMM_IN_ERROR(i_target), + "%s Invalid MPR Mode recieved: %d. Max encoding allowed: %d.", + mss::c_str(i_target), + i_mode, + MAX_MPR_MODE); // Update field if input check passes io_data.iv_mpr_mode = i_mode; return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -1088,17 +1095,24 @@ inline fapi2::ReturnCode set_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE for (size_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) { - if(i_value[l_rank] > MAX_RTT_NOM) - { - FAPI_ERR("Invalid RTT_NOM value recieved: %d. Max encoding allowed: %d.", i_value[l_rank], MAX_RTT_NOM); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_value[l_rank] <= MAX_RTT_NOM, + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(MRS_LOAD) + .set_PARAMETER(RTT_NOM) + .set_PARAMETER_VALUE(i_value[l_rank]) + .set_DIMM_IN_ERROR(i_target), + "%s Invalid RTT_NOM value recieved: %d. Max encoding allowed: %d.", + mss::c_str(i_target), + i_value[l_rank], + MAX_RTT_NOM); // Update field if input check passes io_data.iv_rtt_nom[l_rank] = i_value[l_rank]; } return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -1116,17 +1130,24 @@ inline fapi2::ReturnCode set_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_ for (size_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) { - if(i_value[l_rank] > MAX_RTT_WR) - { - FAPI_ERR("Invalid RTT_WR value recieved: %d. Max encoding allowed: %d.", i_value[l_rank], MAX_RTT_WR); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_value[l_rank] <= MAX_RTT_WR, + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(MRS_LOAD) + .set_PARAMETER(RTT_WR) + .set_PARAMETER_VALUE(i_value[l_rank]) + .set_DIMM_IN_ERROR(i_target), + "%s Invalid RTT_WR value recieved: %d. Max encoding allowed: %d.", + mss::c_str(i_target), + i_value[l_rank], + MAX_RTT_WR); // Update field if input check passes io_data.iv_dram_rtt_wr[l_rank] = i_value[l_rank]; } return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -1142,16 +1163,23 @@ inline fapi2::ReturnCode set_dram_mpr_rd_format(const fapi2::Target<fapi2::TARGE { constexpr uint64_t MAX_READ_FORMAT = 0b10; - if(i_format > MAX_READ_FORMAT) - { - FAPI_ERR("Invalid MPR Read Format recieved: %d. Max encoding allowed: %d.", i_format, MAX_READ_FORMAT); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_format <= MAX_READ_FORMAT, + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(MRS_LOAD) + .set_PARAMETER(MPR_READ_FORMAT) + .set_PARAMETER_VALUE(i_format) + .set_DIMM_IN_ERROR(i_target), + "%s Invalid MPR Read Format recieved: %d. Max encoding allowed: %d.", + mss::c_str(i_target), + i_format, + MAX_READ_FORMAT); // Update field if input check passes io_data.iv_read_format = i_format; return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// @@ -1167,16 +1195,23 @@ inline fapi2::ReturnCode set_dram_mpr_page(const fapi2::Target<fapi2::TARGET_TYP { constexpr uint64_t MAX_PAGE = 0b11; - if(i_page > MAX_PAGE) - { - FAPI_ERR("Invalid MPR Page recieved: %d. Max encoding allowed: %d.", i_page, MAX_PAGE); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + FAPI_ASSERT( i_page <= MAX_PAGE, + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(MRS_LOAD) + .set_PARAMETER(MPR_PAGE) + .set_PARAMETER_VALUE(i_page) + .set_DIMM_IN_ERROR(i_target), + "%s Invalid MPR Page received: %d. Max encoding allowed: %d.", + mss::c_str(i_target), + i_page, + MAX_PAGE); // Update field if input check passes io_data.iv_mpr_page = i_page; return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H index 7cf49f8e2..06a13b279 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_STATE_MACHINE_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C index e69e06130..a5ff4c90b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <vector> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H index e7e546a7c..d78a512f1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_ZQCAL_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H index 0c2f1bcc7..86d5070f2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H @@ -27,10 +27,10 @@ /// @file dimm.H /// @brief Encapsulation for dimms of all types /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_DIMM_H_ @@ -174,15 +174,20 @@ class kind iv_stack_type(i_stack_type) { // Bit of an idiot-check to be sure a hand-crafted dimm::kind make sense wrt slaves, masters, packages, etc. + // Both of these are checked in eff_config. If they are messed up, they should be caught there if (iv_master_ranks > iv_total_ranks) { - FAPI_ERR("Not enough total ranks? master: %d total: %d", iv_master_ranks, iv_total_ranks); + FAPI_ERR("Not enough total ranks? master: %d total: %d", + iv_master_ranks, + iv_total_ranks); fapi2::Assert(false); } if ((iv_total_ranks % iv_master_ranks) != 0) { - FAPI_ERR("total or master ranks seems incorrect. master: %d total: %d", iv_master_ranks, iv_total_ranks); + FAPI_ERR("total or master ranks seems incorrect. master: %d total: %d", + iv_master_ranks, + iv_total_ranks); fapi2::Assert(false); } } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C index 09a161c3a..661725928 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file mrs_load.C /// @brief Run and manage the MRS_LOAD engine /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H index 7dbb16708..bcfdb2803 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H @@ -27,10 +27,10 @@ /// @file mrs_load.H /// @brief Code to support mrs_loads /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_MRS_LOAD_H_ @@ -64,7 +64,16 @@ enum mrs_bad_field RTT_PARK = 7, TCCD = 8, RANK = 9, - RTT_NOM = 10 + RTT_NOM = 10, + MPR_READ_FORMAT = 11, + RTT_WR = 12, + MPR_PAGE = 13, + MPR_MODE = 14, + + // Following is for MR_NUMBER entry into the BAD_MR_PARAM ffdc + // Set to random value so it won't be confused with an actual MR number + // This number doesn't really matter, we should be able to back track from the function numbers alone + MRS_LOAD = 100, }; /// @@ -165,22 +174,35 @@ typename std::enable_if< perform_mrs_load_overload<DEFAULT_KIND>::available, fap perform_mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); -// -// We know we registered overloads for perform_mrs_load, so we need the entry point to -// the dispatcher. Add a set of these for all TargetTypes which get overloads -// for this API -// +/// +/// @brief Function to perform mrs load overloads +/// @param[in] i_target the dimm target for the mrs's +/// @param[in,out] io_inst the MCBIST instruction +/// @note We know we registered overloads for perform_mrs_load, so we need the entry point to +/// the dispatcher. Add a set of these for all TargetTypes which get overloads +/// for this API +/// template<> fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); - +/// +/// @brief Function to perform mrs load overloads +/// @param[in] i_target the dimm target for the mrs's +/// @param[in,out] io_inst the MCBIST instruction +/// @note We know we registered overloads for perform_mrs_load, so we need the entry point to +/// the dispatcher. Add a set of these for all TargetTypes which get overloads +/// for this API +/// template<> fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); - -// -// Boilerplate dispatcher -// +/// +/// @brief Function to perform mrs load overloads +/// @param[in] i_kind the i_target's dimm_kind struct +/// @param[in] i_target the dimm target for the mrs's +/// @param[in,out] io_inst the MCBIST instruction +/// @note boilerplate +/// template< kind_t K, bool B = perform_mrs_load_overload<K>::available > inline fapi2::ReturnCode perform_mrs_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, @@ -198,7 +220,13 @@ inline fapi2::ReturnCode perform_mrs_load_dispatch( const kind_t& i_kind, return perform_mrs_load<K>(i_target, io_inst); } -// DEFAULT_KIND is 0 so this is the end of the recursion +/// +/// @brief Function to perform mrs load overloads +/// @param[in] i_kind the i_target's dimm_kind struct +/// @param[in] i_target the dimm target for the mrs's +/// @param[in,out] io_inst the MCBIST instruction +/// @note DEFAULT_KIND is 0 so this is the end of the recursion +/// template<> inline fapi2::ReturnCode perform_mrs_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C index 6d444c574..6404adf0b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C @@ -25,9 +25,9 @@ /// /// @file rank.C -/// @brief Manage dIMM ranks +/// @brief Manage DIMM ranks /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H index 8c214acc1..9aa3f8e74 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H @@ -27,7 +27,7 @@ /// @file rank.H /// @brief Do things with or for ranks /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 @@ -560,7 +560,8 @@ inline fapi2::ReturnCode map_rank_pair_from_phy( const fapi2::Target<fapi2::TARG fapi2::MSS_NO_DIMM_FOR_MAPPING() .set_FUNCTION(RANK_PAIR_FROM_PHY) .set_MCA_TARGET(i_target), - "Tried to map rank pairs on a port without any DIMMs"); + "%s Tried to map rank pairs on a port without any DIMMs", + mss::c_str(i_target)); // copy over so we get the valid bits io_data = i_rp_reg_value; @@ -727,7 +728,7 @@ inline fapi2::ReturnCode read_rank_pair_reg( const fapi2::Target<T>& i_target, f fapi2::buffer<uint64_t> l_buf; static_assert((N < TT::NUM_RANK_PAIR_REGS), "Rank pair register index failed range check"); FAPI_TRY( mss::getScom(i_target, TT::RANK_PAIR_REGS[N], l_buf) ); - FAPI_INF("read_rank_pair_reg: 0x%016lx", l_buf); + FAPI_INF("%s read_rank_pair_reg: 0x%016lx", mss::c_str(i_target), l_buf); FAPI_TRY( map_rank_pair_from_phy(i_target, l_buf, o_data) ); fapi_try_exit: return fapi2::current_err; @@ -750,7 +751,7 @@ inline fapi2::ReturnCode write_rank_pair_reg( const fapi2::Target<T>& i_target, static_assert((N < TT::NUM_RANK_PAIR_REGS), "Rank pair register index failed range check"); FAPI_TRY( map_rank_pair_to_phy(i_target, i_data, l_buf) ); FAPI_TRY( mss::putScom(i_target, TT::RANK_PAIR_REGS[N], l_buf) ); - FAPI_INF("write_rank_pair_reg: 0x%016lx", l_buf); + FAPI_INF("%s write_rank_pair_reg: 0x%016lx", mss::c_str(i_target), l_buf); fapi_try_exit: return fapi2::current_err; } @@ -767,7 +768,7 @@ template< fapi2::TargetType T, typename TT = rankPairTraits<T, 0> > inline fapi2::ReturnCode read_rank_group( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) { FAPI_TRY( mss::getScom(i_target, TT::RANK_GROUP, o_data) ); - FAPI_INF("read_rank_group: 0x%016lx", o_data); + FAPI_INF("%s read_rank_group: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -784,7 +785,7 @@ template< fapi2::TargetType T, typename TT = rankPairTraits<T, 0> > inline fapi2::ReturnCode write_rank_group( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { FAPI_TRY( mss::putScom(i_target, TT::RANK_GROUP, i_data) ); - FAPI_INF("write_rank_group: 0x%016lx", i_data); + FAPI_INF("%s write_rank_group: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } @@ -801,7 +802,7 @@ template< fapi2::TargetType T, typename TT = rankPairTraits<T, 0> > inline fapi2::ReturnCode read_rank_group_ext( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) { FAPI_TRY( mss::getScom(i_target, TT::RANK_GROUP_EXT, o_data) ); - FAPI_INF("read_rank_group_ext: 0x%016lx", o_data); + FAPI_INF("%s read_rank_group_ext: 0x%016lx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -818,7 +819,7 @@ template< fapi2::TargetType T, typename TT = rankPairTraits<T, 0> > inline fapi2::ReturnCode write_rank_group_ext( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { FAPI_TRY( mss::putScom(i_target, TT::RANK_GROUP_EXT, i_data) ); - FAPI_INF("write_rank_group_ext: 0x%016lx", i_data); + FAPI_INF("%s write_rank_group_ext: 0x%016lx", mss::c_str(i_target), i_data); fapi_try_exit: return fapi2::current_err; } @@ -1132,8 +1133,8 @@ fapi2::ReturnCode set_ranks_in_pair( const fapi2::Target<T>& i_target, .set_RANK_SIZE(i_ranks.size()) .set_MCA_TARGET(i_target) .set_FUNCTION(SET_RANKS_IN_PAIR), - "%s Invalid vector of ranks passed in ", - mss::c_str(i_target)); + "%s Invalid vector of ranks passed in (%d) ", + mss::c_str(i_target), i_ranks.size()); // Use the reg API here so we get the PHY to MC rank conversion FAPI_TRY( (mss::rank::read_rank_pair_reg< RP, 0 >(i_target, l_reg)) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C index 92d9ac1f9..0537508c9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file rcd_load.C /// @brief Run and manage the RCD_LOAD engine /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -38,6 +38,7 @@ #include <mss.H> #include <lib/dimm/rcd_load.H> #include <lib/dimm/rcd_load_ddr4.H> +#include <generic/memory/lib/utils/find.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -64,21 +65,18 @@ fapi2::ReturnCode rcd_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_ l_program.iv_poll.iv_initial_delay = 0; l_program.iv_poll.iv_initial_sim_delay = 0; - for (auto c : i_target.getChildren<TARGET_TYPE_MCS>()) + for (const auto& p : find_targets<TARGET_TYPE_MCA>(i_target)) { - for (auto p : c.getChildren<TARGET_TYPE_MCA>()) + for (const auto& d : find_targets<TARGET_TYPE_DIMM>(p)) { - for (auto d : p.getChildren<TARGET_TYPE_DIMM>()) - { - FAPI_DBG("rcd load for %s", mss::c_str(d)); - FAPI_TRY( perform_rcd_load(d, l_program.iv_instructions) ); - } - - // We have to configure the CCS engine to let it know which port these instructions are - // going out (or whether it's broadcast ...) so lets execute the instructions we presently - // have so that we kind of do this by port - FAPI_TRY( ccs::execute(i_target, l_program, p) ); + FAPI_DBG("rcd load for %s", mss::c_str(d)); + FAPI_TRY( perform_rcd_load(d, l_program.iv_instructions) ); } + + // We have to configure the CCS engine to let it know which port these instructions are + // going out (or whether it's broadcast ...) so lets execute the instructions we presently + // have so that we kind of do this by port + FAPI_TRY( ccs::execute(i_target, l_program, p) ); } fapi_try_exit: @@ -101,7 +99,7 @@ fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYP FAPI_TRY( mss::eff_dimm_type(i_target, l_type) ); FAPI_TRY( mss::eff_dram_gen(i_target, l_gen) ); - // If we're here, we have a problem. The DIMM kind (type and/or generation) wasn't know + // If we're here, we have a problem. The DIMM kind (type and/or generation) wasn't known // to our dispatcher. We have a DIMM plugged in we don't know how to deal with. FAPI_ASSERT(false, fapi2::MSS_UNKNOWN_DIMM() diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H index f572d6389..b9ee410d6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H @@ -27,10 +27,10 @@ /// @file rcd_load.H /// @brief Code to support rcd_loads /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_RCD_LOAD_H_ @@ -55,7 +55,6 @@ namespace mss template< fapi2::TargetType T > fapi2::ReturnCode rcd_load( const fapi2::Target<T>& i_target ); - // // Implement the polymorphism for rcd_load // @@ -128,9 +127,13 @@ template<> fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); -// -// Boilerplate dispatcher -// +/// +/// @brief Start the rcd_load_dispatch boilerplate -- specialization for recursion dispatcher +/// @param[in] i_kind the dimm kind struct for i_target +/// @param[in] i_target a fapi2::Target<TARGET_TYPE_DIMM> +/// @param[in] i_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// template< kind_t K, bool B = perform_rcd_load_overload<K>::available > inline fapi2::ReturnCode perform_rcd_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, @@ -148,7 +151,14 @@ inline fapi2::ReturnCode perform_rcd_load_dispatch( const kind_t& i_kind, return perform_rcd_load<K>(i_target, i_inst); } -// DEFAULT_KIND is 0 so this is the end of the recursion +/// +/// @brief Start the rcd_load_dispatch boilerplate -- specialization for recursion root +/// @param[in] i_kind the dimm kind struct for i_target +/// @param[in] i_target a fapi2::Target<TARGET_TYPE_DIMM> +/// @param[in] i_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note DEFAULT_KIND is 0 so this is the end of the recursion +/// template<> inline fapi2::ReturnCode perform_rcd_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C index db5a92e8a..f645df4e7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C @@ -27,10 +27,10 @@ /// @file rcd_load_ddr4.C /// @brief Run and manage the DDR4 rcd loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -53,7 +53,7 @@ namespace mss /// /// @brief Perform the rcd_load_ddr4 operations - TARGET_TYPE_DIMM specialization /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] a vector of CCS instructions we should add to +/// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H index 6a73da77a..efd91cc1e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H @@ -27,10 +27,10 @@ /// @file rcd_load_ddr4.H /// @brief Code to support rcd_load_ddr4 /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_RCD_LOAD_DDR4_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index a28bb5864..2fe69479e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -27,10 +27,10 @@ /// @file mc.C /// @brief Subroutines to manipulate the memory controller /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -88,8 +88,8 @@ fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& uint8_t l_pwr_cntrl = 0; fapi2::buffer<uint64_t> l_data; - FAPI_TRY(mrw_power_control_requested(l_pwr_cntrl)); - FAPI_TRY(mss::getScom(i_target, MCA_MBARPC0Q, l_data)); + FAPI_TRY(mrw_power_control_requested(l_pwr_cntrl), "Error in set_pwr_cntrl_reg"); + FAPI_TRY(mss::getScom(i_target, MCA_MBARPC0Q, l_data), "Error in set_pwr_cntrl_reg"); l_data.insertFromRight<TT::CFG_MIN_MAX_DOMAINS, TT::CFG_MIN_MAX_DOMAINS_LEN>(MAXALL_MINALL); @@ -117,7 +117,7 @@ fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& l_data.insertFromRight<TT::MIN_DOMAIN_REDUCTION_TIME, TT::MIN_DOMAIN_REDUCTION_TIME_LEN> (MIN_DOMAIN_REDUCTION_TIME); - FAPI_TRY(mss::putScom(i_target, MCA_MBARPC0Q, l_data) ); + FAPI_TRY(mss::putScom(i_target, MCA_MBARPC0Q, l_data), "Error in set_pwr_cntrl_reg" ); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: @@ -137,8 +137,8 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_tar uint8_t l_str_enable = 0; fapi2::buffer<uint64_t> l_data; - FAPI_TRY(mrw_power_control_requested(l_str_enable)); - FAPI_TRY(mss::getScom(i_target, MCA_MBASTR0Q, l_data)); + FAPI_TRY(mrw_power_control_requested(l_str_enable), "Error in set_pwr_cntrl_reg"); + FAPI_TRY(mss::getScom(i_target, MCA_MBASTR0Q, l_data), "Error in set_pwr_cntrl_reg"); //Write bit if STR should be enabled switch (l_str_enable) @@ -169,7 +169,7 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_tar l_data.insertFromRight<TT::ENTER_STR_TIME_POS, TT::ENTER_STR_TIME_LEN>(ENTER_STR_TIME); - FAPI_TRY(mss::putScom(i_target, MCA_MBASTR0Q, l_data) ); + FAPI_TRY(mss::putScom(i_target, MCA_MBASTR0Q, l_data), "Error in set_str_reg" ); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: @@ -195,15 +195,15 @@ fapi2::ReturnCode set_nm_support (const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i fapi2::buffer<uint64_t> l_data; //runtime should be calculated in eff_config_thermal, which is called before scominit in ipl - FAPI_TRY(runtime_mem_throttled_n_commands_per_port(i_target, l_run_port)); - FAPI_TRY(runtime_mem_throttled_n_commands_per_slot(i_target, l_run_slot)); - FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator) ); + FAPI_TRY(runtime_mem_throttled_n_commands_per_port(i_target, l_run_port), "Error in set_nm_support"); + FAPI_TRY(runtime_mem_throttled_n_commands_per_slot(i_target, l_run_slot), "Error in set_nm_support"); + FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator), "Error in set_nm_support" ); FAPI_INF("For target %s throttled n commands per port are %d, per slot are %d, and dram m clocks are %d", mss::c_str(i_target), l_run_port, l_run_slot, l_throttle_denominator); - FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data)); + FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data), "Error in set_nm_support"); l_data.insertFromRight<TT::RUNTIME_N_SLOT, TT::RUNTIME_N_SLOT_LEN>(l_run_slot); l_data.insertFromRight<TT::RUNTIME_N_PORT, TT::RUNTIME_N_PORT_LEN>(l_run_port); @@ -215,7 +215,7 @@ fapi2::ReturnCode set_nm_support (const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i // Set to disable permanently due to hardware design bug (HW403028) that won't be changed l_data.writeBit<TT::NM_CHANGE_AFTER_SYNC>(CHANGE_AFTER_SYNC_OFF); - FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB3Q, l_data) ); + FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB3Q, l_data), "Error in set_nm_support" ); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: @@ -238,13 +238,13 @@ fapi2::ReturnCode set_safemode_throttles(const fapi2::Target<fapi2::TARGET_TYPE_ uint16_t l_throttle_per_slot = 0; uint32_t l_throttle_denominator = 0; - FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator) ); - FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_slot) ); - FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB4Q, l_data) ); + FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator), "Error in set_safemode_throttles" ); + FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_slot), "Error in set_safemode_throttles" ); + FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB4Q, l_data), "Error in set_safemode_throttles" ); l_data.insertFromRight<TT::EMERGENCY_M, TT::EMERGENCY_M_LEN>(l_throttle_denominator); l_data.insertFromRight<TT::EMERGENCY_N, TT::EMERGENCY_N_LEN>(l_throttle_per_slot); - FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB4Q, l_data) ); + FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB4Q, l_data), "Error in set_safemode_throttles" ); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: @@ -268,16 +268,16 @@ fapi2::ReturnCode set_runtime_throttles_to_safe(const fapi2::Target<fapi2::TARGE uint16_t l_throttle_per_port = 0; uint32_t l_throttle_denominator = 0; - FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator) ); - FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_port) ); - FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data) ); + FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator), "Error in set_safemode_throttles" ); + FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_port), "Error in set_safemode_throttles" ); + FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data), "Error in set_safemode_throttles" ); //Same value for both throttles l_data.insertFromRight<TT::RUNTIME_N_SLOT, TT::RUNTIME_N_SLOT_LEN>(l_throttle_per_port); l_data.insertFromRight<TT::RUNTIME_N_PORT, TT::RUNTIME_N_PORT_LEN>(l_throttle_per_port); l_data.insertFromRight<TT::RUNTIME_M, TT::RUNTIME_M_LEN>(l_throttle_denominator); - FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB3Q, l_data) ); + FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB3Q, l_data), "Error in set_safemode_throttles" ); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: @@ -293,10 +293,10 @@ fapi_try_exit: /// fapi2::ReturnCode thermal_throttle_scominit (const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) { - FAPI_TRY(set_pwr_cntrl_reg(i_target)); - FAPI_TRY(set_str_reg(i_target)); - FAPI_TRY(set_nm_support(i_target)); - FAPI_TRY(set_safemode_throttles(i_target)); + FAPI_TRY(set_pwr_cntrl_reg(i_target), "Error in thermal_throttle_scominit"); + FAPI_TRY(set_str_reg(i_target), "Error in thermal_throttle_scominit"); + FAPI_TRY(set_nm_support(i_target), "Error in thermal_throttle_scominit"); + FAPI_TRY(set_safemode_throttles(i_target), "Error in thermal_throttle_scominit"); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H index dde8e88c7..32303b539 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H @@ -27,10 +27,10 @@ /// @file mc.H /// @brief Subroutines to manipulate the memory controller /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_MC_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C index 4fc25aa76..eaf787bbc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C @@ -62,11 +62,11 @@ fapi2::ReturnCode fir_check(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_targe FAPI_TRY( read_error_status0(i_target, l_data) ); FAPI_ASSERT( l_data.getBit<TT::INVALID_ADDRESS>() == false, - fapi2::MSS_APB_INVALID_ADDRESS().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_APB_INVALID_ADDRESS().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting an invalid address on %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::WRITE_PARITY_ERR>() == false, - fapi2::MSS_APB_WR_PAR_ERR().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_APB_WR_PAR_ERR().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a read/write parity error on %s", mss::c_str(i_target) ); } @@ -76,28 +76,28 @@ fapi2::ReturnCode fir_check(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_targe FAPI_TRY( read_fir_err0(i_target, l_data) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_FSM>() == false, - fapi2::MSS_FATAL_FSM_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_FSM_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a fatal FSM error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_PARITY>() == false, - fapi2::MSS_FATAL_PARITY_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_PARITY_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a fatal parity error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FSM>() == false, - fapi2::MSS_FSM_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FSM_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a recoverable FSM error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::PARITY>() == false, - fapi2::MSS_PARITY_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_PARITY_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a recoverable parity error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_ADR52_MASTER>() == false, - fapi2::MSS_FATAL_ADR52_MASTER().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_ADR52_MASTER().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a fatal register parity error in ADR52 master side logic %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_ADR52_SLAVE>() == false, - fapi2::MSS_FATAL_ADR52_SLAVE().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_ADR52_SLAVE().set_PORT_POSITION(mss::fapi_pos(i_target)).set_MCA_TARGET(i_target), "APB interface is reporting a fatal register parity error in ADR52 slave side logic %s", mss::c_str(i_target) ); @@ -106,7 +106,7 @@ fapi2::ReturnCode fir_check(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_targe fapi2::MSS_FSM_DP16() .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_DP16_POSITION(l_dp16) - .set_TARGET_IN_ERROR(i_target), + .set_MCA_TARGET(i_target), "APB interface is reporting a recoverable FSM state checker error in DP16 %s 0x%x", mss::c_str(i_target), l_dp16 ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C index ff353cb28..f53f085d3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H index 9080fa387..4a3678578 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index d510d4fee..a0bc1c84f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -112,7 +112,8 @@ extern "C" { FAPI_INF( "starting DLL calibration %s", mss::c_str(i_target) ); bool l_run_workaround = false; - fapi2::ReturnCode l_rc = mss::dll_calibration(i_target, l_run_workaround); + FAPI_TRY( mss::dll_calibration(i_target, l_run_workaround), "%s Error in p9_mss_ddr_phy_reset.C", + mss::c_str(i_target) ); // Only run DLL workaround if we fail DLL cal // Note: there is no EC workaround for this workaround @@ -120,10 +121,9 @@ extern "C" if( l_run_workaround ) { FAPI_INF( "%s Applying DLL workaround", mss::c_str(i_target) ); - l_rc = mss::workarounds::dll::fix_bad_voltage_settings(i_target); + FAPI_TRY( mss::workarounds::dll::fix_bad_voltage_settings(i_target), "%s Error in p9_mss_ddr_phy_reset.C", + mss::c_str(i_target) ); } - - FAPI_TRY( l_rc, "Failed DLL calibration" ); } // @@ -132,7 +132,8 @@ extern "C" // 16. Take dphy_nclk/SysClk alignment circuits out of reset and put into continuous update mode, FAPI_INF("set up of phase rotator controls %s", mss::c_str(i_target) ); - FAPI_TRY( mss::setup_phase_rotator_control_registers(i_target, mss::ON) ); + FAPI_TRY( mss::setup_phase_rotator_control_registers(i_target, mss::ON), "%s Error in p9_mss_ddr_phy_reset.C", + mss::c_str(i_target) ); // 17. Wait at least 5932 dphy_nclk clock cycles to allow the dphy_nclk/SysClk alignment circuit to // perform initial alignment. @@ -142,11 +143,12 @@ extern "C" // 18. Check for LOCK in DDRPHY_DP16_SYSCLK_PR_VALUE registers and DDRPHY_ADR_SYSCLK_PR_VALUE FAPI_INF("Checking for bang-bang lock %s ...", mss::c_str(i_target)); - FAPI_TRY( mss::check_bang_bang_lock(i_target) ); + FAPI_TRY( mss::check_bang_bang_lock(i_target), "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); // 19. Write 0b0 into the DDRPHY_PC_RESETS register bit 1. This write de-asserts the SYSCLK_RESET. FAPI_INF("deassert sysclk reset %s", mss::c_str(i_target)); - FAPI_TRY( mss::deassert_sysclk_reset(i_target), "deassert_sysclk_reset failed for %s", mss::c_str(i_target) ); + FAPI_TRY( mss::deassert_sysclk_reset(i_target), "deassert_sysclk_reset failed for %s", mss::c_str(i_target), + "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); // 20. Write 8020h into the DDRPHY_ADR_SYSCLK_CNTL_PR Registers and // DDRPHY_DP16_SYSCLK_PR0/1 registers This write takes the dphy_nclk/ @@ -157,7 +159,8 @@ extern "C" // 21. Wait at least 32 dphy_nclk clock cycles. FAPI_DBG("Wait at least 32 memory clock cycles %s", mss::c_str(i_target)); - FAPI_TRY( fapi2::delay(mss::cycles_to_ns(i_target, 32), mss::cycles_to_simcycles(32)) ); + FAPI_TRY( fapi2::delay(mss::cycles_to_ns(i_target, 32), mss::cycles_to_simcycles(32)), + "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); // // Done bang-bang-lock @@ -168,11 +171,13 @@ extern "C" "force_mclk_low (set low) Failed rc = 0x%08X", uint64_t(fapi2::current_err) ); // Workarounds - FAPI_TRY( mss::workarounds::dp16::after_phy_reset(i_target) ); + FAPI_TRY( mss::workarounds::dp16::after_phy_reset(i_target), "%s Error in p9_mss_ddr_phy_reset.C", + mss::c_str(i_target) ); // New for Nimbus - perform duty cycle clock distortion calibration (DCD cal) // Per PHY team's characterization, the DCD cal needs to be run after DLL calibration - FAPI_TRY( mss::adr32s::duty_cycle_distortion_calibration(i_target) ); + FAPI_TRY( mss::adr32s::duty_cycle_distortion_calibration(i_target), "%s Error in p9_mss_ddr_phy_reset.C", + mss::c_str(i_target) ); // mss::check::during_phy_reset checks to see if there are any FIR. We do this 'twice' once here // (as part of the good-path) and once if we jump to the fapi_try label. @@ -185,7 +190,7 @@ extern "C" // The algorithm is 'good path do after_phy_reset, all paths (error or not) perform the checks // which are defined in during_phy_reset'. We won't run after_phy_reset (unmask of FIR) unless // we're done with a success. - FAPI_TRY( mss::unmask::after_phy_reset(i_target) ); + FAPI_TRY( mss::unmask::after_phy_reset(i_target), "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); // Leave as we're all good and checked the FIR already ... return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index f67f2a7ff..6b79f1ac5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -27,10 +27,10 @@ /// @file p9_mss_draminit.C /// @brief Initialize dram /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob L Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -93,7 +93,9 @@ extern "C" { fapi2::buffer<uint64_t> l_ccs_config; - FAPI_TRY( mss::ccs::read_mode(i_target, l_ccs_config) ); + FAPI_TRY( mss::ccs::read_mode(i_target, l_ccs_config), + "%s Failed ccs read_mode in p9_mss_draminit", + mss::c_str(i_target) ); // It's unclear if we want to run with this true or false. Right now (10/15) this // has to be false. Shelton was unclear if this should be on or off in general BRS @@ -102,7 +104,9 @@ extern "C" mss::ccs::copy_cke_to_spare_cke(i_target, l_ccs_config, mss::HIGH); mss::ccs::parity_after_cmd(i_target, l_ccs_config, mss::HIGH); - FAPI_TRY( mss::ccs::write_mode(i_target, l_ccs_config) ); + FAPI_TRY( mss::ccs::write_mode(i_target, l_ccs_config), + "%s Failed ccs write_mode in p9_mss_draminit", + mss::c_str(i_target) ); } // We initialize dram by iterating over the (ungarded) ports. We could allow the caller @@ -118,17 +122,22 @@ extern "C" // for (const auto& p : l_mca) { - FAPI_TRY( mss::draminit_entry_invariant(p) ); + FAPI_TRY( mss::draminit_entry_invariant(p), + "%s Failed mss::draminit_entry_invariant in p9_mss_draminit", + mss::c_str(i_target) ); // Begin driving mem clks, and wait 10ns (we'll do this outside the loop) // From the RCD Spec, before the DRST_n (resetn) input is pulled HIGH the // clock input signal must be stable. - FAPI_TRY( mss::drive_mem_clks(p, PCLK_INITIAL_VALUE, NCLK_INITIAL_VALUE) ); + FAPI_TRY( mss::drive_mem_clks(p, PCLK_INITIAL_VALUE, NCLK_INITIAL_VALUE), + "%s Failed mss::drive_mem_clks in p9_mss_draminit", mss::c_str(i_target) ); // After RESET_n is de-asserted, wait for another 500us until CKE becomes active. // During this time, the DRAM will start internal initialization; this will be done // independently of external clocks. - FAPI_TRY( mss::ddr_resetn(p, mss::HIGH) ); + FAPI_TRY( mss::ddr_resetn(p, mss::HIGH), + "%s Failed mss::resetn in p9_mss_draminit", + mss::c_str(i_target) ); } // From the DDR4 JEDEC Spec (79-A): Power-up Initialization Sequence @@ -143,7 +152,9 @@ extern "C" const uint64_t l_delay_in_cycles = mss::ns_to_cycles(i_target, l_delay_in_ns); // Set our delay (for HW and SIM) - FAPI_TRY( fapi2::delay(l_delay_in_ns, mss::cycles_to_simcycles(l_delay_in_cycles)) ); + FAPI_TRY( fapi2::delay(l_delay_in_ns, mss::cycles_to_simcycles(l_delay_in_cycles)), + "%s Failed delay in p9_mss_draminit", + mss::c_str(i_target) ); } // Also a Deselect command must be registered as required from the Spec. @@ -152,23 +163,33 @@ extern "C" // we'll PDE/DES all DIMM at the same time. l_des.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(400); l_program.iv_instructions.push_back(l_des); - FAPI_TRY( mss::ccs::execute(i_target, l_program, l_mca[0]) ); + FAPI_TRY( mss::ccs::execute(i_target, l_program, l_mca[0]), + "%s Failed execute in p9_mss_draminit", + mss::c_str(i_target) ); // Per conversation with Shelton and Steve 10/9/15, turn off addr_mux_sel after the CKE CCS but // before the RCD/MRS CCSs for (const auto& p : l_mca) { - FAPI_TRY( change_addr_mux_sel(p, mss::LOW) ); + FAPI_TRY( change_addr_mux_sel(p, mss::LOW), + "%s Failed change_addr_mux_sel in p9_mss_draminit", + mss::c_str(i_target) ); } // Load RCD control words - FAPI_TRY( mss::rcd_load(i_target) ); + FAPI_TRY( mss::rcd_load(i_target), + "%s Failed rcd_load in p9_mss_draminit", + mss::c_str(i_target) ); // Load data buffer control words (BCW) - FAPI_TRY( mss::bcw_load(i_target) ); + FAPI_TRY( mss::bcw_load(i_target), + "%s Failed bcw_load in p9_mss_draminit", + mss::c_str(i_target) ); // Load MRS - FAPI_TRY( mss::mrs_load(i_target) ); + FAPI_TRY( mss::mrs_load(i_target), + "%s Failed mrs_load in p9_mss_draminit", + mss::c_str(i_target) ); fapi_try_exit: FAPI_INF("End draminit: %s (0x%lx)", mss::c_str(i_target), uint64_t(fapi2::current_err)); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H index 581afe009..04a387c49 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file p9_mss_draminit.H /// @brief Reset and initialze DRAM /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_DRAMINIT__ diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index b7201a6fc..930e037b5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -27,10 +27,10 @@ /// @file p9_mss_draminit_mc.C /// @brief Initialize the memory controller to take over the DRAM /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -67,13 +67,8 @@ extern "C" continue; } - // Don't do this yet - leverage the sim inits for the moment -#if 0 - // All the scominit for this MCA - l_mc.scominit(p); -#endif // Setup the MC port/dimm address translation registers - FAPI_TRY( mss::mc::setup_xlate_map(p) ); + FAPI_TRY( mss::mc::setup_xlate_map(p), "%s Failed setup_xlate_map", mss::c_str(i_target) ); // Setup the read_pointer_delay // TK: Do we need to do this in general or is this a place holder until the @@ -112,40 +107,42 @@ extern "C" // Reset addr_mux_sel to “0” to allow the MCA to take control of the DDR interface over from CCS. // (Note: this step must remain in this procedure to ensure that data path is placed into mainline - // mode prior to running memory diagnostics. This step maybe superfluous but not harmful.) + // mode prior to running memory diagnostics. This step may be superfluous but not harmful.) // Note: addr_mux_sel is set low in p9_mss_draminit(), however that might be a work-around so we // set it low here kind of like belt-and-suspenders. BRS - FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW) ); + FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW), + "%s Failed to change_addr_mux_sel", mss::c_str(i_target) ); // Re-enable port fails. Turned off in draminit_training - FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ) ); + FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ), + "%s Failed to change_port_fail_disable", mss::c_str(i_target) ); // MC work around for OE bug (seen in periodics + PHY) #ifndef REMOVE_FOR_DD2 // Turn on output-enable always on. Shelton tells me they'll fix for DD2 - FAPI_TRY( mss::change_oe_always_on(p, mss::ON ) ); + FAPI_TRY( mss::change_oe_always_on(p, mss::ON ), "%s Failed to change_oe_always_on", mss::c_str(i_target) ); #endif // Step Two.1: Check RCD protect time on RDIMM and LRDIMM // Step Two.2: Enable address inversion on each MBA for ALL CARDS // Start the refresh engines by setting MBAREF0Q(0) = “1”. Note that the remaining bits in // MBAREF0Q should retain their initialization values. - FAPI_TRY( mss::change_refresh_enable(p, mss::HIGH) ); + FAPI_TRY( mss::change_refresh_enable(p, mss::HIGH), "%s Failed change_refresh_enable", mss::c_str(i_target) ); // Power management is handled in the init file. (or should be BRS) // Enabling periodic calibration - FAPI_TRY( mss::enable_periodic_cal(p) ); + FAPI_TRY( mss::enable_periodic_cal(p), "%s Failed enable_periodic_cal", mss::c_str(i_target) ); // Step Six: Setup Control Bit ECC - FAPI_TRY( mss::enable_read_ecc(p) ); + FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // apply marks from MVPD - FAPI_TRY( mss::apply_mark_store(p) ); + FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); } // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. - FAPI_TRY( mss::unmask::after_draminit_mc(i_target) ); + FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) ); fapi_try_exit: FAPI_INF("End draminit MC"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H index 89e59a5ad..1a766b715 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,10 +26,10 @@ /// @file p9_mss_draminit_mc.H /// @brief Initialize the memory controller to take over the DRAM /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_DRAMINIT_MC__ diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index f2ee76321..94d63b82b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -27,7 +27,7 @@ /// @file p9_mss_draminit_training.C /// @brief Train dram /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 @@ -78,13 +78,14 @@ extern "C" } uint8_t l_reset_disable = 0; - FAPI_TRY( mss::mrw_reset_delay_before_cal(l_reset_disable) ); + FAPI_TRY( mss::mrw_reset_delay_before_cal(l_reset_disable), "%s Error in p9_mss_draminit_training", + mss::c_str(i_target) ); // Configure the CCS engine. { fapi2::buffer<uint64_t> l_ccs_config; - FAPI_TRY( mss::ccs::read_mode(i_target, l_ccs_config) ); + FAPI_TRY( mss::ccs::read_mode(i_target, l_ccs_config), "%s Error in p9_mss_draminit_training", mss::c_str(i_target) ); // It's unclear if we want to run with this true or false. Right now (10/15) this // has to be false. Shelton was unclear if this should be on or off in general BRS @@ -95,7 +96,7 @@ extern "C" // Hm. Centaur sets this up for the longest duration possible. Can we do better? mss::ccs::cal_count(i_target, l_ccs_config, ~0, ~0); - FAPI_TRY( mss::ccs::write_mode(i_target, l_ccs_config) ); + FAPI_TRY( mss::ccs::write_mode(i_target, l_ccs_config), "%s Error in p9_mss_draminit_training", mss::c_str(i_target) ); } // Clean out any previous calibration results, set bad-bits and configure the ranks. @@ -114,20 +115,20 @@ extern "C" // if the i_specal_training bits have not been specified. if (i_special_training == 0) { - FAPI_TRY( mss::cal_step_enable(p, l_cal_steps_enabled) ); + FAPI_TRY( mss::cal_step_enable(p, l_cal_steps_enabled), "Error in p9_mss_draminit_training" ); } FAPI_DBG("cal steps enabled: 0x%x special training: 0x%x", l_cal_steps_enabled, i_special_training); // ZQCAL (for DRAMs and LRDIMM data buffers) isn't a PHY calibration, // so we don't add it in the PHY calibration setup and do it separately here. - FAPI_TRY( mss::setup_and_execute_zqcal(p, l_cal_steps_enabled) ); + FAPI_TRY( mss::setup_and_execute_zqcal(p, l_cal_steps_enabled), "Error in p9_mss_draminit_training" ); FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, 0) ); // Disable port fails as it doesn't appear the MC handles initial cal timeouts // correctly (cal_length.) BRS, see conversation with Brad Michael - FAPI_TRY( mss::change_port_fail_disable(p, mss::ON ) ); + FAPI_TRY( mss::change_port_fail_disable(p, mss::ON ), "Error in p9_mss_draminit_training" ); // The following registers must be configured to the correct operating environment: @@ -138,7 +139,7 @@ extern "C" // Section 5.2.6.3 WC Configuration 2 Register on page 438 // Get our rank pairs. - FAPI_TRY( mss::rank::get_rank_pairs(p, l_pairs) ); + FAPI_TRY( mss::rank::get_rank_pairs(p, l_pairs), "Error in p9_mss_draminit_training" ); // Hits the resets iff zqcal is set so we don't unnecessarily reset errors if ((l_cal_steps_enabled.getBit<mss::cal_steps::DRAM_ZQCAL>()) || @@ -152,13 +153,13 @@ extern "C" if ((l_reset_disable == fapi2::ENUM_ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL_YES) && (i_special_training == 0)) { FAPI_INF("resetting delay values before cal %s", mss::c_str(p)); - FAPI_TRY( mss::dp16::reset_delay_values(p, l_pairs) ); + FAPI_TRY( mss::dp16::reset_delay_values(p, l_pairs), "Error in p9_mss_draminit_training" ); } FAPI_DBG("generating calibration CCS instructions: %d rank-pairs", l_pairs.size()); // Turn on refresh for training - FAPI_TRY( mss::workarounds::dqs_align::turn_on_refresh(p) ); + FAPI_TRY( mss::workarounds::dqs_align::turn_on_refresh(p), "Error in p9_mss_draminit_training" ); // For each rank pair we need to calibrate, pop a ccs instruction in an array and execute it. // NOTE: IF YOU CALIBRATE MORE THAN ONE RANK PAIR PER CCS PROGRAM, MAKE SURE TO CHANGE @@ -169,11 +170,12 @@ extern "C" if (i_abort_on_error == CAL_ABORT_SENTINAL) { - FAPI_TRY( mss::cal_abort_on_error(l_cal_abort_on_error) ); + FAPI_TRY( mss::cal_abort_on_error(l_cal_abort_on_error), "Error in p9_mss_draminit_training" ); } // Execute selected cal steps - FAPI_TRY( mss::setup_and_execute_cal(p, rp, l_cal_steps_enabled, l_cal_abort_on_error) ); + FAPI_TRY( mss::setup_and_execute_cal(p, rp, l_cal_steps_enabled, l_cal_abort_on_error), + "Error in p9_mss_draminit_training" ); fapi2::ReturnCode l_rc (fapi2::current_err); @@ -244,7 +246,7 @@ extern "C" #endif // Unmask FIR - FAPI_TRY( mss::unmask::after_draminit_training(i_target) ); + FAPI_TRY( mss::unmask::after_draminit_training(i_target), "Error in p9_mss_draminit" ); fapi_try_exit: FAPI_INF("End draminit training"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H index 62dc6a4c1..e6d14ddf1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.H @@ -26,10 +26,10 @@ /// @file p9_mss_draminit_training.H /// @brief Train DRAM /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_DRAMINIT_TRAINING__ diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C index 6a0a84923..2ecfd2443 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C @@ -28,9 +28,9 @@ /// @brief configure and start the OCC and thermal cache /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H index 1a8069d0b..2d3e1fa24 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,9 +28,9 @@ /// @brief configure and start the OCC and thermal cache /// // *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_THERMAL_INIT__ diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml index ec8567315..f8177810c 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml @@ -27,10 +27,10 @@ <!-- @file memory_mss_draminit.xml --> <!-- @brief Error xml for draminit --> <!-- --> -<!-- *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> --> +<!-- *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> --> <!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> <!-- *HWP Team: Memory --> -<!-- *HWP Level: 2 --> +<!-- *HWP Level: 3--> <!-- *HWP Consumed by: HB:FSP --> <!-- --> @@ -39,41 +39,53 @@ <hwpError> <rc>RC_MSS_UNKNOWN_DIMM</rc> <description> - This DIMM's type or DRAM generation are not supported by the system + This DIMM's type (RDIMM, LRDIMM, etc) or DRAM generation (DDR3, DDR4, etc) are not supported by the system </description> <ffdc>DIMM_TYPE</ffdc> <ffdc>DRAM_GEN</ffdc> <callout> - <target>DIMM_IN_ERROR</target> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>DIMM_IN_ERROR</target> + <priority>LOW</priority> + </callout> <deconfigure> <target>DIMM_IN_ERROR</target> </deconfigure> - <gard> - <target>DIMM_IN_ERROR</target> - </gard> </hwpError> <hwpError> <rc>RC_MSS_BAD_MR_PARAMETER</rc> <description> - A bad parameter was passed to MR processing + A bad parameter was passed to MR processing + This is probably due to a bad value received from the SPD (e.g. unsupported cas latency) + Could be a code error </description> <ffdc>MR_NUMBER</ffdc> <ffdc>PARAMETER</ffdc> <ffdc>PARAMETER_VALUE</ffdc> <callout> - <target>DIMM_IN_ERROR</target> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>DIMM_IN_ERROR</target> + <priority>LOW</priority> + </callout> <deconfigure> <target>DIMM_IN_ERROR</target> </deconfigure> - <gard> - <target>DIMM_IN_ERROR</target> - </gard> </hwpError> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml index 3b7e47049..74743b025 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_general_errors.xml @@ -30,7 +30,7 @@ <!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> --> <!-- *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> --> <!-- *HWP Team: Memory --> -<!-- *HWP Level: 1 --> +<!-- *HWP Level: 3 --> <!-- *HWP Consumed by: HB:FSP --> <!-- --> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml index 359235310..1f46ce524 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml @@ -28,9 +28,9 @@ <!-- @brief Error xml for MSS library routines --> <!-- --> <!-- *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> --> -<!-- *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> --> +<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> <!-- *HWP Team: Memory --> -<!-- *HWP Level: 1 --> +<!-- *HWP Level: 3 --> <!-- *HWP Consumed by: HB:FSP --> <!-- --> @@ -167,7 +167,7 @@ <description> CCS reports a read miscompare. </description> - <ffdc>REG_CONTENTS</ffdc> + <ffdc>FAIL_TYPE</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>MCBIST_TARGET</target> @@ -191,7 +191,7 @@ CCS reports a UE or SUE in the CCS program array Chould be an indicator of corruption in the CCS program </description> - <ffdc>REG_CONTENTS</ffdc> + <ffdc>FAIL_TYPE</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>MCBIST_TARGET</target> @@ -214,7 +214,7 @@ <description> CCS reports never getting a response back from the PHY on a calibration command </description> - <ffdc>REG_CONTENTS</ffdc> + <ffdc>FAIL_TYPE</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_CCS_FAILURE</id> <target>MCBIST_TARGET</target> @@ -359,7 +359,7 @@ <description>PHY APB interface is reporting an invalid address was read or written</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -369,7 +369,7 @@ <description>PHY APB interface is reporting a read/write parity error</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -379,7 +379,7 @@ <description>Indicates a non-recoverable FSM state checker error in PHYTOP logic</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -389,7 +389,7 @@ <description>Indicates a non-recoverable parity error in PHYTOP logic</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -399,7 +399,7 @@ <description>Indicates a recoverable FSM state checker error in PHYTOP logic</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -409,7 +409,7 @@ <description>Indicates a recoverable register parity error in PHYTOP logic</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -419,7 +419,7 @@ <description>Indicates a non-recoverable register parity error in ADR52 master side logic</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -429,7 +429,7 @@ <description>Indicates a non-recoverable register parity error in ADR52 slave side logic</description> <ffdc>PORT_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -440,7 +440,7 @@ <ffdc>PORT_POSITION</ffdc> <ffdc>DP16_POSITION</ffdc> <callout> - <target>TARGET_IN_ERROR</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml deleted file mode 100644 index 27ed176b0..000000000 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml +++ /dev/null @@ -1,206 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> - -<!-- --> -<!-- @file memory_mss_termination_control.xml --> -<!-- @brief Error xml for termination control --> -<!-- --> -<!-- *HWP HWP Owner: Jacob L Harvey <jlharvey@us.ibm.com> --> -<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> -<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> --> -<!-- *HWP Team: Memory --> -<!-- *HWP Level: 1 --> -<!-- *HWP Consumed by: FSP:HB --> -<!-- --> - -<hwpErrors> - -<hwpError> - <rc>RC_CONFIG_DRV_IMP_INVALID_INPUT</rc> - <description> - The config_drv_imp utility function received a bad parameter - </description> - <ffdc>PORT_PARAM</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> - <rc>RC_CONFIG_RCV_IMP_INVALID_INPUT</rc> - <description> - The config_rcv_imp utility function received a bad parameter - </description> - <ffdc>PORT_PARAM</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> - <rc>RC_CONFIG_SLEW_RATE_INVALID_INPUT</rc> - <description> - The config_slew_rate utility function received a bad parameter - </description> - <ffdc>PORT_PARAM</ffdc> - <ffdc>SLEW_TYPE_PARAM</ffdc> - <ffdc>SLEW_IMP_PARAM</ffdc> - <ffdc>SLEW_RATE_PARAM</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> - <rc>RC_CONFIG_WR_DRAM_VREF_INVALID_INPUT</rc> - <description> - The config_wr_dram_vref utility function received a bad parameter - </description> - <ffdc>PORT_PARAM</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> - <rc>RC_CONFIG_RD_CEN_VREF_INVALID_INPUT</rc> - <description> - The config_rd_cen_vref utility function received a bad parameter - </description> - <ffdc>PORT_PARAM</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> - <rc>RC_MSS_SLEW_CAL_INVALID_DRAM_GEN</rc> - <description> - mss_slew_cal found an invalid DRAM type in ATTR_EFF_DRAM_GEN (not DDR3/4) - </description> - <ffdc>DRAM_GEN</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> - <rc>RC_MSS_SLEW_CAL_INVALID_FREQ</rc> - <description> - mss_slew_cal found a zero frequency in ATTR_MSS_FREQ - </description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<!-- Hm, fairly p9n specific ... BRS --> -<registerFfdc> - <id>REG_FFDC_MSS_SLEW_CAL_FAILURE</id> - <scomRegister>MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0</scomRegister> - <scomRegister>MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1</scomRegister> - <scomRegister>MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2</scomRegister> - <scomRegister>MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3</scomRegister> - - <scomRegister>MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3</scomRegister> -</registerFfdc> - -<!-- Should be good for MCA and MBA, not clear how to deal with the register ffdc, tho BRS --> -<hwpError> - <rc>RC_MSS_SLEW_CAL_TIMEOUT</rc> - <description> - mss_slew_cal found slew calibration timeout - </description> - <ffdc>PORT</ffdc> - <ffdc>DATA_ADR</ffdc> - <ffdc>IMP</ffdc> - <ffdc>SLEW</ffdc> - <ffdc>STAT_REG</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_MSS_SLEW_CAL_FAILURE</id> - <target>TARGET_IN_ERROR</target> - <targetType>TARGET_TYPE_MCA</targetType> - </collectRegisterFfdc> - <callout> - <target>TARGET_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET_IN_ERROR</target> - </deconfigure> - <gard> - <target>TARGET_IN_ERROR</target> - </gard> -</hwpError> - - -<hwpError> - <rc>RC_MSS_SLEW_CAL_ERROR</rc> - <description> - mss_slew_cal found slew calibration error - </description> - <ffdc>PORT</ffdc> - <ffdc>DATA_ADR</ffdc> - <ffdc>IMP</ffdc> - <ffdc>SLEW</ffdc> - <ffdc>STAT_REG</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_MSS_SLEW_CAL_FAILURE</id> - <target>TARGET_IN_ERROR</target> - <targetType>TARGET_TYPE_MCA</targetType> - </collectRegisterFfdc> - <callout> - <target>TARGET_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET_IN_ERROR</target> - </deconfigure> - <gard> - <target>TARGET_IN_ERROR</target> - </gard> -</hwpError> - -<hwpError> - <rc>RC_MSS_IMP_INPUT_ERROR</rc> - <!-- TODO Remove when all HWPs using it are using their own Error XML file --> - <description>Impedance is invalid for driver/receiver type.</description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -</hwpErrors> |
