L3 draminit and mss_lib

Change-Id: If5cae63291864da0b87d6a1e82407da9358d62d2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43121
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43278
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

1 files changed, 20 insertions, 20 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
index 23831968a..a4c5be8c6 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
@@ -27,10 +27,10 @@
 /// @file mrs05.C
 /// @brief Run and manage the DDR4 MRS05 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
-// *HWP Level: 1
+// *HWP Level: 3
 // *HWP Consumed by: FSP:HB
 
 #include <fapi2.H>
@@ -64,22 +64,22 @@ mrs05_data::mrs05_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     iv_write_dbi(fapi2::ENUM_ATTR_EFF_WRITE_DBI_DISABLE),
     iv_read_dbi(fapi2::ENUM_ATTR_EFF_READ_DBI_DISABLE)
 {
-    FAPI_TRY( mss::eff_ca_parity_latency(i_target, iv_ca_parity_latency) );
-    FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear) );
-    FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status) );
-    FAPI_TRY( mss::eff_odt_input_buff(i_target, iv_odt_input_buffer) );
-    FAPI_TRY( mss::eff_dram_rtt_park(i_target, &(iv_rtt_park[0])) );
-    FAPI_TRY( mss::eff_ca_parity(i_target, iv_ca_parity) );
-    FAPI_TRY( mss::eff_data_mask(i_target, iv_data_mask) );
-    FAPI_TRY( mss::eff_write_dbi(i_target, iv_write_dbi) );
-    FAPI_TRY( mss::eff_read_dbi(i_target, iv_read_dbi) );
+    FAPI_TRY( mss::eff_ca_parity_latency(i_target, iv_ca_parity_latency), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_odt_input_buff(i_target, iv_odt_input_buffer), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_dram_rtt_park(i_target, &(iv_rtt_park[0])), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_ca_parity(i_target, iv_ca_parity), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_data_mask(i_target, iv_data_mask), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_write_dbi(i_target, iv_write_dbi), "Error in mrs05_data()" );
+    FAPI_TRY( mss::eff_read_dbi(i_target, iv_read_dbi), "Error in mrs05_data()" );
 
     o_rc = fapi2::FAPI2_RC_SUCCESS;
     return;
 
 fapi_try_exit:
     o_rc = fapi2::current_err;
-    FAPI_ERR("unable to get attributes for mrs0");
+    FAPI_ERR("%s unable to get attributes for mrs05", mss::c_str(i_target));
     return;
 }
 
@@ -96,7 +96,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<TARGET_TYPE_DIMM>& i_target,
 {
     // Check to make sure our ctor worked ok
     mrs05_data l_data( i_target, fapi2::current_err );
-    FAPI_TRY( fapi2::current_err, "Unable to construct MRS05 data from attributes");
+    FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS05 data from attributes", mss::c_str(i_target) );
     FAPI_TRY( mrs05(i_target, l_data, io_inst, i_rank) );
 
 fapi_try_exit:
@@ -148,10 +148,10 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
 
     l_ca_parity_latency_buffer = ca_parity_latency_map[i_data.iv_ca_parity_latency];
 
-    FAPI_INF("MR5 rank %d attributes: CAPL: 0x%x(0x%x), CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x "
-             "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank,
-             i_data.iv_ca_parity_latency, uint8_t(l_ca_parity_latency_buffer), i_data.iv_crc_error_clear,
-             i_data.iv_ca_parity_error_status, i_data.iv_odt_input_buffer,
+    FAPI_INF("%s MR5 rank %d attributes: CAPL: 0x%x(0x%x), CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x "
+             "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x",
+             mss::c_str(i_target), i_rank, i_data.iv_ca_parity_latency, uint8_t(l_ca_parity_latency_buffer),
+             i_data.iv_crc_error_clear, i_data.iv_ca_parity_error_status, i_data.iv_odt_input_buffer,
              uint8_t(l_rtt_park_buffer), i_data.iv_ca_parity,
              i_data.iv_data_mask, i_data.iv_write_dbi, i_data.iv_read_dbi);
 
@@ -165,7 +165,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
     io_inst.arr0.writeBit<A11>(i_data.iv_write_dbi);
     io_inst.arr0.writeBit<A12>(i_data.iv_read_dbi);
 
-    FAPI_INF("MR5: 0x%016llx", uint64_t(io_inst.arr0));
+    FAPI_INF("%s MR5: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0));
 
     return fapi2::FAPI2_RC_SUCCESS;
 
@@ -216,8 +216,8 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS
     o_read_dbi = i_inst.arr0.getBit<A12>();
 
     FAPI_INF("MR5 rank %d decode: CAPL: 0x%x, CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x "
-             "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", i_rank,
-             uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status,
+             "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x",
+             i_rank, uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status,
              o_odt_input_buffer, uint8_t(o_rtt_park_buffer), o_ca_parity, o_data_mask,
              o_write_dbi, o_read_dbi);