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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-02-27 11:18:02 -0600 |
|---|---|---|
| committer | Dean Sanner <dsanner@us.ibm.com> | 2017-07-19 11:39:42 -0400 |
| commit | 543d555ed93fc95330ab9f1ef3a7f1a4e1a13f82 (patch) | |
| tree | b3fbf6b296681a99f459804c9c7fe63f18bee372 /src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C | |
| parent | b47fc4080e6f6b525fcd549811e5594a0b05230f (diff) | |
| download | talos-hostboot-543d555ed93fc95330ab9f1ef3a7f1a4e1a13f82.tar.gz talos-hostboot-543d555ed93fc95330ab9f1ef3a7f1a4e1a13f82.zip | |
L3 support for ddr_phy_reset, termination_control
Change-Id: I70ad1f23dabc4b9f169821b30a903a200f52fbc4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42437
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42452
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index 23831968a..9be19ebfd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -27,7 +27,7 @@ /// @file mrs05.C /// @brief Run and manage the DDR4 MRS05 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 |
