diff options
| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-02-27 11:18:02 -0600 |
|---|---|---|
| committer | Dean Sanner <dsanner@us.ibm.com> | 2017-07-19 11:39:42 -0400 |
| commit | 543d555ed93fc95330ab9f1ef3a7f1a4e1a13f82 (patch) | |
| tree | b3fbf6b296681a99f459804c9c7fe63f18bee372 /src | |
| parent | b47fc4080e6f6b525fcd549811e5594a0b05230f (diff) | |
| download | talos-hostboot-543d555ed93fc95330ab9f1ef3a7f1a4e1a13f82.tar.gz talos-hostboot-543d555ed93fc95330ab9f1ef3a7f1a4e1a13f82.zip | |
L3 support for ddr_phy_reset, termination_control
Change-Id: I70ad1f23dabc4b9f169821b30a903a200f52fbc4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42437
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42452
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Diffstat (limited to 'src')
39 files changed, 469 insertions, 402 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H index 963c06ced..60e39e58b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H @@ -28,7 +28,7 @@ /// @brief Run and manage the DDR4 control words for the RCD and data buffers /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H index c6dc9c2d2..694831f42 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H @@ -28,7 +28,7 @@ /// @brief Code to support data_buffer_ddr4 /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: HB:FSP diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C index d9e553cd5..cc96e9253 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C @@ -28,7 +28,7 @@ /// @brief Latches WR VREF according to JEDEC spec /// // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB Memory diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H index fffa45832..6c95f1280 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H @@ -28,7 +28,7 @@ /// @brief Latches WR VREF according to JEDEC spec /// // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB Memory diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index 1fcbe1b79..b1f181469 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file mrs00.C /// @brief Run and manage the DDR4 MRS00 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C index 19e4c71a1..b7cfcd4fb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C @@ -27,7 +27,7 @@ /// @file mrs01.C /// @brief Run and manage the DDR4 MRS01 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C index 1c86e63e5..7119c0240 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C @@ -27,7 +27,7 @@ /// @file mrs02.C /// @brief Run and manage the DDR4 MRS02 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C index a24421be3..922665c36 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C @@ -27,7 +27,7 @@ /// @file mrs03.C /// @brief Run and manage the DDR4 DDR4 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index 23831968a..9be19ebfd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -27,7 +27,7 @@ /// @file mrs05.C /// @brief Run and manage the DDR4 MRS05 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C index 3064909f3..104657819 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C @@ -27,7 +27,7 @@ /// @file mrs06.C /// @brief Run and manage the DDR4 MRS06 loading /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index 98ddc889c..92e576610 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -27,7 +27,7 @@ /// @file mrs_load_ddr4.H /// @brief Code to support mrs_load_ddr4 /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 1 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H index a3a18b01a..7cf49f8e2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H @@ -28,7 +28,7 @@ /// @brief state_machine delcaration /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: HB:FSP diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H index bdd0a7a3d..8c214acc1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H @@ -70,20 +70,6 @@ enum }; /// -/// @brief set of enums used for ffdc return codes -/// -enum rank_functions -{ - RANK_PAIR_TO_PHY = 0, - RANK_PAIR_FROM_PHY = 1, - SET_RANKS_IN_PAIR = 2, - GET_RANKS_IN_PAIR = 3, - GET_RANK_FIELD = 4, - GET_PAIR_VALID = 5, - SET_RANK_FIELD = 6, - RD_CTR_WORKAROUND_READ_DATA = 7, -}; -/// /// @class rankPairTraits /// @brief a collection of traits associated with rank pairs /// @tparam T fapi2::TargetType representing the PHY @@ -1193,6 +1179,8 @@ template< uint64_t RP, fapi2::TargetType T, typename TT = rankPairTraits<T, RP> fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target, std::vector<uint64_t>& o_ranks ) { + static_assert(RP < MAX_RANK_PER_DIMM, "Passed in Rank Pair is too high"); + o_ranks.clear(); // Read the rank pair register(s) @@ -1338,12 +1326,12 @@ inline fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK_PAIR() .set_RANK_PAIR(i_rp) - .set_MCA_TARGET(i_target) - .set_FUNCTION(GET_RANKS_IN_PAIR), - "%s Invalid rank pair (%d) in get_ranks_in_pair", + .set_FUNCTION(GET_RANKS_IN_PAIR) + .set_MCA_TARGET(i_target), + "%s Invalid number of rankpairs entered. num: %lu max: %lu", mss::c_str(i_target), - i_rp); - + i_rp, + MAX_PRIMARY_RANKS_PER_PORT); break; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C index ce0497058..ed1cbb30b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C @@ -27,10 +27,10 @@ /// @file check.C /// @brief Subroutines for checking MSS FIR /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C index b174e5ff6..4f3ecc441 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.C @@ -27,10 +27,10 @@ /// @file adr.C /// @brief Subroutines for the PHY ADR registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -168,17 +168,14 @@ fapi2::ReturnCode reset_imp_clk( const fapi2::Target<TARGET_TYPE_MCA>& i_target FAPI_TRY(mss::vpd_mt_mc_drv_imp_clk(i_target, l_attr_value)); //checks the attr value - if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM30 && - l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM40 ) - { - FAPI_ASSERT(false, - fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CLK() - .set_VALUE(l_attr_value) - .set_MCA_TARGET(i_target), - "%s value is not valid: %u", - c_str(i_target), - l_attr_value); - } + FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM30 || + l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK_OHM40, + fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CLK() + .set_VALUE(l_attr_value) + .set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ), + "%s value is not valid: %u", + c_str(i_target), + l_attr_value); //loops and sets the value in each register //Note: does RMW as other functions set the other lanes @@ -228,17 +225,14 @@ fapi2::ReturnCode reset_imp_cmd_addr( const fapi2::Target<TARGET_TYPE_MCA>& i_ta FAPI_TRY(mss::vpd_mt_mc_drv_imp_cmd_addr(i_target, l_attr_value)); //checks the attr value - if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM30 && - l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM40 ) - { - FAPI_ASSERT(false, - fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CMD_ADDR() - .set_VALUE(l_attr_value) - .set_MCA_TARGET(i_target), - "%s value is not valid: %u", - c_str(i_target), - l_attr_value); - } + FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM30 || + l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR_OHM40, + fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CMD_ADDR() + .set_VALUE(l_attr_value) + .set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ), + "%s value is not valid: %u", + c_str(i_target), + l_attr_value); //loops and sets the value in each register //Note: does RMW as other functions set the other lanes @@ -288,17 +282,14 @@ fapi2::ReturnCode reset_imp_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_target FAPI_TRY(mss::vpd_mt_mc_drv_imp_cntl(i_target, l_attr_value)); //checks the attr value - if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM30 && - l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM40 ) - { - FAPI_ASSERT(false, - fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CNTL() - .set_VALUE(l_attr_value) - .set_MCA_TARGET(i_target), - "%s value is not valid: %u", - c_str(i_target), - l_attr_value); - } + FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM30 || + l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL_OHM40, + fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CNTL() + .set_VALUE(l_attr_value) + .set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ), + "%s value is not valid: %u", + c_str(i_target), + l_attr_value); //loops and sets the value in each register //Note: does RMW as other functions set the other lanes @@ -325,7 +316,6 @@ fapi2::ReturnCode reset_imp_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_target FAPI_TRY(mss::putScom(i_target, l_reg_info.first, l_value)); - } fapi_try_exit: @@ -348,17 +338,14 @@ fapi2::ReturnCode reset_imp_cscid( const fapi2::Target<TARGET_TYPE_MCA>& i_targe FAPI_TRY(mss::vpd_mt_mc_drv_imp_cscid(i_target, l_attr_value)); //checks the attr value - if(l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM30 && - l_attr_value != fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM40 ) - { - FAPI_ASSERT(false, - fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CSCID() - .set_VALUE(l_attr_value) - .set_MCA_TARGET(i_target), - "%s value is not valid: %u", - c_str(i_target), - l_attr_value); - } + FAPI_ASSERT( l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM30 || + l_attr_value == fapi2::ENUM_ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID_OHM40, + fapi2::MSS_INVALID_VPD_MT_MC_DRV_IMP_CSCID() + .set_VALUE(l_attr_value) + .set_MCS_TARGET( mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target) ), + "%s value is not valid: %u", + c_str(i_target), + l_attr_value); //loops and sets the value in each register //Note: does RMW as other functions set the other lanes diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H index 199b3f9de..62884f8bd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr.H @@ -27,10 +27,10 @@ /// @file adr.H /// @brief Subroutines for the PHY ADR registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_ADR_H_ @@ -223,7 +223,7 @@ inline fapi2::ReturnCode read_imp_clk( const fapi2::Target<T>& i_target, //one register per CLK FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CLK_REG[I].first, o_data) ); - FAPI_INF("imp_clk lane<%d>: 0x%016lx", I, o_data); + FAPI_INF("%s imp_clk lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; @@ -245,7 +245,7 @@ inline fapi2::ReturnCode write_imp_clk( const fapi2::Target<T>& i_target, static_assert( I < TT::NUM_CLK_LANES, "lane instance out of range"); //one register per CLK - FAPI_INF("imp_clk lane<%d>: 0x%016lx", I, i_data); + FAPI_INF("%s imp_clk lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CLK_REG[I].first, i_data) ); fapi_try_exit: @@ -278,7 +278,7 @@ inline fapi2::ReturnCode read_imp_cmd_addr( const fapi2::Target<T>& i_target, //one register per CMD/ADDR lane FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CMD_ADDR_REG[I].first, o_data) ); - FAPI_INF("imp_cmd_addr lane<%d>: 0x%016lx", I, o_data); + FAPI_INF("%s imp_cmd_addr lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; @@ -300,7 +300,7 @@ inline fapi2::ReturnCode write_imp_cmd_addr( const fapi2::Target<T>& i_target, static_assert( I < TT::NUM_CMD_ADDR_LANES, "lane instance out of range"); //one register per CMD/ADDR lane - FAPI_INF("imp_cmd_addr lane<%d>: 0x%016lx", I, i_data); + FAPI_INF("%s imp_cmd_addr lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CMD_ADDR_REG[I].first, i_data) ); fapi_try_exit: @@ -333,7 +333,7 @@ inline fapi2::ReturnCode read_imp_cntl( const fapi2::Target<T>& i_target, //one register per CNTL FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CNTL_REG[I].first, o_data) ); - FAPI_INF("imp_cntl lane<%d>: 0x%016lx", I, o_data); + FAPI_INF("%s imp_cntl lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; @@ -355,7 +355,7 @@ inline fapi2::ReturnCode write_imp_cntl( const fapi2::Target<T>& i_target, static_assert( I < TT::NUM_CNTL_LANES, "lane instance out of range"); //one register per CNTL - FAPI_INF("imp_cntl lane<%d>: 0x%016lx", I, i_data); + FAPI_INF("%s imp_cntl lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CNTL_REG[I].first, i_data) ); fapi_try_exit: @@ -388,7 +388,7 @@ inline fapi2::ReturnCode read_imp_cscid( const fapi2::Target<T>& i_target, //one register per CS/CID FAPI_TRY( mss::getScom(i_target, TT::IO_TX_FET_SLICE_CSCID_REG[I].first, o_data) ); - FAPI_INF("imp_cscid lane<%d>: 0x%016lx", I, o_data); + FAPI_INF("%s imp_cscid lane<%d>: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; @@ -410,7 +410,7 @@ inline fapi2::ReturnCode write_imp_cscid( const fapi2::Target<T>& i_target, static_assert( I < TT::NUM_CSCID_LANES, "lane instance out of range"); //one register per CS/CID - FAPI_INF("imp_cscid lane<%d>: 0x%016lx", I, i_data); + FAPI_INF("%s imp_cscid lane<%d>: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::IO_TX_FET_SLICE_CSCID_REG[I].first, i_data) ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C index a3012202c..f68b7dab9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -98,7 +98,7 @@ fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2:: if (l_mca.size() == 0) { - FAPI_INF("No MCA, skipping duty cycle distortion calibration"); + FAPI_INF("%s No MCA, skipping duty cycle distortion calibration", mss::c_str(i_target) ); return FAPI2_RC_SUCCESS; } @@ -113,13 +113,14 @@ fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2:: if(mss::chip_ec_nimbus_lt_2_0(i_target)) { // Runs the DD1 calibration - FAPI_TRY(mss::workarounds::adr32s::duty_cycle_distortion_calibration(i_target)); + FAPI_TRY(mss::workarounds::adr32s::duty_cycle_distortion_calibration(i_target), "%s Failed dcd calibration", + mss::c_str(i_target) ); } else { // Runs the DD2 calibration algorithm - FAPI_TRY(mss::dcd::execute_hw_calibration(i_target)); + FAPI_TRY(mss::dcd::execute_hw_calibration(i_target), "%s Failed dcd execute hw calibration", mss::c_str(i_target) ); } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H index d5246bafd..ac45811f6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H @@ -27,7 +27,7 @@ /// @file adr32s.H /// @brief Subroutines for the PHY ADR32S registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 @@ -180,7 +180,7 @@ inline fapi2::ReturnCode read_dcd_cntl( const fapi2::Target<T>& i_target, fapi2: { static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range"); FAPI_TRY( mss::getScom(i_target, TT::DUTY_CYCLE_DISTORTION_REG[I], o_data) ); - FAPI_INF("dcd_cntl adrs32%d: 0x%016lx", I, o_data); + FAPI_INF("%s dcd_cntl adrs32%d: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; } @@ -207,7 +207,7 @@ inline fapi2::ReturnCode write_dcd_cntl( const fapi2::Target<T>& i_target, const fapi2::Assert(false); } - FAPI_INF("dcd_cntl adr32s%d: 0x%016lx", I, i_data); + FAPI_INF("%s dcd_cntl adr32s%d: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::DUTY_CYCLE_DISTORTION_REG[I], i_data) ); fapi_try_exit: return fapi2::current_err; @@ -231,7 +231,7 @@ inline fapi2::ReturnCode reset_dcd_cntl( const fapi2::Target<T>& i_target ) for (const auto r : TT::DUTY_CYCLE_DISTORTION_REG) { - FAPI_INF("reset dcd_cntl 0x%016lx: 0x%016lx", r, l_data); + FAPI_INF("%s reset dcd_cntl 0x%016lx: 0x%016lx", mss::c_str(i_target), r, l_data); FAPI_TRY( mss::putScom(i_target, r, l_data) ); } @@ -269,7 +269,7 @@ inline fapi2::ReturnCode read_output_driver( const fapi2::Target<T>& i_target, f { static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range"); FAPI_TRY( mss::getScom(i_target, TT::OUTPUT_DRIVER_REG[I], o_data) ); - FAPI_INF("output_driver adrs32%d: 0x%016lx", I, o_data); + FAPI_INF("%s output_driver adrs32%d: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; } @@ -287,7 +287,7 @@ template< uint64_t I, fapi2::TargetType T, typename TT = adr32sTraits<T> > inline fapi2::ReturnCode write_output_driver( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range"); - FAPI_INF("output_driver adr32s%d: 0x%016lx", I, i_data); + FAPI_INF("%s output_driver adr32s%d: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::OUTPUT_DRIVER_REG[I], i_data) ); fapi_try_exit: return fapi2::current_err; @@ -344,7 +344,7 @@ inline fapi2::ReturnCode read_tsys_adr( const fapi2::Target<T>& i_target, fapi2: { static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range"); FAPI_TRY( mss::getScom(i_target, TT::PR_STATIC_OFFSET_REG[I], o_data) ); - FAPI_INF("tsys_adr adrs32%d: 0x%016lx", I, o_data); + FAPI_INF("%s tsys_adr adrs32%d: 0x%016lx", mss::c_str(i_target), I, o_data); fapi_try_exit: return fapi2::current_err; } @@ -362,7 +362,7 @@ template< uint64_t I, fapi2::TargetType T, typename TT = adr32sTraits<T> > inline fapi2::ReturnCode write_tsys_adr( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range"); - FAPI_INF("tsys_adr adr32s%d: 0x%016lx", I, i_data); + FAPI_INF("%s tsys_adr adr32s%d: 0x%016lx", mss::c_str(i_target), I, i_data); FAPI_TRY( mss::putScom(i_target, TT::PR_STATIC_OFFSET_REG[I], i_data) ); fapi_try_exit: return fapi2::current_err; @@ -387,7 +387,7 @@ inline fapi2::ReturnCode reset_tsys_adr( const fapi2::Target<T>& i_target ) for (const auto r : TT::PR_STATIC_OFFSET_REG) { // TODO RTC:160358 Suspect duplicated scoms in ddr initfile - FAPI_INF("reset tsys_adr 0x%016lx: 0x%016lx", r, l_data); + FAPI_INF("%s reset tsys_adr 0x%016lx: 0x%016lx", mss::c_str(i_target), r, l_data); FAPI_TRY( mss::putScom(i_target, r, l_data) ); } @@ -395,7 +395,6 @@ fapi_try_exit: return fapi2::current_err; } - } // close namespace adr32s } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C index 70cd20c78..4fc25aa76 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C @@ -27,10 +27,10 @@ /// @file apb.C /// @brief Subroutines for the PHY APB registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H index 2e03d9924..96c41eb14 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H @@ -27,10 +27,10 @@ /// @file apb.H /// @brief Subroutines for the PHY APB registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_APB_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H index 665aef3ba..16f87310f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H @@ -27,10 +27,10 @@ /// @file cal_timers.H /// @brief Subroutines to calculate the duration of training operations /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_CAL_TIMERS_H_ @@ -61,8 +61,11 @@ uint64_t wr_lvl_cycles(const fapi2::Target<T>& i_target ) const uint64_t l_wr_lvl_cycles = (80 + TWLO_TWLOE) * WR_LVL_NUM_VALID_SAMPLES * (384 / (WR_LVL_BIG_STEP + 1) + (2 * (WR_LVL_BIG_STEP + 1)) / (WR_LVL_SMALL_STEP + 1)) + 20; - FAPI_DBG("wr_lvl_cycles: %llu(%lluns) (%llu, %llu, %llu, %llu)", l_wr_lvl_cycles, mss::cycles_to_ns(i_target, - l_wr_lvl_cycles), + FAPI_DBG("%s wr_lvl_cycles: %llu(%lluns) (%llu, %llu, %llu, %llu)", + mss::c_str(i_target), + l_wr_lvl_cycles, + mss::cycles_to_ns(i_target, + l_wr_lvl_cycles), TWLO_TWLOE, WR_LVL_NUM_VALID_SAMPLES, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP); return l_wr_lvl_cycles; @@ -80,7 +83,8 @@ uint64_t dqs_align_cycles(const fapi2::Target<T>& i_target ) // This step runs for approximately 6 x 600 x 4 DRAM clocks per rank pair. const uint64_t l_dqs_align_cycles = 6 * 600 * 4; - FAPI_DBG("dqs_align_cycles: %llu(%lluns)", l_dqs_align_cycles, mss::cycles_to_ns(i_target, l_dqs_align_cycles)); + FAPI_DBG("%s dqs_align_cycles: %llu(%lluns)", mss::c_str(i_target), l_dqs_align_cycles, mss::cycles_to_ns(i_target, + l_dqs_align_cycles)); return l_dqs_align_cycles; } @@ -96,7 +100,7 @@ uint64_t rdclk_align_cycles(const fapi2::Target<T>& i_target ) // This step runs for approximately 24 x ((1024/COARSE_CAL_STEP_SIZE + 4 x COARSE_CAL_STEP_SIZE) x 4 + 32) DRAM // clocks per rank pair const uint64_t l_rdclk_align_cycles = 24 * ((1024 / COARSE_CAL_STEP_SIZE + 4 * COARSE_CAL_STEP_SIZE) * 4 + 32); - FAPI_DBG("rdclk_align_cycles: %llu(%lluns) (%llu)", l_rdclk_align_cycles, + FAPI_DBG("%s rdclk_align_cycles: %llu(%lluns) (%llu)", mss::c_str(i_target), l_rdclk_align_cycles, mss::cycles_to_ns(i_target, l_rdclk_align_cycles), COARSE_CAL_STEP_SIZE); return l_rdclk_align_cycles; } @@ -114,8 +118,12 @@ uint64_t read_ctr_cycles(const fapi2::Target<T>& i_target ) // 4 x CONSEQ_PASS)) x 24 DRAM clocks per rank pair. const uint64_t l_read_ctr_cycles = 6 * (512 / COARSE_CAL_STEP_SIZE + 4 * (COARSE_CAL_STEP_SIZE + 4 * CONSEQ_PASS)) * 24; - FAPI_DBG("read_ctr_cycles %llu(%lluns) (%llu, %llu)", l_read_ctr_cycles, mss::cycles_to_ns(i_target, l_read_ctr_cycles), - COARSE_CAL_STEP_SIZE, CONSEQ_PASS); + FAPI_DBG("%s read_ctr_cycles %llu(%lluns) (%llu, %llu)", + mss::c_str(i_target), + l_read_ctr_cycles, + mss::cycles_to_ns(i_target, l_read_ctr_cycles), + COARSE_CAL_STEP_SIZE, + CONSEQ_PASS); return l_read_ctr_cycles; } @@ -141,9 +149,15 @@ fapi2::ReturnCode write_ctr_cycles(const fapi2::Target<T>& i_target, uint64_t& o (1024 / (WR_LVL_SMALL_STEP + 1) + 128 / (WR_LVL_BIG_STEP + 1)) + 2 * (WR_LVL_BIG_STEP + 1) / (WR_LVL_SMALL_STEP + 1)) * 24; - FAPI_DBG("write_ctr_cycles: %lu(%luns) (%u, %u, %u, %u, %u)", - o_cycles, mss::cycles_to_ns(i_target, o_cycles), - WR_LVL_NUM_VALID_SAMPLES, WR_CNTR_FW_WR_RD, l_fw_rd_wr, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP); + FAPI_DBG("%s write_ctr_cycles: %lu(%luns) (%u, %u, %u, %u, %u)", + mss::c_str(i_target), + o_cycles, + mss::cycles_to_ns(i_target, o_cycles), + WR_LVL_NUM_VALID_SAMPLES, + WR_CNTR_FW_WR_RD, + l_fw_rd_wr, + WR_LVL_BIG_STEP, + WR_LVL_SMALL_STEP); return fapi2::FAPI2_RC_SUCCESS; @@ -163,7 +177,10 @@ uint64_t coarse_wr_cycles(const fapi2::Target<T>& i_target ) // The run length given here is the maximum run length for this calibration algorithm. // This step runs for approximately 40 DRAM clocks per rank pair. static const uint64_t l_coarse_wr_cycles = 40; - FAPI_DBG("coarse_wr_cycles: %llu(%lluns)", l_coarse_wr_cycles, mss::cycles_to_ns(i_target, l_coarse_wr_cycles)); + FAPI_DBG("%s coarse_wr_cycles: %llu(%lluns)", + mss::c_str(i_target), + l_coarse_wr_cycles, + mss::cycles_to_ns(i_target, l_coarse_wr_cycles)); return l_coarse_wr_cycles; } @@ -179,7 +196,10 @@ uint64_t coarse_rd_cycles(const fapi2::Target<T>& i_target ) // The run length given here is the maximum run length for this calibration algorithm. // This step runs for approximately 32 DRAM clocks per rank pair. static const uint64_t l_coarse_rd_cycles = 32; - FAPI_DBG("coarse_rd_cycles: %llu(%lluns)", l_coarse_rd_cycles, mss::cycles_to_ns(i_target, l_coarse_rd_cycles)); + FAPI_DBG("%s coarse_rd_cycles: %llu(%lluns)", + mss::c_str(i_target), + l_coarse_rd_cycles, + mss::cycles_to_ns(i_target, l_coarse_rd_cycles)); return l_coarse_rd_cycles; } @@ -187,13 +207,13 @@ uint64_t coarse_rd_cycles(const fapi2::Target<T>& i_target ) /// @brief Configure the polling intervals with the proper timeings based on the cal steps enabled /// @tparam T the fapi2::TargetType of the port /// @param[in] i_target the port target -/// @param[in] i_poll the poll_parameters to update +/// @param[in,out] io_poll the poll_parameters to update /// @param[in] i_cal_steps_enabled a fapi2::buffer<uint8_t> representing the cal steps enabled /// @return FAPI2_RC_SUCCESS iff everything is OK /// template<fapi2::TargetType T> inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target, - poll_parameters& i_poll, + poll_parameters& io_poll, const fapi2::buffer<uint32_t>& i_cal_steps_enabled) { // This should equal half of the minimum poll count of the quickest cal segment when in sim @@ -206,9 +226,11 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target, uint8_t cal_abort_on_error = 0; uint16_t l_vref_cal_enable = 0; - FAPI_TRY( mss::write_ctr_cycles(i_target, l_write_cntr_cycles) ); - FAPI_TRY( mss::cal_abort_on_error(cal_abort_on_error) ); - FAPI_TRY( mss::rdvref_cal_enable(i_target, l_vref_cal_enable) ); + FAPI_TRY( mss::write_ctr_cycles(i_target, l_write_cntr_cycles), "%s Failed calling write_ctr_cycles", + mss::c_str(i_target) ); + FAPI_TRY( mss::cal_abort_on_error(cal_abort_on_error), "%s Failed calling cal_abort_on_errorp", mss::c_str(i_target) ); + FAPI_TRY( mss::rdvref_cal_enable(i_target, l_vref_cal_enable), "%s Failed calling rdvref_cal_enable", + mss::c_str(i_target) ); // First, calculate the total number of cycles this cal should take if everything // runs to completion @@ -231,37 +253,43 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target, // when training starts - makes it simpler to get an AET for, say, write leveling. So // this is here to allow the simple removal of the initial delay for those situations. #ifdef THRASH_CCS_IP_IN_SIM - i_poll.iv_initial_delay = mss::cycles_to_ns(i_target, 1); - i_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(1); + io_poll.iv_initial_delay = mss::cycles_to_ns(i_target, 1); + io_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(1); #else // We don't want to wait too long for the initial check, just some hueristics here - i_poll.iv_initial_delay = mss::cycles_to_ns(i_target, l_total_cycles / 8); - i_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(l_total_cycles / 8); + io_poll.iv_initial_delay = mss::cycles_to_ns(i_target, l_total_cycles / 8); + io_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(l_total_cycles / 8); #endif // Delay 10us between polls, and setup the poll count so // iv_initial_delay + (iv_delay * iv_poll_count) == l_total_cycles + some fudge; - i_poll.iv_delay = 10 * DELAY_1US; - i_poll.iv_sim_delay = mss::cycles_to_simcycles(mss::ns_to_cycles(i_target, i_poll.iv_delay)); + io_poll.iv_delay = DELAY_10US; + io_poll.iv_sim_delay = mss::cycles_to_simcycles(mss::ns_to_cycles(i_target, io_poll.iv_delay)); // Round up to the cycles left after the initial delay l_ns_left = std::max(int64_t(0), (int64_t(mss::cycles_to_ns(i_target, - l_total_cycles)) - int64_t(i_poll.iv_initial_delay))); - i_poll.iv_poll_count = l_ns_left / i_poll.iv_delay; - i_poll.iv_poll_count += l_ns_left % i_poll.iv_delay ? 0 : 1; + l_total_cycles)) - int64_t(io_poll.iv_initial_delay))); + io_poll.iv_poll_count = l_ns_left / io_poll.iv_delay; + io_poll.iv_poll_count += l_ns_left % io_poll.iv_delay ? 0 : 1; // Make the minimum poll count 2, as that's the value of the quickest cal step in sim - i_poll.iv_poll_count = (i_poll.iv_poll_count < MINIMUM_POLL_COUNT) ? MINIMUM_POLL_COUNT : i_poll.iv_poll_count; + io_poll.iv_poll_count = (io_poll.iv_poll_count < MINIMUM_POLL_COUNT) ? MINIMUM_POLL_COUNT : io_poll.iv_poll_count; // Fudge some for sim irregularities. This will increase time to a complete timeout but won't // really effect valid training unless these cycles are needed. So this isn't a bad thing ... // AKA watchdog timer // HB is failing, bump it out 4x for the polling - i_poll.iv_poll_count *= 4; - - FAPI_INF("cal abort on error? %s. tc: %luc, id: %luns(%lusc), d: %lu(%lusc), pc: %lu", - (cal_abort_on_error ? "yup" : "nope"), l_total_cycles, i_poll.iv_initial_delay, - i_poll.iv_initial_sim_delay, i_poll.iv_delay, i_poll.iv_sim_delay, i_poll.iv_poll_count); + io_poll.iv_poll_count *= 4; + + FAPI_INF("%s cal abort on error? %s. tc: %luc, id: %luns(%lusc), d: %lu(%lusc), pc: %lu", + mss::c_str(i_target), + (cal_abort_on_error ? "yup" : "nope"), + l_total_cycles, + io_poll.iv_initial_delay, + io_poll.iv_initial_sim_delay, + io_poll.iv_delay, + io_poll.iv_sim_delay, + io_poll.iv_poll_count); return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.C index 420dee664..d8bee45ba 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -264,17 +264,17 @@ fapi2::ReturnCode sw_cal_side_helper( const fapi2::Target<TARGET_TYPE_MCA>& i_ta FAPI_ASSERT( l_current_adjust != l_overrun, fapi2::MSS_DUTY_CLOCK_DISTORTION_CAL_FAILED() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_CURRENT_ADJUST(l_current_adjust) .set_SIDE(i_side) .set_REGISTER(i_reg) .set_REGISTER_VALUE(l_read), - "Failed DCD for %s 0x%016lx", mss::c_str(i_target), i_reg ); + "%s Failed DCD for %s 0x%016lx", mss::c_str(i_target), mss::c_str(i_target), i_reg ); // If we're here, we were done and there were no errors. So we can return back the current adjust value // as the output/result of our operation o_value = l_current_adjust; - FAPI_INF("side: %d final adjust value: 0x%x (0x%x)", i_side, o_value, l_current_adjust); + FAPI_INF("%s side: %d final adjust value: 0x%x (0x%x)", mss::c_str(i_target), i_side, o_value, l_current_adjust); return FAPI2_RC_SUCCESS; @@ -325,8 +325,11 @@ fapi2::ReturnCode sw_cal_per_register( const fapi2::Target<TARGET_TYPE_MCA>& i_t FAPI_TRY(compute_dcd_value(l_a_rc, l_a_side_value, l_b_rc, l_b_side_value, io_seed)); FAPI_INF("%s calibrated value for both sides for reg 0x%016lx cal value: 0x%02x, a_side 0x%02x b_side: 0x%02x", - mss::c_str(i_target), i_reg, io_seed, - l_a_side_value, l_b_side_value); + mss::c_str(i_target), + i_reg, + io_seed, + l_a_side_value, + l_b_side_value); // Stores the final calibrated values in the register with a RMW FAPI_TRY( mss::getScom(i_target, i_reg, l_buff) ); @@ -367,9 +370,13 @@ fapi2::ReturnCode compute_dcd_value(fapi2::ReturnCode& io_a_side_rc, (io_b_side_rc != FAPI2_RC_SUCCESS)) { // Log a-side and b-side RC's leave the seed as it is + // Currently not logging a-side b-side issue due to bad hardware? + // We can still run even if we fail DCD cal fail + // Recovered flag will make it informational. Deconfigs won't happen and the customer won't see + // But we will ;) FAPI_ERR("Recovered from DCD calibration fail - both side A and side B failed, using prior calibrated value"); - fapi2::logError(io_a_side_rc); - fapi2::logError(io_b_side_rc); + fapi2::logError(io_a_side_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); + fapi2::logError(io_b_side_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); return FAPI2_RC_SUCCESS; } @@ -377,7 +384,7 @@ fapi2::ReturnCode compute_dcd_value(fapi2::ReturnCode& io_a_side_rc, if(io_b_side_rc != FAPI2_RC_SUCCESS) { FAPI_ERR("Recovered from DCD calibration fail - side B failed, using side-A's value"); - fapi2::logError(io_b_side_rc); + fapi2::logError(io_b_side_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); o_value = i_a_side_val; return FAPI2_RC_SUCCESS; } @@ -386,7 +393,7 @@ fapi2::ReturnCode compute_dcd_value(fapi2::ReturnCode& io_a_side_rc, if(io_a_side_rc != FAPI2_RC_SUCCESS) { FAPI_ERR("Recovered from DCD calibration fail - side A failed, using side-B's value"); - fapi2::logError(io_a_side_rc); + fapi2::logError(io_a_side_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); o_value = i_b_side_val; return FAPI2_RC_SUCCESS; } @@ -427,7 +434,7 @@ void log_reg_results( const fapi2::Target<TARGET_TYPE_MCA>& i_target, // Set current error, and log it FAPI_ASSERT(false, fapi2::MSS_HARDWARE_DUTY_CLOCK_DISTORTION_CAL_FAILED() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(i_reg), "DCD hardware calibration failed on %s. register 0x%016lx. Attempting software recovery", mss::c_str(i_target), i_reg); @@ -499,7 +506,7 @@ fapi2::ReturnCode poll_for_done_and_log_reg( const fapi2::Target<TARGET_TYPE_MCA // If the polling didn't finish, exit out with an error FAPI_ASSERT( l_poll_finished, fapi2::MSS_HARDWARE_DUTY_CLOCK_DISTORTION_CAL_TIMEOUT() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(i_reg), "Timed out in hardware DCD for %s 0x%016lx", mss::c_str(i_target), i_reg ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.H index 5a5b75a8b..424c38b99 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dcd.H @@ -30,7 +30,7 @@ // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef MSS_DCD_H diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 919869a88..a0a8a8d8e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -27,8 +27,8 @@ /// @file ddr_phy.C /// @brief Subroutines to manipulate the phy, or used during phy procedures /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB @@ -58,6 +58,7 @@ #include <generic/memory/lib/utils/scom.H> #include <lib/utils/count_dimm.H> #include <lib/dimm/rank.H> +#include <lib/shared/mss_const.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_PROC_CHIP; @@ -73,7 +74,7 @@ namespace mss /// /// @brief Clears all training related errors - specialization for MCA /// @param[in] i_target the port in question -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error /// template< > fapi2::ReturnCode clear_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MCA>& i_target ) @@ -104,8 +105,8 @@ fapi_try_exit: /// /// @brief Clears all training related errors - specialization for MCBIST -/// @param[in] i_target the port in question -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error +/// @param[in] i_target MCBIST target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error /// template< > fapi2::ReturnCode clear_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) @@ -487,9 +488,9 @@ fapi2::ReturnCode rank_pair_primary_to_dimm( const fapi2::Target<TARGET_TYPE_MCA FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks_in_rp) ); // Make sure we have a valid rank - FAPI_ASSERT( l_ranks_in_rp[0] != NO_RANK, - fapi2::MSS_NO_PRIMARY_RANK_FOUND_RP() - .set_RANK_PAIR(i_rp) + FAPI_ASSERT( (l_ranks_in_rp.size() != 0) && (l_ranks_in_rp[0] != NO_RANK), + fapi2::MSS_NO_PRIMARY_RANK_IN_RANK_PAIR() + .set_RP(i_rp) .set_MCA_TARGET(i_target), "%s No primary rank in rank pair %d", mss::c_str(i_target), @@ -870,6 +871,7 @@ fapi2::ReturnCode setup_read_vref_config1( const fapi2::Target<fapi2::TARGET_TYP fapi_try_exit: return fapi2::current_err; } + /// /// @brief Setup all the cal config register /// @param[in] i_target the MCA target associated with this cal setup @@ -1437,6 +1439,15 @@ fapi2::ReturnCode override_odt_wr_config( const fapi2::Target<fapi2::TARGET_TYPE const uint64_t l_dimm_count = count_dimm(i_target); + FAPI_ASSERT( i_rank < MAX_MRANK_PER_PORT, + fapi2::MSS_INVALID_RANK() + .set_RANK(i_rank) + .set_MCA_TARGET(i_target) + .set_FUNCTION(OVERRIDE_ODT_WR_CONFIG), + "%s had invalid rank (0x%016lx) passed into override_odt_wr_config", + mss::c_str(i_target), + i_rank ); + // read the attributes FAPI_TRY( mss::vpd_mt_odt_wr(i_target, &(l_odt_wr[0][0])) ); @@ -1479,9 +1490,13 @@ fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET fapi2::MSS_NO_RANKS_IN_RANK_PAIR() .set_TARGET(i_target) .set_RANK_PAIR(i_rp), - "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), i_rp ); + "No ranks configured in MCA %s, rank pair %d", + mss::c_str(i_target), + i_rp ); - FAPI_INF("%s Setting up terminations for WR_LEVEL, MRANK %d", mss::c_str(i_target), l_ranks[0]); + FAPI_INF("%s Setting up terminations for WR_LEVEL, MRANK %d", + mss::c_str(i_target), + l_ranks[0]); // Get DIMM target FAPI_TRY( mss::rank::get_dimm_target_from_rank(i_target, l_ranks[0], l_dimm) ); @@ -1568,11 +1583,14 @@ fapi_try_exit: /// /// @brief Start the DLL calibration, monitor for fails. /// @param[in] i_target the target associated with this DLL cal +/// @param[out] o_run_workaround boolean whether we need to run workarounds /// @return FAPI2_RC_SUCCESS iff setup was successful /// template<> -fapi2::ReturnCode dll_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) +fapi2::ReturnCode dll_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + bool& o_run_workaround ) { + o_run_workaround = false; uint8_t l_sim = 0; fapi2::buffer<uint64_t> l_status; constexpr uint64_t l_dll_status_reg = pcTraits<TARGET_TYPE_MCA>::PC_DLL_ZCAL_CAL_STATUS_REG; @@ -1659,16 +1677,10 @@ fapi2::ReturnCode dll_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST fapi2::buffer<uint64_t> l_read; FAPI_TRY( mss::getScom(p, l_dll_status_reg, l_read) ); - if( mss::pc::get_dll_cal_status(l_read) != mss::YES ) - { - // For all Nimbus parts parts we want to run DLL workaround so - // Instead of using FAPI_ASSERT and logging FFDC we will - // return a "bad" ReturnCode to trigger a workaround that - // will be run after DLL Calibration for all failing DLLs. - // FFDC will be collected there if it doesn't pass. - return fapi2::FAPI2_RC_FALSE; - - }// endif + // For all Nimbus parts we want to run DLL workaround so + // Instead of using FAPI_ASSERT or returning an error + // We'll use a bool to tell if we need to run the workaround + o_run_workaround = (mss::pc::get_dll_cal_status(l_read) != mss::YES); }// mca diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H index bb0a3a847..1c27efccc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H @@ -27,10 +27,10 @@ /// @file ddr_phy.H /// @brief Subroutines to manipulate the phy, or used during phy procedures /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_DDR_PHY_H_ @@ -72,12 +72,6 @@ fapi2::ReturnCode enable_zctl( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i /// fapi2::ReturnCode change_force_mclk_low (const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, const mss::states i_state); -/// -/// @brief Unset the PLL and check to see that the PLL's have started -/// @param[in] i_target the mcbist target -/// @return FAPI2_RC_SUCCES iff ok -/// -fapi2::ReturnCode deassert_pll_reset( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); /// /// @brief Change the continuous update mode of the PR CNTL registers @@ -370,18 +364,20 @@ fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARG /// @brief Perform the DLL calibration /// @tparam T the target type of the MCBIST /// @param[in] i_target the target associated with this DLL cal +/// @param[out] o_run_workaround whether we need to run workarounds /// @return FAPI2_RC_SUCCESS iff setup was successful /// template< fapi2::TargetType T > -fapi2::ReturnCode dll_calibration( const fapi2::Target<T>& i_target ); +fapi2::ReturnCode dll_calibration( const fapi2::Target<T>& i_target, bool& o_run_workaround ); /// /// @brief Perform the DLL calibration /// @param[in] i_target the target associated with this DLL cal +/// @param[out] o_run_workaround whether we need to run workarounds /// @return FAPI2_RC_SUCCESS iff setup was successful /// template<> -fapi2::ReturnCode dll_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); +fapi2::ReturnCode dll_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, bool& o_run_workaround ); /// /// @brief Flush the output drivers diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 6eac144d1..5258d87b0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -27,10 +27,10 @@ /// @file dp16.C /// @brief Static data and subroutines to control the DP16 logic blocks /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Jacob L Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -639,7 +639,7 @@ fapi2::ReturnCode rd_vref_bitfield_helper( const fapi2::Target<T>& i_target, .set_VALUE(i_vref) .set_VREF_MAX(l_max) .set_VREF_MIN(l_min) - .set_TARGET(i_target), + .set_MCS_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target)), "Target %s VPD_MT_VREF_MC_RD percentage out of bounds (%d - %d): %d", c_str(i_target), l_max, @@ -1425,7 +1425,7 @@ fapi2::ReturnCode reset_ctle_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_targe FAPI_TRY( mss::vpd_mt_mc_dq_ctle_cap(i_target, l_ctle_cap) ); FAPI_TRY( mss::vpd_mt_mc_dq_ctle_res(i_target, l_ctle_res) ); - FAPI_INF("seeing ctle attributes cap: 0x%016lx res: 0x%016lx", l_ctle_cap, l_ctle_res); + FAPI_INF("%s seeing ctle attributes cap: 0x%016lx res: 0x%016lx", mss::c_str(i_target), l_ctle_cap, l_ctle_res); // For the capacitance CTLE attributes, they're laid out in the uint64_t as such. The resitance // attributes are the same, but 3 bits long. Notice that DP Block X Nibble 0 is DQ0:3, @@ -1601,7 +1601,7 @@ fapi2::ReturnCode reset_rd_vref( const fapi2::Target<TARGET_TYPE_MCA>& i_target l_reg_data.insertFromRight<TT::RD_VREF_BYTE0_NIB1, TT::RD_VREF_BYTE0_NIB1_LEN>(l_vref_bitfield); } - FAPI_INF("blasting VREF settings from VPD to dp16 RD_VREF registers"); + FAPI_INF("%s blasting VREF settings from VPD to dp16 RD_VREF registers", mss::c_str(i_target)); FAPI_TRY( mss::scom_blastah(i_target, RD_VREF_CNTRL_REG, l_data) ); } @@ -1695,7 +1695,7 @@ fapi2::ReturnCode get_dq_dqs_drv_imp_field_value( const fapi2::Target<TARGET_TYP fapi2::MSS_INVALID_VPD_VALUE_MC_DRV_IMP_DQ_DQS() .set_VALUE(l_vpd_value[dp]) .set_DP(dp) - .set_MCA_TARGET(i_target), + .set_MCS_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target)), "%s DQ_DQS %s impedance value is not valid: %u for DP[%u]", c_str(i_target), "driver", @@ -1829,7 +1829,7 @@ fapi2::ReturnCode get_dq_dqs_rcv_imp_field_value( const fapi2::Target<TARGET_TYP fapi2::MSS_INVALID_VPD_VALUE_MC_RCV_IMP_DQ_DQS() .set_VALUE(l_vpd_value[dp]) .set_DP(dp) - .set_MCA_TARGET(i_target), + .set_MCS_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target)), "%s DQ_DQS %s impedance value is not valid: %u for DP[%u]", c_str(i_target), "receiver", diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index 26ae89ea8..4a778c5f1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -27,10 +27,10 @@ /// @file dp16.H /// @brief Subroutines to control the DP16 logic blocks /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_DP16_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C index 54f403657..d97e6cc4b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C @@ -27,10 +27,10 @@ /// @file phy_cntrl.C /// @brief Subroutines for the PHY PC registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> @@ -38,7 +38,6 @@ #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/index.H> - #include <lib/mss_attribute_accessors.H> using fapi2::TARGET_TYPE_MCA; @@ -122,9 +121,11 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) { typedef pcTraits<TARGET_TYPE_MCA> TT; + constexpr uint64_t NUM_DIMM_TYPES = 4; + constexpr uint64_t NUM_DIMM_GEN = 3; // Static table of PHY config values for MEMORY_TYPE. // [EMPTY, RDIMM, CDIMM, or LRDIMM][EMPTY, DDR3 or DDR4] - constexpr uint64_t memory_type[4][3] = + constexpr uint64_t memory_type[NUM_DIMM_TYPES][NUM_DIMM_GEN] = { { 0, 0, 0 }, // Empty, never really used. { 0, 0b001, 0b101 }, // RDIMM @@ -149,9 +150,24 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) // There's no way to configure the PHY for more than one value. However, we don't know if there's // a DIMM in one slot, the other or double drop. So we do a little gyration here to make sure // we have one of the two values (and assume effective config caught a bad config) + // For both attributes, 0 == empty l_type_index = l_dimm_type[0] | l_dimm_type[1]; l_gen_index = l_dram_gen[0] | l_dram_gen[1]; + // These two checks should never be called, but better safe than seg fault + FAPI_ASSERT( l_type_index < NUM_DIMM_TYPES, + fapi2::MSS_INVALID_DIMM_TYPE() + .set_DIMM_TYPE(l_type_index) + .set_TARGET(i_target), + "Invalid DIMM configuration or DIMM type on %s", + mss::c_str(i_target)); + FAPI_ASSERT( l_gen_index < NUM_DIMM_GEN, + fapi2::MSS_PLUG_RULES_INVALID_DRAM_GEN() + .set_DRAM_GEN(l_gen_index) + .set_DIMM_TARGET(i_target), + "Invalid DIMM configuration or DRAM gen on %s", + mss::c_str(i_target)); + // FOR NIMBUS PHY (as the protocol choice above is) BRS FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H index ba2a14345..a4c015415 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H @@ -27,10 +27,10 @@ /// @file phy_cntrl.H /// @brief Subroutines for the PHY phy control registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_PHY_CNTRL_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H index fa50d25ee..055f0ba1d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H @@ -27,10 +27,10 @@ /// @file read_cntrl.H /// @brief Subroutines for the PHY read control registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_READ_CNTRL_H_ @@ -117,7 +117,6 @@ class rcTraits<fapi2::TARGET_TYPE_MCA> RDVREF_CALIBRATION_ENABLE = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE, SKIP_RDCENTERING = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING, }; - }; namespace rc @@ -134,7 +133,7 @@ inline fapi2::ReturnCode read_vref_config0( const fapi2::Target<T>& i_target, fa { FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG0_REG, o_data), "%s failed to read rc_vref_config0 register", mss::c_str(i_target) ); - FAPI_DBG("rc_vref_config0: 0x%016llx", o_data); + FAPI_DBG("%s rc_vref_config0: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -149,7 +148,7 @@ template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_vref_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_vref_config0: 0x%016llx", i_data); + FAPI_DBG("%s rc_vref_config0: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG0_REG, i_data), "%s failed to write rc_vref_config0 register", mss::c_str(i_target) ); fapi_try_exit: @@ -167,7 +166,7 @@ inline fapi2::ReturnCode read_vref_config1( const fapi2::Target<T>& i_target, fa { FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG1_REG, o_data), "%s failed to read rc_vref_config1 register", mss::c_str(i_target) ); - FAPI_DBG("rc_vref_config1: 0x%016llx", o_data); + FAPI_DBG("%s rc_vref_config1: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -182,14 +181,13 @@ template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_vref_config1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_vref_config1: 0x%016llx", i_data); + FAPI_DBG("%s rc_vref_config1: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG1_REG, i_data), "%s failed to write rc_vref_config1 register", mss::c_str(i_target) ); fapi_try_exit: return fapi2::current_err; } - /// /// @brief Read RC_CONFIG0 /// @param[in] i_target the fapi2 target of the port @@ -201,7 +199,7 @@ inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2:: { FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG0_REG, o_data), "%s failed to read rc_config0 register", mss::c_str(i_target) ); - FAPI_DBG("rc_config0: 0x%016llx", o_data); + FAPI_DBG("%s rc_config0: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -215,7 +213,7 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_config0: 0x%016llx", i_data); + FAPI_DBG("%s rc_config0: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG0_REG, i_data), "%s failed to write rc_config0 register", mss::c_str(i_target) ); fapi_try_exit: @@ -234,7 +232,7 @@ inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, fapi2:: { FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG1_REG, o_data), "%s failed to read rc_config1 register", mss::c_str(i_target) ); - FAPI_DBG("rc_config1: 0x%016llx", o_data); + FAPI_DBG("%s rc_config1: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -248,7 +246,7 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_config1: 0x%016llx", i_data); + FAPI_DBG("%s rc_config1: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG1_REG, i_data), "%s failed to write rc_config1 register", mss::c_str(i_target) ); fapi_try_exit: @@ -266,7 +264,7 @@ inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target, fapi2:: { FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG2_REG, o_data), "%s failed to read rc_config2 register", mss::c_str(i_target) ); - FAPI_DBG("rc_config2: 0x%016llx", o_data); + FAPI_DBG("%s rc_config2: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -280,7 +278,7 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_config2: 0x%016llx", i_data); + FAPI_DBG("%s rc_config2: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG2_REG, i_data), "%s failed to write rc_config2 register", mss::c_str(i_target) ); fapi_try_exit: @@ -298,7 +296,7 @@ inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target, fapi2:: { FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG3_REG, o_data), "%s failed to read rc_config3 register", mss::c_str(i_target) ); - FAPI_DBG("rc_config3: 0x%016llx", o_data); + FAPI_DBG("%s rc_config3: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -312,7 +310,7 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_config3: 0x%016llx", i_data); + FAPI_DBG("%s rc_config3: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG3_REG, i_data), "%s failed to write rc_config3 register", mss::c_str(i_target) ); fapi_try_exit: @@ -504,7 +502,7 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = rcTraits<T> > inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("rc_error_status0: 0x%016llx", i_data); + FAPI_DBG("%s rc_error_status0: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::RC_ERROR_STATUS0_REG, i_data), "%s failed to write rc_error_status0 register", mss::c_str(i_target) ); fapi_try_exit: @@ -524,7 +522,7 @@ inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, f { FAPI_TRY( mss::getScom(i_target, TT::RC_ERROR_STATUS0_REG, o_data), "%s failed to read rc_error_status0 register", mss::c_str(i_target) ); - FAPI_DBG("rc_error_status0: 0x%016llx", o_data); + FAPI_DBG("%s rc_error_status0: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C index 03387e173..8c5f0b02d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C @@ -27,10 +27,10 @@ /// @file seq.C /// @brief Subroutines for the PHY SEQ registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H index c62c79108..3386b9b09 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H @@ -27,7 +27,7 @@ /// @file seq.H /// @brief Subroutines for the PHY sequencer registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 2 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H index 60016b59b..9e4da36a0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H @@ -27,10 +27,10 @@ /// @file write_cntrl.H /// @brief Subroutines for the PHY write control registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _MSS_WRITE_CNTRL_H_ @@ -142,7 +142,7 @@ inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, { FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG0_REG, o_data), "%s failed to read wc_config0 register", mss::c_str(i_target) ); - FAPI_DBG("wc_config0: 0x%016llx", o_data); + FAPI_DBG("%s wc_config0: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -159,7 +159,7 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("wc_config0: 0x%016llx", i_data); + FAPI_DBG("%s wc_config0: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG0_REG, i_data), "%s failed to write wc_config0 register", mss::c_str(i_target) ); fapi_try_exit: @@ -180,7 +180,7 @@ inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, { FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG1_REG, o_data), "%s failed to read wc_config1 register", mss::c_str(i_target) ); - FAPI_DBG("wc_config1: 0x%016llx", o_data); + FAPI_DBG("%s wc_config1: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -197,7 +197,7 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("wc_config1: 0x%016llx", i_data); + FAPI_DBG("%s wc_config1: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG1_REG, i_data), "%s failed to write wc_config1 register", mss::c_str(i_target) ); fapi_try_exit: @@ -218,7 +218,7 @@ inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target, { FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG2_REG, o_data), "%s failed to read wc_config2 register", mss::c_str(i_target) ); - FAPI_DBG("wc_config2: 0x%016llx", o_data); + FAPI_DBG("%s wc_config2: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -235,7 +235,7 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("wc_config2: 0x%016llx", i_data); + FAPI_DBG("%s wc_config2: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG2_REG, i_data), "%s failed to write wc_config2 register", mss::c_str(i_target) ); fapi_try_exit: @@ -257,7 +257,7 @@ inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target, { FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG3_REG, o_data), "%s failed to read wc_config3 register", mss::c_str(i_target) ); - FAPI_DBG("wc_config3: 0x%016llx", o_data); + FAPI_DBG("%s wc_config3: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -274,7 +274,7 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("wc_config3: 0x%016llx", i_data); + FAPI_DBG("%s wc_config3: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG3_REG, i_data), "%s failed to write wc_config3 register", mss::c_str(i_target) ); fapi_try_exit: @@ -296,7 +296,7 @@ inline fapi2::ReturnCode read_rtt_wr_swap_enable( const fapi2::Target<T>& i_targ { FAPI_TRY( mss::getScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, o_data), "%s failed to read wc_rtt_wr_swap_enable register", mss::c_str(i_target) ); - FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", o_data); + FAPI_DBG("%s wc_rtt_wr_swap_enable: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } @@ -313,7 +313,7 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T inline fapi2::ReturnCode write_rtt_wr_swap_enable( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", i_data); + FAPI_DBG("%s wc_rtt_wr_swap_enable: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, i_data), "%s failed to write wc_rtt_wr_swap_enable register", mss::c_str(i_target) ); fapi_try_exit: @@ -351,7 +351,7 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target ) // 63, 0b1, any; # CUSTOM_INIT_WRITE - set to a 1 to get proper values for RD VREF l_data.setBit<TT::CUSTOM_INIT_WRITE>(); - FAPI_DBG("wc_config0 reset 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target)); + FAPI_DBG("%s wc_config0 reset 0x%llx (tWLO_tWLOE: %d)", mss::c_str(i_target), l_data, mss::twlo_twloe(i_target)); FAPI_TRY( write_config0(i_target, l_data), "%s failed to reset wc_config0 register via write", mss::c_str(i_target) ); fapi_try_exit: @@ -376,8 +376,8 @@ inline fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target ) l_data.insertFromRight<TT::SMALL_STEP, TT::SMALL_STEP_LEN>(WR_LVL_SMALL_STEP); l_data.insertFromRight<TT::WR_PRE_DLY, TT::WR_PRE_DLY_LEN>(WR_LVL_PRE_DLY); - FAPI_DBG("wc_config1 reset 0x%llx (big 0x%x small 0x%x wr_pre_dly 0x%x)", - l_data, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP, WR_LVL_PRE_DLY); + FAPI_DBG("%s wc_config1 reset 0x%llx (big 0x%x small 0x%x wr_pre_dly 0x%x)", + mss::c_str(i_target), l_data, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP, WR_LVL_PRE_DLY); FAPI_TRY( write_config1(i_target, l_data), "%s failed to reset wc_config1 register via write", mss::c_str(i_target) ); fapi_try_exit: @@ -402,7 +402,7 @@ inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target ) l_data.insertFromRight<TT::NUM_VALID_SAMPLES, TT::NUM_VALID_SAMPLES_LEN>(WR_LVL_NUM_VALID_SAMPLES); l_data.insertFromRight<TT::FW_RD_WR, TT::FW_RD_WR_LEN>(l_fw_rd_wr); - FAPI_DBG("wc_config2 reset 0x%llx", l_data); + FAPI_DBG("%s wc_config2 reset 0x%llx", mss::c_str(i_target), l_data); FAPI_TRY( write_config2(i_target, l_data), "%s failed to reset wc_config2 register via write", mss::c_str(i_target) ); fapi_try_exit: @@ -432,7 +432,7 @@ inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target ) l_data.insertFromRight<TT::MRS_CMD_DQ_OFF, TT::MRS_CMD_DQ_OFF_LEN>(CMD_DQ_OFF); } - FAPI_DBG("wc_config3 reset 0x%llx", l_data); + FAPI_DBG("%s wc_config3 reset 0x%llx", mss::c_str(i_target), l_data); FAPI_TRY( write_config3(i_target, l_data), "%s failed to reset wc_config3 register via write", mss::c_str(i_target) ); fapi_try_exit: @@ -486,7 +486,7 @@ inline fapi2::ReturnCode reset_rtt_wr_swap_enable( const fapi2::Target<T>& i_tar l_data.insertFromRight<TT::VREF_COUNTER_RESET_VAL, TT::VREF_COUNTER_RESET_VAL_LEN>(l_vref_counter_reset); } - FAPI_DBG("wc_rtt_wr_swap_enable reset 0x%llx", l_data); + FAPI_DBG("%s wc_rtt_wr_swap_enable reset 0x%llx", mss::c_str(i_target), l_data); FAPI_TRY( write_rtt_wr_swap_enable(i_target, l_data), "%s failed to reset wc_rtt_wr_swap_enable register via write", mss::c_str(i_target) ); @@ -527,7 +527,7 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = wcTraits<T> > inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) { - FAPI_DBG("wc_error_status0: 0x%016llx", i_data); + FAPI_DBG("%s wc_error_status0: 0x%016llx", mss::c_str(i_target), i_data); FAPI_TRY( mss::putScom(i_target, TT::WC_ERROR_STATUS0_REG, i_data), "%s failed to write wc_error_status0 register", mss::c_str(i_target) ); fapi_try_exit: @@ -547,7 +547,7 @@ inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, f { FAPI_TRY( mss::getScom(i_target, TT::WC_ERROR_STATUS0_REG, o_data), "%s failed to read wc_error_status0 register", mss::c_str(i_target) ); - FAPI_DBG("wc_error_status0: 0x%016llx", o_data); + FAPI_DBG("%s wc_error_status0: 0x%016llx", mss::c_str(i_target), o_data); fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 6543a8ae1..2214abb40 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -115,6 +115,7 @@ enum times DELAY_10NS = 10 , ///< general purpose 10 ns delay for HW mode DELAY_100NS = 100, ///< general purpose 100 ns delay for HW mode DELAY_1US = 1000, ///< general purpose 1 usec delay for HW mode + DELAY_10US = 10000, ///< general purpose 1 usec delay for HW mode DELAY_100US = 100000, ///< general purpose 100 usec delay for HW mode DELAY_1MS = 1000000, ///< general purpose 1 ms delay for HW mode @@ -166,6 +167,23 @@ enum states NO_CHIP_SELECT_ACTIVE = 0xFF, }; +/// +/// @brief function ID codes for FFDC functions +/// @note If we get a fail in HB, we can trace back to the function that failed +/// +enum ffdc_functions +{ + // Following are used in rank.H + RANK_PAIR_TO_PHY = 0, + RANK_PAIR_FROM_PHY = 1, + SET_RANKS_IN_PAIR = 2, + GET_RANKS_IN_PAIR = 3, + GET_RANK_FIELD = 4, + GET_PAIR_VALID = 5, + SET_RANK_FIELD = 6, + RD_CTR_WORKAROUND_READ_DATA = 7, + OVERRIDE_ODT_WR_CONFIG = 8, +}; // Static consts describing the bits used in the cal_step_enable attribute // These are bit positions. 0 is the left most bit. enum cal_steps : uint64_t diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C index 7f4144579..18c2f419e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C @@ -187,7 +187,7 @@ fapi2::ReturnCode setup_dll_control_regs( const fapi2::Target<fapi2::TARGET_TYPE // do the error check FAPI_ASSERT( l_done, fapi2::MSS_DLL_UPDATE_BIT_STUCK() - .set_TARGET(i_target) + .set_MCA_TARGET(i_target) .set_REGISTER(i_reg), "Failed to setup DLL control reg for %s 0x%016lx", mss::c_str(i_target), i_reg ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C index 38fe32402..647ec0a36 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C @@ -26,7 +26,7 @@ // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <map> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index b1ea39b4c..d510d4fee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -30,7 +30,7 @@ // *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <stdint.h> @@ -59,7 +59,6 @@ extern "C" /// fapi2::ReturnCode p9_mss_ddr_phy_reset(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) { - // If there are no DIMM we don't need to bother. In fact, we can't as we didn't setup // attributes for the PHY, etc. if (mss::count_dimm(i_target) == 0) @@ -112,12 +111,13 @@ extern "C" // complete. One of the 3 bits will be asserted for ADR and DP16. { FAPI_INF( "starting DLL calibration %s", mss::c_str(i_target) ); - fapi2::ReturnCode l_rc = mss::dll_calibration(i_target); + bool l_run_workaround = false; + fapi2::ReturnCode l_rc = mss::dll_calibration(i_target, l_run_workaround); // Only run DLL workaround if we fail DLL cal // Note: there is no EC workaround for this workaround // The designer team informed me that there is no hardware fix in plan for this type of fail as of DD2 - SPG - if( l_rc != fapi2::FAPI2_RC_SUCCESS ) + if( l_run_workaround ) { FAPI_INF( "%s Applying DLL workaround", mss::c_str(i_target) ); l_rc = mss::workarounds::dll::fix_bad_voltage_settings(i_target); @@ -203,5 +203,4 @@ extern "C" return fapi2::current_err; } - } diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml index 3288e3ca3..3f110887a 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml @@ -203,60 +203,6 @@ </registerFfdc> <hwpError> - <rc>RC_MSS_DP16_PLL_FAILED_TO_LOCK</rc> - <description> - p9_mss_ddr_phy_reset: DP16 PLL failed to lock! Value in MCA_DDRPHY_PC_DP18_PLL_LOCK_STATUS not as expected - </description> - <ffdc>EXPECTED_STATUS</ffdc> - <ffdc>ACTUAL_STATUS</ffdc> - <ffdc>REGISTER</ffdc> - <callout> - <target>MCBIST_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <callout> - <hw> - <hwid>MEM_REF_CLOCK</hwid> - <refTarget>MCBIST_IN_ERROR</refTarget> - </hw> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>MCBIST_IN_ERROR</target> - </deconfigure> - <gard> - <target>MCBIST_IN_ERROR</target> - </gard> -</hwpError> - -<hwpError> - <rc>RC_MSS_AD32S_PLL_FAILED_TO_LOCK</rc> - <description> - p9_mss_ddr_phy_reset: AD32S PLL failed to lock! Value in MCA_DDRPHY_PC_AD32S_PLL_LOCK_STATUS not as expected - </description> - <ffdc>EXPECTED_STATUS</ffdc> - <ffdc>ACTUAL_STATUS</ffdc> - <ffdc>REGISTER</ffdc> - <callout> - <target>MCBIST_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <callout> - <hw> - <hwid>MEM_REF_CLOCK</hwid> - <refTarget>MCBIST_IN_ERROR</refTarget> - </hw> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>MCBIST_IN_ERROR</target> - </deconfigure> - <gard> - <target>MCBIST_IN_ERROR</target> - </gard> -</hwpError> - -<hwpError> <rc>RC_MSS_DP16_BANG_BANG_FAILED_TO_LOCK</rc> <description> p9_mss_ddr_phy_reset: DP16 phy clock and sysclk failed to align. @@ -268,16 +214,16 @@ <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <callout> - <target>MCA_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <callout> <hw> <hwid>MEM_REF_CLOCK</hwid> <refTarget>MCA_IN_ERROR</refTarget> </hw> <priority>MEDIUM</priority> </callout> + <callout> + <target>MCA_IN_ERROR</target> + <priority>HIGH</priority> + </callout> <deconfigure> <target>MCA_IN_ERROR</target> </deconfigure> @@ -298,16 +244,16 @@ <targetType>TARGET_TYPE_MCA</targetType> </collectRegisterFfdc> <callout> - <target>MCA_IN_ERROR</target> - <priority>HIGH</priority> - </callout> - <callout> <hw> <hwid>MEM_REF_CLOCK</hwid> <refTarget>MCA_IN_ERROR</refTarget> </hw> <priority>MEDIUM</priority> </callout> + <callout> + <target>MCA_IN_ERROR</target> + <priority>HIGH</priority> + </callout> <deconfigure> <target>MCA_IN_ERROR</target> </deconfigure> @@ -339,6 +285,19 @@ </hwpError> <hwpError> + <rc>RC_MSS_NO_PRIMARY_RANK_IN_RANK_PAIR</rc> + <description> + Failed to find a primary rank in the rank pair + </description> + <ffdc>RP</ffdc> + <ffdc>MCA_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> <rc>RC_MSS_ZCNTL_FAILED_TO_COMPLETE</rc> <description> ZCAL failed to complete @@ -369,104 +328,132 @@ <ffdc>VREF_MAX</ffdc> <ffdc>VREF_MIN</ffdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> <priority>HIGH</priority> </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> </hwpError> <hwpError> -<rc>RC_MSS_INVALID_VPD_VALUE_MC_DRV_IMP_DQ_DQS</rc> -<description> - Value in the VPD for MC_DRV_IMP_DQ_DQS is not valid. -</description> -<ffdc>VALUE</ffdc> -<ffdc>DP</ffdc> -<callout> - <target>MCA_TARGET</target> - <priority>HIGH</priority> -</callout> -<deconfigure> - <target>MCA_TARGET</target> -</deconfigure> + <rc>RC_MSS_INVALID_VPD_VALUE_MC_DRV_IMP_DQ_DQS</rc> + <description> + Value in the VPD for MC_DRV_IMP_DQ_DQS is not valid. + </description> + <ffdc>VALUE</ffdc> + <ffdc>DP</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> -<rc>RC_MSS_INVALID_VPD_VALUE_MC_RCV_IMP_DQ_DQS</rc> -<description> - Value in the VPD for MC_RCV_IMP_DQ_DQS is not valid. -</description> -<ffdc>VALUE</ffdc> -<ffdc>DP</ffdc> -<callout> - <target>MCA_TARGET</target> - <priority>HIGH</priority> -</callout> -<deconfigure> - <target>MCA_TARGET</target> -</deconfigure> + <rc>RC_MSS_INVALID_VPD_VALUE_MC_RCV_IMP_DQ_DQS</rc> + <description> + Value in the VPD for MC_RCV_IMP_DQ_DQS is not valid. + </description> + <ffdc>VALUE</ffdc> + <ffdc>DP</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> -<rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CLK</rc> -<description> - Value in the VPD for MC_DRV_IMP_CLK is not valid. -</description> -<ffdc>VALUE</ffdc> -<callout> - <target>MCA_TARGET</target> - <priority>HIGH</priority> -</callout> -<deconfigure> - <target>MCA_TARGET</target> -</deconfigure> + <rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CLK</rc> + <description> + Value in the VPD for MC_DRV_IMP_CLK is not valid. + </description> + <ffdc>VALUE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> -<rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CMD_ADDR</rc> -<description> - Value in the VPD for MC_DRV_IMP_CMD_ADDR is not valid. -</description> -<ffdc>VALUE</ffdc> -<callout> - <target>MCA_TARGET</target> - <priority>HIGH</priority> -</callout> -<deconfigure> - <target>MCA_TARGET</target> -</deconfigure> + <rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CMD_ADDR</rc> + <description> + Value in the VPD for MC_DRV_IMP_CMD_ADDR is not valid. + </description> + <ffdc>VALUE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> -<rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CNTL</rc> -<description> - Value in the VPD for MC_DRV_IMP_CNTL is not valid. -</description> -<ffdc>VALUE</ffdc> -<callout> - <target>MCA_TARGET</target> - <priority>HIGH</priority> -</callout> -<deconfigure> - <target>MCA_TARGET</target> -</deconfigure> + <rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CNTL</rc> + <description> + Value in the VPD for MC_DRV_IMP_CNTL is not valid. + </description> + <ffdc>VALUE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> -<rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CSCID</rc> -<description> - Value in the VPD for MC_DRV_IMP_CSCID is not valid. -</description> -<ffdc>VALUE</ffdc> -<callout> - <target>MCA_TARGET</target> - <priority>HIGH</priority> -</callout> -<deconfigure> - <target>MCA_TARGET</target> -</deconfigure> + <rc>RC_MSS_INVALID_VPD_MT_MC_DRV_IMP_CSCID</rc> + <description> + Value in the VPD for MC_DRV_IMP_CSCID is not valid. + </description> + <ffdc>VALUE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> + <priority>HIGH</priority> + </callout> </hwpError> <hwpError> @@ -474,11 +461,22 @@ <description> The DLL update bit failed to be cleared after a number of loops </description> + <collectRegisterFfdc> + <id>REG_FFDC_DLL_REGS</id> + <target>MCA_TARGET</target> + <targetType>TARGET_TYPE_MCA</targetType> + </collectRegisterFfdc> <ffdc>REGISTER</ffdc> <callout> - <target>TARGET</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>MCA_TARGET</target> + </deconfigure> + <gard> + <target>MCA_TARGET</target> + </gard> </hwpError> <hwpError> @@ -491,9 +489,19 @@ <ffdc>REGISTER</ffdc> <ffdc>REGISTER_VALUE</ffdc> <callout> - <target>TARGET</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>MCA_TARGET</target> + </deconfigure> + <gard> + <target>MCA_TARGET</target> + </gard> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> </hwpError> <hwpError> @@ -503,14 +511,18 @@ </description> <ffdc>REGISTER</ffdc> <callout> - <target>TARGET</target> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET</target> + <target>MCA_TARGET</target> </deconfigure> <gard> - <target>TARGET</target> + <target>MCA_TARGET</target> </gard> </hwpError> @@ -521,9 +533,15 @@ </description> <ffdc>REGISTER</ffdc> <callout> - <target>TARGET</target> + <target>MCA_TARGET</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>MCA_TARGET</target> + </deconfigure> + <gard> + <target>MCA_TARGET</target> + </gard> </hwpError> <hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml index 29b825ac5..27ed176b0 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_termination_control.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -27,7 +27,7 @@ <!-- @file memory_mss_termination_control.xml --> <!-- @brief Error xml for termination control --> <!-- --> -<!-- *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> --> +<!-- *HWP HWP Owner: Jacob L Harvey <jlharvey@us.ibm.com> --> <!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> <!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> --> <!-- *HWP Team: Memory --> @@ -158,7 +158,7 @@ <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGETIN_ERROR</target> + <target>TARGET_IN_ERROR</target> </deconfigure> <gard> <target>TARGET_IN_ERROR</target> |
