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authorJacob Harvey <jlharvey@us.ibm.com>2017-07-13 15:06:13 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-07-26 10:29:10 -0400
commitfd029f5afa54473a055a9b938d53da2e556b5a75 (patch)
tree87215911f0c9d138c74abe760334dd20a5864856 /src/import/chips/p9/procedures/hwp/memory/lib/ccs
parent135d297bcee4f80451c3fd5e4061f1010fe4f6d6 (diff)
downloadtalos-hostboot-fd029f5afa54473a055a9b938d53da2e556b5a75.tar.gz
talos-hostboot-fd029f5afa54473a055a9b938d53da2e556b5a75.zip
L3 draminit and mss_lib
Change-Id: If5cae63291864da0b87d6a1e82407da9358d62d2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43121 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43278 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/ccs')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C39
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H13
2 files changed, 24 insertions, 28 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C
index 521bd0a87..d93885fec 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C
@@ -27,10 +27,10 @@
/// @file ccs.C
/// @brief Run and manage the CCS engine
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
@@ -55,7 +55,7 @@ namespace ccs
/// @return FAPI2_RC_SUCCESS iff success
///
template<>
-fapi2::ReturnCode start_stop( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, bool i_start_stop )
+fapi2::ReturnCode start_stop( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, const bool i_start_stop )
{
typedef ccsTraits<TARGET_TYPE_MCBIST> TT;
@@ -73,7 +73,6 @@ fapi_try_exit:
///
/// @brief Determine the CCS failure type
-/// @tparam T the fapi2 target type of the target for this error
/// @param[in] i_target MCBIST target
/// @param[in] i_type the failure type
/// @param[in] i_mca The port the CCS instruction is training
@@ -90,16 +89,20 @@ fapi2::ReturnCode fail_type( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
FAPI_ASSERT(STAT_READ_MISCOMPARE != i_type,
fapi2::MSS_CCS_READ_MISCOMPARE()
.set_MCBIST_TARGET(i_target)
+ .set_FAIL_TYPE(i_type)
.set_MCA_TARGET(i_mca),
"%s CCS FAIL Read Miscompare", mss::c_str(i_mca));
// This error is likely due to a bad CCS engine/ MCBIST
FAPI_ASSERT(STAT_UE_SUE != i_type,
- fapi2::MSS_CCS_UE_SUE().set_MCBIST_TARGET(i_target),
+ fapi2::MSS_CCS_UE_SUE()
+ .set_FAIL_TYPE(i_type)
+ .set_MCBIST_TARGET(i_target),
"%s CCS FAIL UE or SUE Error", mss::c_str(i_target));
FAPI_ASSERT(STAT_CAL_TIMEOUT != i_type,
fapi2::MSS_CCS_CAL_TIMEOUT()
+ .set_FAIL_TYPE(i_type)
.set_MCBIST_TARGET(i_target)
.set_MCA_TARGET(i_mca),
"%s CCS FAIL Calibration Operation Time Out", mss::c_str(i_mca));
@@ -128,7 +131,7 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<TARGET_TYPE_MCBIST>& i_
fapi2::buffer<uint64_t> status;
- FAPI_TRY(start_stop(i_target, mss::START));
+ FAPI_TRY(start_stop(i_target, mss::START), "%s Error in execute_inst_array", mss::c_str(i_port) );
mss::poll(i_target, TT::STATQ_REG, i_program.iv_poll,
[&status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool
@@ -142,13 +145,14 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<TARGET_TYPE_MCBIST>& i_
// Check for done and success. DONE being the only bit set.
if (status == STAT_QUERY_SUCCESS)
{
- FAPI_INF("CCS Executed Successfully.");
+ FAPI_INF("%s CCS Executed Successfully.", mss::c_str(i_port) );
goto fapi_try_exit;
}
// So we failed or we're still in progress. Mask off the fail bits
// and run this through the FFDC generator.
- FAPI_TRY( fail_type(i_target, status & 0x1C00000000000000, i_port) );
+ // TK: Put the const below into a traits class? -- JLH
+ FAPI_TRY( fail_type(i_target, status & 0x1C00000000000000, i_port), "Error in execute_inst_array" );
fapi_try_exit:
return fapi2::current_err;
@@ -181,15 +185,14 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
auto l_inst_iter = i_program.iv_instructions.begin();
// Stop the CCS engine just for giggles - it might be running ...
- FAPI_TRY( start_stop(i_target, mss::states::STOP) );
+ FAPI_TRY( start_stop(i_target, mss::states::STOP), "Error in ccs::execute" );
FAPI_ASSERT( mss::poll(i_target, TT::STATQ_REG, poll_parameters(),
[](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool
{
FAPI_INF("ccs statq (stop) 0x%llx, remaining: %d", stat_reg, poll_remaining);
return stat_reg.getBit<TT::CCS_IN_PROGRESS>() != 1;
}),
- fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target),
- "CCS appears hung (trying to stop)");
+ fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target));
while (l_inst_iter != i_program.iv_instructions.end())
{
@@ -207,8 +210,8 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
// simple (straight line) CCS programs. Anything with a loop or such will need another mechanism.
l_inst_iter->arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_GOTO_CMD,
MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN>(l_inst_count + 1);
- FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0) );
- FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1) );
+ FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0), "Error in ccs::execute" );
+ FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1), "Error in ccs::execute" );
// arr1 contains a specification of the delay and repeat after this instruction, as well
// as a repeat. Total up the delays as we go so we know how long to wait before polling
@@ -244,8 +247,8 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
// here as an instruction forces the CCS engine to wait the delay specified in
// the last instruction in this array (which it otherwise doesn't do.)
l_des.arr1.setBit<MCBIST_CCS_INST_ARR1_00_END>();
- FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0) );
- FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1) );
+ FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0), "Error in ccs::execute" );
+ FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1), "Error in ccs::execute" );
FAPI_INF("css inst %d fixup: 0x%016lX 0x%016lX (0x%lx, 0x%lx) %s",
l_inst_count, l_des.arr0, l_des.arr1,
@@ -255,8 +258,8 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target,
for (const auto& p : i_ports)
{
FAPI_INF("executing CCS array for port %d (%s)", mss::relative_pos<TARGET_TYPE_MCBIST>(p), mss::c_str(p));
- FAPI_TRY( select_ports( i_target, mss::relative_pos<TARGET_TYPE_MCBIST>(p)) );
- FAPI_TRY( execute_inst_array(i_target, i_program, p) );
+ FAPI_TRY( select_ports( i_target, mss::relative_pos<TARGET_TYPE_MCBIST>(p)), "Error in ccs execute" );
+ FAPI_TRY( execute_inst_array(i_target, i_program, p), "Error in ccs execute" );
}
}
@@ -267,8 +270,6 @@ fapi_try_exit:
///
/// @brief Nimbus specialization for modeq_copy_cke_to_spare_cke
-/// @tparam T the fapi2::TargetType - derived
-/// @tparam TT the ccsTraits associated with T - derived
/// @param[in] fapi2::Target<TARGET_TYPE_MCBIST>& the target to effect
/// @param[in,out] the buffer representing the mode register
/// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
index c3a680790..56fa05e99 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
@@ -27,7 +27,7 @@
/// @file ccs.H
/// @brief Run and manage the CCS engine
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
@@ -174,6 +174,9 @@ namespace mss
namespace ccs
{
+///
+/// @brief Enums for CCS return codes
+///
enum
{
// Success is defined as done-bit set, no others.
@@ -324,7 +327,6 @@ class program
/// @tparam T the target type of the chiplet which executes the CCS instruction
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in,out] i_arr0 fapi2::buffer<uint64_t> representing the ARR0 of the instruction
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
static void mrs_rcd_helper( fapi2::buffer<uint64_t>& i_arr0 )
@@ -679,7 +681,6 @@ inline instruction_t<T> precharge_all_command( const fapi2::Target<fapi2::TARGET
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in] i_target the target to effect
/// @param[in] i_ports the buffer representing the ports
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline fapi2::ReturnCode select_ports( const fapi2::Target<T>& i_target, uint64_t i_ports)
@@ -706,7 +707,6 @@ fapi_try_exit:
/// @param[in] the target to effect
/// @param[in,out] io_buffer the buffer representing the mode register
/// @param[in] i_value true iff stop whenever failure occurs.
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline void stop_on_err( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value)
@@ -720,7 +720,6 @@ inline void stop_on_err( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_bu
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in] the target to effect
/// @param[in,out] io_buffer the buffer representing the mode register
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline void disable_ecc( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer)
@@ -737,7 +736,6 @@ inline void disable_ecc( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_bu
/// @param[in] the target to effect
/// @param[in,out] io_buffer the buffer representing the mode register
/// @param[in] i_value true iff ignore any array ue or sue errors.
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline void ue_disable( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value)
@@ -752,7 +750,6 @@ inline void ue_disable( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buf
/// @param[in] the target to effect
/// @param[in,out] io_buffer the buffer representing the mode register
/// @param[in] i_value mss::ON iff delay parity a cycle
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline void parity_after_cmd( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value)
@@ -768,7 +765,6 @@ inline void parity_after_cmd( const fapi2::Target<T>&, fapi2::buffer<uint64_t>&
/// @param[in,out] io_buffer the buffer representing the mode register
/// @param[in] i_count the count to wait for DDR cal to complete.
/// @param[in] i_mult the DDR calibration time multiplaction factor
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline void cal_count( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer,
@@ -790,7 +786,6 @@ inline void cal_count( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buff
/// @param[in,out] io_buffer the buffer representing the mode register
/// @param[in] i_value mss::ON iff Copy CKE signals to CKE Spare on both ports
/// @note no-op for p9n
-/// @return void
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
void copy_cke_to_spare_cke( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value);
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