PM: Added support for PGPE Boot/PGPE integration

- support for P-State parameter block
- implements a compact image layout of PGPE similar to CME/SGPE.
- adds PGPE boot progress code as a field in PPMR header.
- implements PGPE boot loader and PGPE boot copier.
- incorporates ability to generate PPMR header in the build flow.
- change logic for calculating CME's first block copy length.
- Turned on generated tables in PGPE Hcode
- Fixed up pointers to generated tables
- add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE ops
- fix p9_pstate_parameter_build bug with AVS timing attributes
- Make OCC Pstate Parameter block a fixed offset (128KB) in PPMR
- Make Pstate Table from PGPE a fixed offset (144KB) in PPMR to ease debug
- Fix Endianes issues in OCC PPB and input slope calcs
- Added PGPE Hcode Length to PGPE header so that GPPB SRAM location is known.
- Build flag for OCc Immediate IPC response
- Build flag to no use temp boot settings
- Expanding tracing for debug
- Added default values for PBAX attributes as placeholders for MRW in firmware
- Added WOF VFRT structure definions to headers;  movement into HOMER NOT
  yet supported
- Addressed review comments and rebased
- Rebased with ATTR_PGPE_HCODE_FUNCTION_ENABLE in separate commit for Cronus

Change-Id: I4752debbc7fb3275d4e79804333654511de427ff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26115
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26116
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 27 insertions, 11 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
index ca3a260b0..67be858be 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -36,11 +36,22 @@
 #define __P9_PSTATES_OCC_H__
 
 #include <p9_pstates_common.h>
+#include <p9_pstates_pgpe.h>
 
+#ifndef __ASSEMBLER__
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/// PstateParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures.  The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define OCC_PARMSBLOCK_MAGIC 0x4f43435050423030ull /* OCCPPB00 */
+
 /// IDDQ Reading Type
 /// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a
 /// maximum value of 409.6A to be represented.
@@ -51,7 +62,7 @@ typedef uint16_t iddq_entry_t;
 /// Each entry is 1 byte. The values are in 0.5degC units; this allow for a
 /// maximum value of 127degC to be represented.
 ///
-typedef uint16_t avgtemp_entry_t;
+typedef uint8_t avgtemp_entry_t;
 
 /// Iddq Table
 ///
@@ -76,10 +87,10 @@ typedef struct
     uint8_t     good_caches_per_sort;
 
     /// Good Normal Cores
-    uint8_t     good_normal_cores[MAX_QUADS];
+    uint8_t     good_normal_cores[MAXIMUM_QUADS];
 
     /// Good Caches
-    uint8_t     good_caches[MAX_QUADS];
+    uint8_t     good_caches[MAXIMUM_QUADS];
 
     /// RDP to TDP Scaling Factor in 0.01% units
     uint16_t    rdp_to_tdp_scale_factor;
@@ -103,10 +114,10 @@ typedef struct
     iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS];
 
     /// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units
-    iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+    iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
 
-    /// IVDDN ; 6.25mA units
-    iddq_entry_t ivdn;
+    /// IVDDN  6.25mA units
+    iddq_entry_t ivdn[IDDQ_MEASUREMENTS];
 
 
     /// IVDD ALL Good Cores ON, Caches ON; 6.25mA units
@@ -119,11 +130,14 @@ typedef struct
     avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS];
 
     /// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units
-    avgtemp_entry_t avgtemp_quad_good_cores_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+    avgtemp_entry_t avgtemp_quad_good_cores_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
 
     /// avgtempN ; 6.25mA units
     avgtemp_entry_t avgtemp_vdn;
 
+    /// spare (per MVPD documentation
+    uint8_t spare_1[43];
+
 } IddqTable;
 
 
@@ -132,6 +146,9 @@ typedef struct
 /// comsumption by the OCC firmware.  This data will reside in the Quad
 /// Power Management Region (QPMR).
 ///
+/// This structure is aligned to 128B to allow for easy downloading using the
+/// OCC block copy engine
+///
 typedef struct
 {
 
@@ -168,11 +185,10 @@ typedef struct
     // Minimum Pstate;  Maximum is always 0.
     uint32_t pstate_min;    // Comes from PowerSave #V point after biases
 
-} OCCPstateParmBlock;
-
+} __attribute__((aligned(128))) OCCPstateParmBlock;
 
 #ifdef __cplusplus
 } // end extern C
 #endif
-
+#endif    /* __ASSEMBLER__ */
 #endif    /* __P9_PSTATES_OCC_H__ */