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authorPrem Shanker Jha <premjha2@in.ibm.com>2016-06-08 05:48:31 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-03-01 13:58:01 -0500
commitd3d4ae7c89e6b35fffa8857170762992dc3c6538 (patch)
treefbdb27d57e114993d527ff5b43f12e285ad8eb66 /src/import/chips/p9/procedures
parentaba5dad89d16464fbf1a9228f5c44c5972e9d070 (diff)
downloadtalos-hostboot-d3d4ae7c89e6b35fffa8857170762992dc3c6538.tar.gz
talos-hostboot-d3d4ae7c89e6b35fffa8857170762992dc3c6538.zip
PM: Added support for PGPE Boot/PGPE integration
- support for P-State parameter block - implements a compact image layout of PGPE similar to CME/SGPE. - adds PGPE boot progress code as a field in PPMR header. - implements PGPE boot loader and PGPE boot copier. - incorporates ability to generate PPMR header in the build flow. - change logic for calculating CME's first block copy length. - Turned on generated tables in PGPE Hcode - Fixed up pointers to generated tables - add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE ops - fix p9_pstate_parameter_build bug with AVS timing attributes - Make OCC Pstate Parameter block a fixed offset (128KB) in PPMR - Make Pstate Table from PGPE a fixed offset (144KB) in PPMR to ease debug - Fix Endianes issues in OCC PPB and input slope calcs - Added PGPE Hcode Length to PGPE header so that GPPB SRAM location is known. - Build flag for OCc Immediate IPC response - Build flag to no use temp boot settings - Expanding tracing for debug - Added default values for PBAX attributes as placeholders for MRW in firmware - Added WOF VFRT structure definions to headers; movement into HOMER NOT yet supported - Addressed review comments and rebased - Rebased with ATTR_PGPE_HCODE_FUNCTION_ENABLE in separate commit for Cronus Change-Id: I4752debbc7fb3275d4e79804333654511de427ff Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26115 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26116 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H179
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h33
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h16
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h153
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h38
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h21
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h5
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C599
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk3
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C465
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H11
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk1
12 files changed, 1159 insertions, 365 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index cf9e8b1a6..a438b6250 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -35,33 +35,40 @@
#ifndef __HW_IMG_DEFINE
#define __HW_IMG_DEFINE
-
#include <p9_hcd_header_defs.H>
+#include <p9_pstates_cmeqm.h>
+#include <p9_pstates_common.h>
+#include <p9_pstates_occ.h>
+#include <p9_pstates_pgpe.h>
+#include <p9_pstates_table.h>
+
//--------------------------------------------------------------------------
// local structs and constants
// -------------------------------------------------------------------------
#ifndef __ASSEMBLER__
-
+#ifdef __cplusplus
#ifndef __PPE_PLAT
namespace p9_hcodeImageBuild
{
#endif //__PPE_PLAT
+#endif //__cplusplus
#endif //__ASSEMBLER__
-
// Constants used in both C++ and Assembler/Linker code
CONST_UINT32_T(CPMR_HEADER_SIZE, 256);
CONST_UINT32_T(QPMR_HEADER_SIZE, 512);
+CONST_UINT32_T(PPMR_HEADER_SIZE, 512);
+CONST_UINT32_T(PGPE_IVPR_ADDR, 0xfff20000);
//#pragma message (STR(CPMR_HEADER_SIZE))
// Define the Magic Numbers for the various images
HCD_MAGIC_NUMBER(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)); // CPMR_1.0
-HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)); // QPMR_1.0
HCD_MAGIC_NUMBER(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)); // CME__1.0
+HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)); // QPMR_1.0
HCD_MAGIC_NUMBER(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30 )); // SGPE_1.0
+HCD_MAGIC_NUMBER(PPMR_MAGIC_NUMBER, ULL(0x50504d525f312e30)); // PPMR_1.0
HCD_MAGIC_NUMBER(PGPE_MAGIC_NUMBER , ULL(0x504750455F312E30)); // PGPE_1.0
-
/**
* @brief models QPMR header in HOMER
*/
@@ -124,7 +131,7 @@ typedef struct
{
#endif
HCD_HDR_ATTN ( attnOpcodes, 2);
-HCD_HDR_UINT64( magic_number, CPMR_MAGIC_NUMBER); // CPMR_1.0
+HCD_HDR_UINT64( magic_number, CPMR_MAGIC_NUMBER);
HCD_HDR_UINT32( cpmrbuildDate, 0);
HCD_HDR_UINT32( cpmrVersion, 0);
HCD_HDR_UINT8_VEC (cpmrReserveFlags, 7, 0);
@@ -139,16 +146,63 @@ HCD_HDR_UINT32( coreSpecRingOffset, 0);
HCD_HDR_UINT32( coreSpecRingLength, 0);
HCD_HDR_UINT32( coreScomOffset, 0);
HCD_HDR_UINT32( coreScomLength, 0);
-HCD_HDR_PAD(256);
+HCD_HDR_PAD(CPMR_HEADER_SIZE);
#ifdef __ASSEMBLER__
.endm
#else
} __attribute__((packed, aligned(256))) cpmrHeader_t;
#endif
+
// @todo Get around the above hardcoding.
/**
+ * PPMR Header
+ *
+ * This header is only consumed by Hcode Image Build and
+ * lab tools, not by PPE code. It is generated with assembler
+ * primitives during PGPE build and placed in HOMER by
+ * Hcode Image Build.
+ */
+
+#ifdef __ASSEMBLER__
+.macro .ppmr_header
+.section ".ppmr_header" , "aw"
+.balign 8
+#else
+typedef struct
+{
+#endif
+//Offset are wrt to start of PPMR unless specified otherwise
+//length in bytes unless specified otherwise.
+HCD_HDR_UINT64(g_ppmr_magic_number, PPMR_MAGIC_NUMBER); // PPMR_1.0
+HCD_HDR_UINT32(g_ppmr_bc_offset, 0 ); // PGPE Level1 Boot loader
+HCD_HDR_UINT32(g_ppmr_reserve1, 0 );
+HCD_HDR_UINT32(g_ppmr_bl_offset, 0 ); // PGPE Level2 Boot loader
+HCD_HDR_UINT32(g_ppmr_bl_length, 0 ); // PGPE Level2 Boot loader
+HCD_HDR_UINT32(g_ppmr_build_date, 0 ); // Build date for PGPE Image
+HCD_HDR_UINT32(g_ppmr_build_ver, 0 ); // Build Version
+HCD_HDR_UINT64(g_ppmr_reserve_flag, 0 ); // Reserve Flag
+HCD_HDR_UINT32(g_ppmr_hcode_offset, 0 ); // Offset to start of PGPE Hcode
+HCD_HDR_UINT32(g_ppmr_hcode_length, 0 ); // PGPE Hcode length in Bytes
+HCD_HDR_UINT32(g_ppmr_gppb_offset, 0 ); // Offset to Global P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_gppb_length, 0 ); // Length of Global P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_lppb_offset, 0 ); // Offset to Local P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_lppb_length, 0 ); // Length of Local P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_oppb_offset, 0 ); // Offset to OCC P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_oppb_length, 0 ); // Length of OCC P State Parameter Block
+HCD_HDR_UINT32(g_ppmr_pstables_offset, 0); // Offset to PState Table
+HCD_HDR_UINT32(g_ppmr_pstables_length, 0); // Length of P State table
+HCD_HDR_UINT32(g_ppmr_pgpe_sram_img_size, 0); // PGPE Actual SRAM Image Size
+HCD_HDR_UINT32(g_ppmr_pgpe_boot_prog_code, 0 );// for debug of PGPE booting
+HCD_HDR_PAD(0x200);
+#ifdef __ASSEMBLER__
+.endm
+#else
+} __attribute__((packed, aligned(0x200))) PpmrHeader_t;
+#endif
+
+/**
* SGPE Header
*
* The SGPE header is loaded in the OCC SRAM. Structure member names are
@@ -169,7 +223,7 @@ HCD_HDR_PAD(256);
typedef struct
{
#endif
-HCD_HDR_UINT64(g_sgpe_magic_number, P9_XIP_MAGIC_SGPE); //XIP SGPE
+HCD_HDR_UINT64(g_sgpe_magic_number, SGPE_MAGIC_NUMBER); //SGPE 1.0
HCD_HDR_UINT32(g_sgpe_reset_address, 0);
HCD_HDR_UINT32(g_sgpe_reserve1, 0);
HCD_HDR_UINT32(g_sgpe_ivpr_address, 0);
@@ -214,7 +268,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
typedef struct
{
#endif
-HCD_HDR_UINT64(g_cme_magic_number, CME_MAGIC_NUMBER); // CME__1.0
+HCD_HDR_UINT64(g_cme_magic_number, CME_MAGIC_NUMBER);
HCD_HDR_UINT32(g_cme_hcode_offset, 0);
HCD_HDR_UINT32(g_cme_hcode_length, 0);
HCD_HDR_UINT32(g_cme_common_ring_offset, 0);
@@ -255,25 +309,40 @@ typedef struct CMEImageFlags
* PGPE Header
*
* The PGPE header is loaded in the OCC SRAM so it is "tight" (little extra space)
- * Thus, this "structure" is NOT padded to a specific size and is limited to
- * 64B. Also, structure member names are preceded with "g_" as these becoming
- * global variables in the CME Hcode.
+ * Also, structure member names are preceded with "g_" as these becoming
+ * global variables in the PGPE Hcode.
*/
#ifdef __ASSEMBLER__
.macro .pgpe_header
-.section ".pgpe_header" , "aw"
+.section ".pgpe_image_header" , "aw"
.balign 8
#else
typedef struct
{
#endif
-HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER); // PGPE_1.0
-HCD_HDR_UINT32(g_pgpe_build_date, 0);
-HCD_HDR_UINT32(g_pgpe_build_ver, 0);
-HCD_HDR_UINT32(g_pgpe_hcode_offset, 0);
-HCD_HDR_UINT32(g_pgpe_hcode_length, 0);
-HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
-//FIXME Need to get info on other fields
+HCD_HDR_UINT64(g_pgpe_magic_number, PGPE_MAGIC_NUMBER); // PGPE_1.0
+HCD_HDR_UINT32(g_pgpe_sys_reset_addr, 0 ); // Fully qualified OCC address where pk_init resides
+HCD_HDR_UINT32(g_pgpe_shared_sram_addr, 0 ); // SRAM address where shared SRAM begins
+HCD_HDR_UINT32(g_pgpe_ivpr_addr, PGPE_IVPR_ADDR ); // Beginning of PGPE region in OCC SRAM
+HCD_HDR_UINT32(g_pgpe_shared_sram_len, 0 ); // Length of shared SRAM area
+HCD_HDR_UINT32(g_pgpe_build_date, 0 ); // Build date for PGPE Image
+HCD_HDR_UINT32(g_pgpe_build_ver, 0 ); // Build Version
+HCD_HDR_UINT16(g_pgpe_flags, 0 ); // PGPE Flags
+HCD_HDR_UINT16(g_pgpe_reserve1, 0 ); // Reserve field
+HCD_HDR_UINT32(g_pgpe_reserve2, 0 ); // Reserve field
+HCD_HDR_UINT32(g_pgpe_gppb_sram_addr, 0 ); // Offset to Global P State Parameter Block
+HCD_HDR_UINT32(g_pgpe_hcode_length, 0 ); // Length of PGPE Hcode
+HCD_HDR_UINT32(g_pgpe_gppb_mem_offset,
+ 0 ); // Offset to start of Global PS Param Block wrt start of HOMER.
+HCD_HDR_UINT32(g_pgpe_gppb_length, 0 ); // Length of Global P State Parameter Block
+HCD_HDR_UINT32(g_pgpe_gen_pstables_mem_offset, 0 ); // Offset to PState Table wrt start of HOMER
+HCD_HDR_UINT32(g_pgpe_gen_pstables_length, 0 ); // Length of P State table
+HCD_HDR_UINT32(g_pgpe_occ_pstables_sram_addr, 0 ); // Offset to start of OCC P-State table
+HCD_HDR_UINT32(g_pgpe_occ_pstables_len, 0 ); // Length of OCC P-State table
+HCD_HDR_UINT32(g_pgpe_beacon_addr, 0 ); // SRAM addr where PGPE beacon is located
+HCD_HDR_UINT32(g_quad_status_addr, 0 );
+HCD_HDR_UINT32(g_wof_table_addr, 0 );
+HCD_HDR_UINT32(g_wof_table_length, 0 );
#ifdef __ASSEMBLER__
.endm
#else
@@ -409,17 +478,39 @@ enum
SGPE_PROC_FAB_ADDR_BAR_MODE_POS = 0x00008000,
// PPMR
-
//** Boot Loaders
- PGPE_LVL_1_BOOT_LOAD_SIZE = ONE_KB,
- PGPE_LVL_2_BOOT_LOAD_SIZE = ONE_KB,
- PGPE_INT_VECTOR = 384,
- PGPE_HCODE_SIZE = 30 * ONE_KB,
- PGPE_PARAM_BLOCK_SIZE = 8 * ONE_KB, //Global and OCC PPB
- PSTATE_OUTPUT_TABLE = 8 * ONE_KB,
-
- PGPE_MAX_AREA_SIZE = 48 * ONE_KB, // @todo RTC 158543 Reallocate space
-
+ PPMR_OFFSET = HOMER_PPMR_REGION_NUM * ONE_MB,
+ PPMR_HEADER_LEN = 512,
+ PGPE_LVL_1_BOOT_LOAD_SIZE = ONE_KB,
+ PGPE_LVL_2_BOOT_LOAD_SIZE = ONE_KB,
+ PGPE_MAX_AREA_SIZE = 48 * ONE_KB, // @todo RTC 158543 Reallocate space
+
+ PGPE_HOMER_SRAM_ALLOC = 128 * ONE_KB,
+ PGPE_HOMER_SRAM_RESERVE = PGPE_HOMER_SRAM_ALLOC -
+ (PPMR_HEADER_LEN +
+ PGPE_LVL_1_BOOT_LOAD_SIZE +
+ PGPE_LVL_2_BOOT_LOAD_SIZE +
+ PGPE_MAX_AREA_SIZE),
+
+ PGPE_INT_VECTOR = 384,
+ PGPE_HCODE_SIZE = 32 * ONE_KB,
+ PGPE_PARAM_BLOCK_SIZE = 8 * ONE_KB,
+
+ // @todo: get these from the p9_homer_map.h file
+ HOMER_OOC_PARAM_BLOCK_ADDR = 0x00320000, // PPMR + 128KB
+ HOMER_PSTATE_OUTPUT_TABLE_ADDR = 0x00324000, // PPMR + 144KB
+ HOMER_WOF_TABLE_ADDR = 0x003C0000, // PPMR + 768KB (the last 256KB)
+
+ OCC_PARAM_BLOCK_ALLOC = 16 * ONE_KB,
+ OCC_PARAM_BLOCK_SIZE = 8 * ONE_KB,
+
+ PSTATE_OUTPUT_TABLE_ALLOC = 16 * ONE_KB,
+ PSTATE_OUTPUT_TABLE_SIZE = 8 * ONE_KB,
+
+ WOF_TABLES_BLOCK_ALLOC = 256 * ONE_KB,
+
+ OCI_SRAM_ADDR_BASE = 0xFFF20000, // @todo: what is this for?
+ OCI_PBA_ADDR_BASE = 0x80300000,
IGNORE_CHIPLET_INSTANCE = 0xFF,
//RING LAYOUT
@@ -468,6 +559,7 @@ enum ImgBldRetCode_t
CME_SRAM_IMG_SIZE_ERR = 31,
SGPE_SRAM_IMG_SIZE_ERR = 32,
PGPE_SRAM_IMG_SIZE_ERR = 33,
+ BUILD_FAIL_PGPE_PPMR = 34,
};
/**
@@ -658,24 +750,17 @@ typedef struct
/**
* @brief models image section associated with PGPE in HOMER.
*/
-typedef union PgpeHcodeLayout
-{
- uint8_t hcode[PGPE_HCODE_SIZE];
- struct
- {
- uint8_t pgpeIntVector[PGPE_INT_VECTOR];
- PgpeHeader_t imgHeader;
- uint8_t exe[PGPE_HCODE_SIZE - PGPE_INT_VECTOR - sizeof(PgpeHeader_t)];
- } elements;
-} PgpeHcodeLayout_t;
-
typedef struct
{
- uint8_t l1BootLoader[PGPE_LVL_1_BOOT_LOAD_SIZE];
- uint8_t l2BootLoader[PGPE_LVL_2_BOOT_LOAD_SIZE];
- PgpeHcodeLayout_t pgpeBin;
- uint8_t paramBlock[PGPE_PARAM_BLOCK_SIZE];
- uint8_t pstateOutputTable[PSTATE_OUTPUT_TABLE];
+ uint8_t ppmrHeader[PPMR_HEADER_LEN];
+ uint8_t l1BootLoader[PGPE_LVL_1_BOOT_LOAD_SIZE];
+ uint8_t l2BootLoader[PGPE_LVL_2_BOOT_LOAD_SIZE];
+ uint8_t pgpeSramImage[PGPE_MAX_AREA_SIZE]; // Includes the Global Pstate Parameter Block
+ uint8_t ppmr_reserved0[PGPE_HOMER_SRAM_RESERVE];
+ uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB
+ uint8_t occParmBlockReserve[OCC_PARAM_BLOCK_ALLOC - sizeof(OCCPstateParmBlock)];
+ uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB
+ uint8_t pstateTableReserve[PSTATE_OUTPUT_TABLE_ALLOC - sizeof(GeneratedPstateInfo)];
} PPMRLayout_t;
/**
@@ -702,9 +787,11 @@ typedef struct
uint8_t pgpeReserve[ONE_MB - sizeof( PPMRLayout_t )];
} Homerlayout_t;
+#ifdef __cplusplus
#ifndef __PPE_PLAT
}// namespace p9_hcodeImageBuild ends
#endif //__PPE_PLAT
+#endif //__cplusplus
#endif //__ASSEMBLER__
#endif //__HW_IMG_DEFINE
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
index f1760cc6c..fe5848944 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -134,6 +134,37 @@ typedef union occ_scratch2
} fields;
} occ_scratch2_t;
+typedef union pgpe_flags
+{
+ uint16_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint16_t resclk_enable : 1;
+ uint16_t ivrm_enable : 1;
+ uint16_t vdm_enable : 1;
+ uint16_t wof_enable : 1;
+ uint16_t dpll_dynamic_fmax_enable : 1;
+ uint16_t dpll_dynamic_fmin_enable : 1;
+ uint16_t dpll_droop_protect_enable : 1;
+ uint16_t reserved7 : 1;
+ uint16_t occ_ipc_immed_response : 1;
+ uint16_t reserved_9_15 : 7;
+#else
+ uint16_t reserved_9_15 : 7;
+ uint16_t occ_ipc_immed_response : 1;
+ uint16_t reserved7 : 1;
+ uint16_t dpll_droop_protect_enable : 1;
+ uint16_t dpll_dynamic_fmin_enable : 1;
+ uint16_t dpll_dynamic_fmax_enable : 1;
+ uint16_t wof_enable : 1;
+ uint16_t vdm_enable : 1;
+ uint16_t ivrm_enable : 1;
+ uint16_t resclk_enable : 1;
+#endif
+ } fields;
+} pgpe_flags_t;
+
typedef union cme_flags
{
uint32_t value;
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h
index 20b216e34..6a7cab9b1 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -34,6 +34,7 @@
#ifndef __P9_PSTATES_CME_H__
#define __P9_PSTATES_CME_H__
+#include <p9_pstates_common.h>
/// \defgroup QM Flags
///
@@ -64,13 +65,22 @@
/// @}
-
+#ifndef __ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
+/// LocalParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures. The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define LOCAL_PARMSBLOCK_MAGIC 0x434d455050423030ull /* CMEPPB00 */
+
/// Quad Manager Flags
///
@@ -292,5 +302,5 @@ typedef struct
#ifdef __cplusplus
} // end extern C
#endif
-
+#endif /* __ASSEMBLER__ */
#endif /* __P9_PSTATES_CME_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
index bc90d7231..f698aa989 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h
@@ -35,13 +35,13 @@
#ifndef __P9_PSTATES_COMMON_H__
#define __P9_PSTATES_COMMON_H__
-/// The minimum Pstate (knowing the increasing Pstates numbers represent
+/// The maximum Pstate (knowing the increasing Pstates numbers represent
/// decreasing frequency)
-#define PSTATE_MIN 255
+#define PSTATE_MAX 255
-/// The maximum Pstate (knowing the increasing Pstates numbers represent
+/// The minimum Pstate (knowing the increasing Pstates numbers represent
/// decreasing frequency)
-#define PSTATE_MAX 0
+#define PSTATE_MIN 0
/// The minimum \e legal DPLL frequency code
///
@@ -83,7 +83,7 @@
#define IVID_STEP_UV 4000
/// Maximum number of Quads (4 cores plus associated caches)
-#define MAX_QUADS 6
+#define MAXIMUM_QUADS 6
// Constants associated with VRM stepping
// @todo Determine what is needed here (eg Attribute mapping) and if any constants
@@ -130,7 +130,8 @@
#define IDDQ_MEASUREMENTS 6
#define MEASUREMENT_ELEMENTS 6 // Number of Quads for P9
#define IDDQ_READINGS_PER_IQ 2
-#define IDDQ_ARRAY_VOLTAGES {0.60, 0.70, 0.80, 0.90, 1.00, 1.10}
+#define IDDQ_ARRAY_VOLTAGES { 0.60 , 0.70 , 0.80 , 0.90 , 1.00 , 1.10}
+#define IDDQ_ARRAY_VOLTAGES_STR {"0.60", "0.70", "0.80", "0.90", "1.00", "1.10"}
/// WOF Items
#define NUM_ACTIVE_CORES 24
@@ -170,6 +171,7 @@
#define LPST_GPST_WARNING 0x00477902
#define LPST_INCR_CLIP_ERROR 0x00477903
+#ifndef __ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
@@ -198,15 +200,13 @@ typedef uint16_t VidAVS;
///
typedef struct
{
-
uint32_t vdd_mv;
uint32_t vcs_mv;
uint32_t idd_100ma;
uint32_t ics_100ma;
uint32_t frequency_mhz;
uint8_t pstate; // Pstate of this VpdOperating
- uint8_t pad[3];
-
+ uint8_t pad[3]; // Alignment padding
} VpdOperatingPoint;
/// VPD Biases.
@@ -258,16 +258,141 @@ typedef struct
// WOF Voltage, Frequency Ratio Tables
//
+// VFRT Header
+
+typedef struct
+{
+
+ /// Magic Number
+ /// Set to ASCII "VT"
+ uint16_t magic_number;
+
+ /// Indicator
+ /// Space for generation tools to be anything unique necessary to ID this
+ /// VFRT
+ uint16_t indicator;
+
+ union
+ {
+ uint8_t value;
+ struct
+ {
+ uint8_t type : 4;
+ uint8_t version : 4;
+ } fields;
+ } typever;
+
+ uint8_t reserved;
+
+ union
+ {
+ uint16_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint16_t reserved: 4;
+ uint16_t vdn_id : 4;
+ uint16_t vdd_id : 4;
+ uint16_t qa_id : 4;
+#else
+ uint16_t qa_id : 4;
+ uint16_t vdd_id : 4;
+ uint16_t vdn_id : 4;
+ uint16_t reserved: 4;
+#endif // _BIG_ENDIAN
+
+ } fields;
+ } ids;
+
+} VFRTHeader_t;
+
+// WOF Tables Header
+
+typedef struct
+{
+
+ /// Magic Number
+ /// Set to ASCII "VFRT___x" where x is the version of the VFRT structure
+ uint64_t magic_number;
+
+ /// VFRT Size
+ /// Length, in bytes, of a VFRT
+ uint8_t vfrt_size;
+
+ /// VFRT Data Size
+ /// Length, in bytes, of the data field.
+ uint8_t vfrt_data_size;
+
+ uint8_t reserved;
+
+ /// Quad Active Size
+ /// Total number of Active Quads
+ uint8_t quads_active_size;
+
+ /// Ceff Vdn Start
+ /// CeffVdn value represented by index 0 (in percent)
+ uint8_t vdn_start;
+
+ /// Ceff Vdn Step
+ /// CeffVdn step value for each CeffVdn index (in percent)
+ uint8_t vdn_step;
+
+ /// Ceff Vdn Size
+ /// Number of CeffVdn indexes
+ uint8_t vdn_size;
+
+ /// Ceff Vdd Start
+ /// CeffVdd value represented by index 0 (in percent)
+ uint8_t vdd_start;
+
+ /// Ceff Vdd Step
+ /// CeffVdd step value for each CeffVdd index (in percent)
+ uint8_t vdd_step;
+
+ /// Ceff Vdd Size
+ /// Number of CeffVdd indexes
+ uint8_t vdd_size;
+
+ /// Vratio Start
+ /// Vratio value represented by index 0 (in percent)
+ uint8_t vratio_start;
+
+ /// Vratio Step
+ /// Vratio step value for each CeffVdd index (in percent)
+ uint8_t vratio_step;
+
+ /// Vratio Size
+ /// Number of Vratio indexes
+ uint8_t vratio_size;
+
+ /// Fratio Start
+ /// Fratio value represented by index 0 (in percent)
+ uint8_t fratio_start;
+
+ /// Fratio Step
+ /// Fratio step value for each CeffVdd index (in percent)
+ uint8_t fratio_step;
+
+ /// Fratio Size
+ /// Number of Fratio indexes
+ uint8_t fratio_size;
+
+} WofTablesHeader_t;
+
+
// VDN
// Data is provided in 12ths (eg 12 core pairs on a 24 core chip)
#define VFRT_VRATIO_SIZE 12
-// 100%/10% steps + 1 (for 0)
-#define VFRT_FRATIO_SIZE 11
+// 100%/10% steps
+#define VFRT_FRATIO_SIZE 10
+
+// Holds a frequency that is 1000MHz + 16.667*VFRT_Circuit_t
+typedef uint8_t VFRT_Circuit_t;
+typedef Pstate VFRT_Hcode_t;
+
-typedef uint16_t VFRT_Circuit_t; // Holds a frequency in MHz
-typedef Pstate VFRT_Hcode_t;
extern VFRT_Circuit_t VFRTCircuitTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
@@ -277,5 +402,5 @@ extern VFRT_Hcode_t VFRTInputTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE];
#ifdef __cplusplus
} // end extern C
#endif
-
+#endif /* __ASSEMBLER__ */
#endif /* __P9_PSTATES_COMMON_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
index ca3a260b0..67be858be 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -36,11 +36,22 @@
#define __P9_PSTATES_OCC_H__
#include <p9_pstates_common.h>
+#include <p9_pstates_pgpe.h>
+#ifndef __ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
+/// PstateParmsBlock Magic Number
+///
+/// This magic number identifies a particular version of the
+/// PstateParmsBlock and its substructures. The version number should be
+/// kept up to date as changes are made to the layout or contents of the
+/// structure.
+
+#define OCC_PARMSBLOCK_MAGIC 0x4f43435050423030ull /* OCCPPB00 */
+
/// IDDQ Reading Type
/// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a
/// maximum value of 409.6A to be represented.
@@ -51,7 +62,7 @@ typedef uint16_t iddq_entry_t;
/// Each entry is 1 byte. The values are in 0.5degC units; this allow for a
/// maximum value of 127degC to be represented.
///
-typedef uint16_t avgtemp_entry_t;
+typedef uint8_t avgtemp_entry_t;
/// Iddq Table
///
@@ -76,10 +87,10 @@ typedef struct
uint8_t good_caches_per_sort;
/// Good Normal Cores
- uint8_t good_normal_cores[MAX_QUADS];
+ uint8_t good_normal_cores[MAXIMUM_QUADS];
/// Good Caches
- uint8_t good_caches[MAX_QUADS];
+ uint8_t good_caches[MAXIMUM_QUADS];
/// RDP to TDP Scaling Factor in 0.01% units
uint16_t rdp_to_tdp_scale_factor;
@@ -103,10 +114,10 @@ typedef struct
iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS];
/// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units
- iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+ iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
- /// IVDDN ; 6.25mA units
- iddq_entry_t ivdn;
+ /// IVDDN 6.25mA units
+ iddq_entry_t ivdn[IDDQ_MEASUREMENTS];
/// IVDD ALL Good Cores ON, Caches ON; 6.25mA units
@@ -119,11 +130,14 @@ typedef struct
avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS];
/// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units
- avgtemp_entry_t avgtemp_quad_good_cores_on[MAX_QUADS][IDDQ_MEASUREMENTS];
+ avgtemp_entry_t avgtemp_quad_good_cores_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS];
/// avgtempN ; 6.25mA units
avgtemp_entry_t avgtemp_vdn;
+ /// spare (per MVPD documentation
+ uint8_t spare_1[43];
+
} IddqTable;
@@ -132,6 +146,9 @@ typedef struct
/// comsumption by the OCC firmware. This data will reside in the Quad
/// Power Management Region (QPMR).
///
+/// This structure is aligned to 128B to allow for easy downloading using the
+/// OCC block copy engine
+///
typedef struct
{
@@ -168,11 +185,10 @@ typedef struct
// Minimum Pstate; Maximum is always 0.
uint32_t pstate_min; // Comes from PowerSave #V point after biases
-} OCCPstateParmBlock;
-
+} __attribute__((aligned(128))) OCCPstateParmBlock;
#ifdef __cplusplus
} // end extern C
#endif
-
+#endif /* __ASSEMBLER__ */
#endif /* __P9_PSTATES_OCC_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
index fd4ce8da0..7106bf9d0 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h
@@ -47,6 +47,7 @@
#define PSTATE_PARMSBLOCK_MAGIC 0x5053544154453030ull /* PSTATE00 */
+#ifndef __ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
@@ -117,8 +118,6 @@ typedef struct
/// UltraTurbo Segment VIDs by Core Count
VIDModificationTable ut_vid_mod;
- uint8_t pad[4];
-
} WOFElements;
@@ -218,28 +217,28 @@ typedef struct
/// Resonant Clock Grid Management Setup
ResonantClockingSetup resclk;
- //Time b/w ext VRM detects write voltage cmd and when voltage begins to move
+ /// Time b/w ext VRM detects write voltage cmd and when voltage begins to move
uint32_t ext_vrm_transition_start_ns;
- //Transition rate for an increasing VDD voltage excursion
+ /// Transition rate for an increasing VDD voltage excursion
uint32_t ext_vrm_transition_rate_inc_uv_per_us;
- //Transition rate for an decreasing VDD voltage excursion
+ /// Transition rate for an decreasing VDD voltage excursion
uint32_t ext_vrm_transition_rate_dec_uv_per_us;
- //Delay to account for VDD rail setting
+ /// Delay to account for VDD rail setting
uint32_t ext_vrm_stabilization_time_us;
- //External VRM transition step size
+ /// External VRM transition step size
uint32_t ext_vrm_step_size_mv;
- //Nest frequency in Mhz. This is used by FIT interrupt
+ /// Nest frequency in Mhz. This is used by FIT interrupt
uint32_t nest_frequency_mhz;
- //Precalculated Pstate-Voltage Slopes
+ /// Precalculated Pstate-Voltage Slopes
uint16_t PsVSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
- //Precalculated Voltage-Pstates Slopes
+ /// Precalculated Voltage-Pstates Slopes
uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION];
@@ -251,5 +250,5 @@ typedef struct
#ifdef __cplusplus
} // end extern C
#endif
-
+#endif /* __ASSEMBLER__ */
#endif /* __P9_PSTATES_PGPE_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
index e286f0991..ede135996 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -49,6 +49,7 @@
#define MAX_PSTATE_TABLE_ENTRIES 128
#define GEN_PSTATES_TBL_MAGIC 0x50535441424c3030 //PSTABL00 (last two ASCII characters indicate version number)
+#ifndef __ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
@@ -137,5 +138,5 @@ typedef struct
#ifdef __cplusplus
} // end extern C
#endif
-
+#endif /* __ASSEMBLER__ */
#endif /* __P9_PSTATES_TABLE_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 4a7c66acb..437ae96c5 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -40,6 +40,7 @@
#include <p9_hcode_image_build.H>
#include "p9_xip_image.h"
#include "p9_hcode_image_defines.H"
+#include "p9_pm_hcd_flags.h"
#include "p9_stop_util.H"
#include "p9_scan_ring_util.H"
#include "p9_tor.H"
@@ -50,6 +51,7 @@
#include <p9_ringId.H>
#include <p9_quad_scom_addresses.H>
#include <p9_fbc_utils.H>
+#include "p9_pstate_parameter_block.H"
#ifdef __CRONUS_VER
#include <string>
@@ -230,7 +232,7 @@ extern "C"
iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE)] = CME_SRAM_SIZE;
- //iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPPMR)] = HALF_KB;
+ iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR)] = HALF_KB;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL)] = PGPE_LVL_1_BOOT_LOAD_SIZE ;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL)] = PGPE_LVL_2_BOOT_LOAD_SIZE ;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE)] = PGPE_MAX_AREA_SIZE;
@@ -302,6 +304,15 @@ extern "C"
std::map<uint32_t, ExpairId> iv_idMap;
};
+#define ALIGN_DBWORD( OUTSIZE, INSIZE ) \
+ { \
+ OUTSIZE = INSIZE; \
+ if( 0 != (INSIZE/8) ) \
+ { \
+ OUTSIZE = ((( INSIZE + 7 )/ 8) << 3 ); \
+ } \
+ }
+
/**
* @brief constructor
*/
@@ -321,7 +332,7 @@ extern "C"
}
}
- //-------------------------------------------------------------------------
+//-------------------------------------------------------------------------
/**
* @brief returns ex chiplet ID associated with a scan ring and EQ id.
@@ -374,7 +385,7 @@ extern "C"
return exChipletId;
}
- //-------------------------------------------------------------------------------------------------
+//-------------------------------------------------------------------------
uint32_t validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize )
{
@@ -386,6 +397,7 @@ extern "C"
ImgSizeBank sizebank;
sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT];
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
+ PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader;
//FIXME size will change once SCOM and 24x7 are handled
o_sramImgSize = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset);
@@ -411,6 +423,16 @@ extern "C"
rc = CME_SRAM_IMG_SIZE_ERR;
break;
}
+
+ o_sramImgSize = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size);
+ rc = sizebank.isSizeGood( PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, o_sramImgSize );
+ FAPI_DBG("PGPE SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" );
+
+ if( rc )
+ {
+ rc = PGPE_SRAM_IMG_SIZE_ERR;
+ break;
+ }
}
while(0);
@@ -419,13 +441,13 @@ extern "C"
return rc;
}
- //-------------------------------------------------------------------------
+//-------------------------------------------------------------------------
/**
* @brief validates arguments passed for hcode image build
* @param refer to p9_hcode_image_build arguments
* @return fapi2 return code
- */
+ */
fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut,
SysPhase_t i_phase, ImageType_t i_imgType,
void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2,
@@ -489,7 +511,7 @@ extern "C"
return fapi2::current_err;
}
- //------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
/**
* @brief Copies section of hardware image to HOMER
* @param i_destPtr a location in HOMER
@@ -557,10 +579,12 @@ extern "C"
uint8_t attrVal = 0;
uint32_t cmeFlag = 0;
uint32_t sgpeFlag = 0;
+ pgpe_flags_t pgpeFlags;
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT];
+ PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR];
//Handling flags common to CME and SGPE
@@ -617,13 +641,31 @@ extern "C"
FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" );
- //Updating flag field in CME/SGPE Image header
+ // Set PGPE Header Flags from Attributes
+ FAPI_DBG(" -------------------- PGPE Flags -----------------");
+ pgpeFlags.value = 0;
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE,
+ FAPI_SYSTEM,
+ attrVal),
+ "Error from FAPI_ATTR_GET for attribute ATTR_PGPE_HCODE_FUNCTION_ENABLE");
+
+ // If 0 (Hcode disabled), then set the occ_opc_immed_response flag bit
+ if( !attrVal )
+ {
+ pgpeFlags.fields.occ_ipc_immed_response = 1;
+ }
+
+ FAPI_DBG("PGPE Hcode Mode : %s", attrVal ? "PSTATES Enabled" : "OCC IPC Immediate Response Mode" );
+
+ // Updating flag fields in the headers
pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag);
pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag);
+ pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlags.value);
FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags));
FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags));
- FAPI_DBG(" ==================== CME/SGPE Flags Ends =================");
+ FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags));
+ FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------==");
fapi_try_exit:
return fapi2::current_err;
@@ -645,7 +687,7 @@ extern "C"
pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CPMR_CME_HCODE_OFFSET >> CME_BLK_SIZE_SHIFT));
pCpmrHdr->cmePstateOffset = CPMR_CME_HCODE_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset);
pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset);
- pCpmrHdr->cmePstateLength = 0;
+ pCpmrHdr->cmePstateLength = pCmeHdr->g_cme_pstate_region_length;
pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled
pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_START);
pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RES_SIZE);
@@ -670,7 +712,6 @@ extern "C"
//Updating CME Image header
pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER);
-
pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) +
SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) +
SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length);
@@ -682,32 +723,38 @@ extern "C"
pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_PER_CME);
FAPI_INF("========================= CME Header Start ==================================");
- FAPI_INF(" Magic Num = 0x%16lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_magic_number));
- FAPI_INF(" HC Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset));
- FAPI_INF(" HC Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length));
- FAPI_INF(" PS Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset));
- FAPI_INF(" PS Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length));
- FAPI_INF(" CR Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset));
- FAPI_INF(" CR Ovrd Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset ));
- FAPI_INF(" CR Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length));
- FAPI_INF(" CSR Offset = 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset));
- FAPI_INF(" CSR Length = 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) );
- FAPI_INF(" SCOM Offset = 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset));
- FAPI_INF(" SCOM Area Len = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length));
- FAPI_INF(" CPMR Phy Add = 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr));
+ char magicWord[16] = {0};
+ uint64_t temp = pCmeHdr->g_cme_magic_number;
+ memcpy(magicWord, &temp, sizeof(uint64_t));
+ FAPI_DBG(" Magic Num : %s", magicWord);
+ FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset));
+ FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length));
+ FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset));
+ FAPI_INF(" PS Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length));
+ FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset));
+ FAPI_INF(" CR Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset ));
+ FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length));
+ FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset));
+ FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) );
+ FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset));
+ FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length));
+ FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr));
FAPI_INF("========================= CME Header End ==================================");
FAPI_INF("==========================CPMR Header===========================================");
- FAPI_INF(" CME HC Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
- FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));
- FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset));
- FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength));
- FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset));
- FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength));
- FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset));
- FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength));
- FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset));
- FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength ));
+ temp = pCpmrHdr->magic_number;
+ memcpy(magicWord, &temp, sizeof(uint64_t));
+ FAPI_DBG(" Magic Num : %s", magicWord);
+ FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
+ FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));
+ FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset));
+ FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength));
+ FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset));
+ FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength));
+ FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset));
+ FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength));
+ FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset));
+ FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength ));
FAPI_INF("==================================CPMR Ends=====================================");
}
@@ -750,40 +797,51 @@ extern "C"
{
uint32_t rc = IMG_BUILD_SUCCESS;
+
QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader);
sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT];
memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) );
+ //FIXME Populating headers fields with max possible values for now. This is to keep things in line with SGPE
+ //bootloader design. SGPE bootloader doesn't expect a hole in image layout how ever due to current design of
+ //hcode image build there are holes between various section of image say common and instance ring.
pQpmrHdr->magic_number = SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER);
pSgpeHdr->g_sgpe_magic_number = SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER);
FAPI_INF("==============================QPMR==================================");
- FAPI_INF(" Magic Num : 0x%16lX", SWIZZLE_8_BYTE(pQpmrHdr->magic_number));
- FAPI_INF(" Build Date : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildDate));
- FAPI_INF(" Version : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildVersion));
- FAPI_INF(" BC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset));
- FAPI_INF(" BL Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderOffset));
- FAPI_INF(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength));
- FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset));
- FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength));
+ char magicWord[16] = {0};
+ uint64_t temp = pQpmrHdr->magic_number;
+ memcpy(magicWord, &temp, sizeof(uint64_t));
+ FAPI_DBG(" Magic Num : %s", magicWord);
+ FAPI_DBG(" Build Date : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildDate));
+ FAPI_DBG(" Version : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildVersion));
+ FAPI_DBG(" BC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset));
+ FAPI_DBG(" BL Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderOffset));
+ FAPI_DBG(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength));
+ FAPI_DBG(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset));
+ FAPI_DBG(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength));
FAPI_DBG(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) );
FAPI_DBG(" Cmn Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) );
FAPI_DBG(" Cmn Ring Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdOffset) );
FAPI_DBG(" Cmn Ring Ovrd Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdLength) );
FAPI_DBG(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) );
FAPI_DBG(" Quad Spec Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) );
- FAPI_INF("==============================QPMR Ends==============================");
- FAPI_INF("===========================SGPE Image Hdr=============================");
- FAPI_INF(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset ));
- FAPI_INF(" Override Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset ));
- FAPI_INF(" Flags : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags ));
- FAPI_INF(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset ));
- FAPI_INF(" Quad SCOM SRAM Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset));
- FAPI_INF(" Quad SCOM Mem Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset));
- FAPI_INF(" Quad SCOM Mem Length : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length ));
- FAPI_INF(" 24x7 Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset ));
- FAPI_INF(" 24x7 Length : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_length ));
- FAPI_INF("========================SGPE Image Hdr Ends===========================");
+ FAPI_DBG("==============================QPMR Ends==============================");
+
+ FAPI_DBG("===========================SGPE Image Hdr=============================");
+ temp = pSgpeHdr->g_sgpe_magic_number;
+ memcpy(magicWord, &temp, sizeof(uint64_t));
+ FAPI_DBG(" Magic Num : %s", magicWord);
+ FAPI_DBG(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset ));
+ FAPI_DBG(" Override Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset ));
+ FAPI_DBG(" Flags : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags ));
+ FAPI_DBG(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset ));
+ FAPI_DBG(" Quad SCOM SRAM Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset));
+ FAPI_DBG(" Quad SCOM Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset));
+ FAPI_DBG(" Quad SCOM Mem Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length ));
+ FAPI_DBG(" 24x7 Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset ));
+ FAPI_DBG(" 24x7 Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_length ));
+ FAPI_DBG("========================SGPE Image Hdr Ends===========================");
return rc;
}
@@ -1145,11 +1203,12 @@ extern "C"
* @brief copies PGPE section from hardware image to HOMER.
* @param[in] i_pImageIn points to start of hardware image.
* @param[in] i_pChipHomer points to HOMER image in main memory.
+ * @param[io] io_ppmrHdr an instance of PpmrHeader_t
* @param[in] i_imgType image sections to be built
* @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise.
*/
uint32_t buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer,
- ImageType_t i_imgType )
+ PpmrHeader_t& io_ppmrHdr, ImageType_t i_imgType )
{
uint32_t retCode = IMG_BUILD_SUCCESS;
FAPI_INF("> PGPE Img build")
@@ -1161,6 +1220,11 @@ extern "C"
P9XipSection ppeSection;
uint8_t* pPgpeImg = NULL;
+ //Init PGPE region with zero
+ memset( i_pChipHomer->ppmrRegion.ppmrHeader, 0x00, ONE_MB );
+
+ PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader;
+
if(!i_imgType.pgpeImageBuild )
{
break;
@@ -1176,9 +1240,29 @@ extern "C"
}
pPgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn );
+ FAPI_DBG("HW image PGPE Offset = 0x%08X", ppeSection.iv_offset);
- rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader, pPgpeImg,
- P9_XIP_SECTION_PGPE_LVL1_BL, PLAT_SGPE, ppeSection );
+ FAPI_INF("PPMR Header");
+ rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.ppmrHeader,
+ pPgpeImg,
+ P9_XIP_SECTION_PGPE_PPMR,
+ PLAT_PGPE,
+ ppeSection );
+
+ if( rcTemp )
+ {
+ FAPI_ERR("Failed to copy PPMR Header");
+ retCode = BUILD_FAIL_PGPE_PPMR;
+ break;
+ }
+
+ memcpy( &io_ppmrHdr, pPpmrHdr, sizeof(PpmrHeader_t));
+
+ rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader,
+ pPgpeImg,
+ P9_XIP_SECTION_PGPE_LVL1_BL,
+ PLAT_PGPE,
+ ppeSection );
if( rcTemp )
{
@@ -1187,9 +1271,14 @@ extern "C"
break;
}
+ io_ppmrHdr.g_ppmr_bc_offset = PPMR_HEADER_LEN;
+
- rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l2BootLoader, pPgpeImg,
- P9_XIP_SECTION_PGPE_LVL2_BL, PLAT_PGPE, ppeSection );
+ rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l2BootLoader,
+ pPgpeImg,
+ P9_XIP_SECTION_PGPE_LVL2_BL,
+ PLAT_PGPE,
+ ppeSection );
if( rcTemp )
{
@@ -1198,8 +1287,14 @@ extern "C"
break;
}
- rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.pgpeBin.hcode, pPgpeImg,
- P9_XIP_SECTION_PGPE_HCODE, PLAT_PGPE, ppeSection );
+ io_ppmrHdr.g_ppmr_bl_offset = io_ppmrHdr.g_ppmr_bc_offset + PGPE_LVL_1_BOOT_LOAD_SIZE;
+ io_ppmrHdr.g_ppmr_bl_length = ppeSection.iv_size;
+
+ rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.pgpeSramImage,
+ pPgpeImg,
+ P9_XIP_SECTION_PGPE_HCODE,
+ PLAT_PGPE,
+ ppeSection );
if( rcTemp )
{
@@ -1208,8 +1303,15 @@ extern "C"
break;
}
- //FIXME PGPE image header shall be populated after its definition is published.
+ io_ppmrHdr.g_ppmr_hcode_offset = io_ppmrHdr.g_ppmr_bl_offset + PGPE_LVL_2_BOOT_LOAD_SIZE;
+ io_ppmrHdr.g_ppmr_hcode_length = ppeSection.iv_size;
+ //Finally let us take care of endianess
+ io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset);
+ io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset);
+ io_ppmrHdr.g_ppmr_bl_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_length);
+ io_ppmrHdr.g_ppmr_hcode_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset);
+ io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length);
}
while(0);
@@ -1263,14 +1365,14 @@ extern "C"
break;
}
- FAPI_DBG("================== Input Buffer Specs ====================");
+ FAPI_DBG("------------------ Input Buffer Specs --------------------");
FAPI_DBG("Ring section (buf,size)=(0x%016llX,0x%08X)",
(uintptr_t)(i_ringData.iv_pRingBuffer), i_ringData.iv_ringBufSize);
FAPI_DBG("Work buf1 (buf,size)=(0x%016llX,0x%08X)",
(uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1);
FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)",
(uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2);
- FAPI_DBG("================== Buffer Specs Ends ====================");
+ FAPI_DBG("---------------=== Buffer Specs Ends --------------------");
uint32_t l_bootMask = ENABLE_ALL_CORE;
fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS;
@@ -1377,6 +1479,7 @@ extern "C"
ALIGN_DWORD(tempRingLength, tempBufSize)
ALIGN_RING_LOC( pOverrideStart, pOvrdRingPayload );
+
memcpy( pOvrdRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize);
*(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOvrdRingPayload - pOverrideStart) + ringStartToHdrOffset);
@@ -1405,29 +1508,321 @@ extern "C"
}
while(0);
- sgpeOvrdRings.dumpOverrideRings();
-
- FAPI_DBG("====================SGPE Override Rings================" );
- FAPI_DBG("====================SGPE Header ========================");
+ FAPI_DBG("--------------------SGPE Override Rings---------------=" );
+ FAPI_DBG("--------------------SGPE Header --------------------====");
FAPI_DBG("Override Ring Offset 0x%08X", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset));
+ sgpeOvrdRings.dumpOverrideRings();
+
FAPI_INF("< layoutSgpeScanOverride")
return rc;
}
-//------------------------------------------------------------------------------
+ /**
+ * @brief update fields of PGPE image header region with parameter block info.
+ * @param i_pHomer points to start of chip's HOMER.
+ */
+
+
+ void updatePgpeHeader( void* const i_pHomer )
+ {
+ FAPI_DBG("> updatePgpeHeader");
+ Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer;
+ PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)&pHomerLayout->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR];
+ PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) pHomerLayout->ppmrRegion.ppmrHeader;
+ //Updating PGPE Image Header
+ //Global P-State Parameter Block SRAM address
+ pPgpeHdr->g_pgpe_gppb_sram_addr = 0; // set by PGPE Hcode
+
+ //PGPE Hcode length
+ pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length);
+
+ //Global P-State Parameter Block HOMER address
+ pPgpeHdr->g_pgpe_gppb_mem_offset = (OCI_PBA_ADDR_BASE |
+ (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset) +
+ PPMR_OFFSET ));
+ //Global P-State Parameter Block length
+ pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length);
+
+ //P-State Parameter Block HOMER offset
+ pPgpeHdr->g_pgpe_gen_pstables_mem_offset = (OCI_PBA_ADDR_BASE |
+ (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset) +
+ PPMR_OFFSET ));
+
+ //P-State Table length
+ pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length);
+
+ //OCC P-State Table SRAM address
+ pPgpeHdr->g_pgpe_occ_pstables_sram_addr = 0;
+
+ //OCC P-State Table Length
+ pPgpeHdr->g_pgpe_occ_pstables_len = 0;
+
+ //PGPE Beacon SRAM address
+ pPgpeHdr->g_pgpe_beacon_addr = 0;
+ pPgpeHdr->g_quad_status_addr = 0;
+ pPgpeHdr->g_wof_table_addr = 0;
+ pPgpeHdr->g_wof_table_length = 0;
+
+ //Finally handling the endianess
+ pPgpeHdr->g_pgpe_magic_number = SWIZZLE_8_BYTE(PGPE_MAGIC_NUMBER);
+ pPgpeHdr->g_pgpe_gppb_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr);
+ pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_hcode_length);
+ pPgpeHdr->g_pgpe_gppb_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset);
+ pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length);
+ pPgpeHdr->g_pgpe_gen_pstables_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset);
+ pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length);
+ pPgpeHdr->g_pgpe_occ_pstables_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr);
+ pPgpeHdr->g_pgpe_occ_pstables_len = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len);
+ pPgpeHdr->g_pgpe_beacon_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr);
+ pPgpeHdr->g_quad_status_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr);
+ pPgpeHdr->g_wof_table_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr);
+ pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length);
+
+ FAPI_DBG("================================PGPE Image Header==========================================")
+ char magicWord[16] = {0};
+ uint64_t temp = pPgpeHdr->g_pgpe_magic_number;
+ memcpy(magicWord, &temp, sizeof(uint64_t));
+ FAPI_DBG("PGPE Magic Word : %s", magicWord);
+ FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length));
+ FAPI_DBG("GPPB SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr));
+ FAPI_DBG("GPPB Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset));
+ FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length));
+ FAPI_DBG("PS Table Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset));
+ FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length));
+ FAPI_DBG("OCC PST SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr));
+ FAPI_DBG("OCC PST Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len));
+ FAPI_DBG("Beacon Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr));
+ FAPI_DBG("Quad Status : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr));
+ FAPI_DBG("WOF Addr : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr));
+ FAPI_DBG("WOF Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length));
+ FAPI_DBG("==============================PGPE Image Header End========================================")
+
+ FAPI_DBG("< updatePgpeHeader");
+ }
+
+//---------------------------------------------------------------------------
+
+ void updatePpmrHeader( void* const i_pHomer, PpmrHeader_t& io_ppmrHdr )
+ {
+ FAPI_DBG("> updatePpmrHeader");
+ Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer;
+ PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) &pHomerLayout->ppmrRegion.ppmrHeader;
+ memcpy( pPpmrHdr, &io_ppmrHdr, sizeof(PpmrHeader_t) );
+
+ FAPI_DBG("=========================== PPMR Header ====================================" );
+ char magicWord[16] = {0};
+ uint64_t temp = io_ppmrHdr.g_ppmr_magic_number;
+ memcpy(magicWord, &temp, sizeof(uint64_t));
+ FAPI_DBG("Magic Word : %s", magicWord);
+ FAPI_DBG("BC Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset));
+ FAPI_DBG("BL Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_offset));
+ FAPI_DBG("BL Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_length));
+ FAPI_DBG("Hcode Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_offset));
+ FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length));
+ FAPI_DBG("GPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset));
+ FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length));
+ FAPI_DBG("LPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_offset));
+ FAPI_DBG("LPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_length));
+ FAPI_DBG("OPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_offset));
+ FAPI_DBG("OPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_length));
+ FAPI_DBG("PS Table Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset));
+ FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length));
+ FAPI_DBG("PSGPE SRAM Size : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size));
+ FAPI_DBG("=========================== PPMR Header ends ==================================" );
+
+ updatePgpeHeader( i_pHomer );
+
+ FAPI_DBG("< updatePpmrHeader");
+ }
+
+//---------------------------------------------------------------------------
/**
- * @brief creates a lean scan ring layout for core specific rings in HOMER.
- * @param i_pHOMER points to HOMER image.
- * @param i_chipState functional state of all cores within P9 chip
- * @param i_ringData scan ring related data
- * @param i_debugMode debug type set for scan rings
- * @param i_ringVariant scan ring flavor
- * @param i_imgType image type to be built
- * @param io_cmeRings instance of RingBucket
- * @param io_cmnRingSize input: CME region length populated. output: CME region length after copying cmn ring.
- * @param IMG_BUILD_SUCCESS if function succeeds else error code.
+ * @brief updates the PState parameter block info in CPMR and PPMR region.
+ * @param i_pHomer points to start of of chip's HOMER.
+ * @param i_procTgt fapi2 target associated with P9 chip.
+ * @param i_imgType image type to be built.
+ * return fapi2::Returncode
+ */
+ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i_procTgt,
+ PpmrHeader_t& io_ppmrHdr,
+ ImageType_t i_imgType )
+ {
+ FAPI_INF("buildParameterBlock entered");
+
+ do
+ {
+ if( !i_imgType.pgpePstateParmBlockBuild )
+ {
+ break;
+ }
+
+ fapi2::ReturnCode retCode;
+ Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer;
+ PPMRLayout_t* pPpmr = (PPMRLayout_t*) &pHomerLayout->ppmrRegion;
+ cmeHeader_t* pCmeHdr = (cmeHeader_t*) &pHomerLayout->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
+
+ uint32_t ppmrRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset) +
+ SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length);
+
+ FAPI_DBG("Hcode ppmrRunningOffset 0x%08x", ppmrRunningOffset );
+
+ uint32_t pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length);
+
+ FAPI_DBG(" PGPE Hcode End 0x%08x", pgpeRunningOffset );
+
+ uint32_t sizeAligned = 0;
+ uint32_t sizePStateBlock = 0;
+ PstateSuperStructure pStateSupStruct;
+
+ //Building P-State Parameter block info by calling a HWP
+ FAPI_DBG("Generating P-State Parameter Block" );
+ FAPI_EXEC_HWP(retCode, p9_pstate_parameter_block, i_procTgt, &pStateSupStruct);
+ FAPI_TRY(retCode);
+
+ //-------------------------- Local P-State Parameter Block ------------------------------
+
+ uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length);
+ uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex];
+
+ sizePStateBlock = sizeof(LocalPstateParmBlock);
+
+ FAPI_DBG("Copying Local P-State Parameter Block into CPMR" );
+ memcpy( pLocalPState, &pStateSupStruct.localppb, sizePStateBlock );
+
+ ALIGN_DBWORD( sizeAligned, sizePStateBlock )
+ uint32_t localPStateBlock = sizeAligned;
+ FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned );
+
+ pCmeHdr->g_cme_pstate_region_length = localPStateBlock;
+ pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + localPStateBlock;
+
+ //-------------------------- Local P-State Parameter Block Ends --------------------------
+
+ //-------------------------- Global P-State Parameter Block ------------------------------
+
+ FAPI_DBG("Copying Global P-State Parameter Block" );
+ sizePStateBlock = sizeof(GlobalPstateParmBlock);
+
+ // MAKE ASSERT
+ if (sizePStateBlock > PSTATE_OUTPUT_TABLE_SIZE)
+ {
+ FAPI_ERR("GlobalPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)",
+ sizePStateBlock, sizePStateBlock,
+ PSTATE_OUTPUT_TABLE_SIZE, PSTATE_OUTPUT_TABLE_SIZE);
+ }
+
+ FAPI_DBG("GPPBB pgpeRunningOffset 0x%08x", pgpeRunningOffset );
+ memcpy( &pPpmr->pgpeSramImage[pgpeRunningOffset], &pStateSupStruct.globalppb, sizePStateBlock );
+
+ ALIGN_DBWORD( sizeAligned, sizePStateBlock )
+ FAPI_DBG("GPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned );
+
+ //Updating PPMR header info with GPSPB offset and length
+ io_ppmrHdr.g_ppmr_gppb_offset = ppmrRunningOffset;
+ io_ppmrHdr.g_ppmr_gppb_length = sizeAligned;
+
+ ppmrRunningOffset += sizeAligned;
+ pgpeRunningOffset += sizeAligned;
+ FAPI_DBG("OPPB pgpeRunningOffset 0x%08x OPPB ppmrRunningOffset 0x%08x",
+ pgpeRunningOffset, ppmrRunningOffset );
+
+ //------------------------------ Global P-State Parameter Block Ends ----------------------
+
+ //------------------------------ OCC P-State Parameter Block ------------------------------
+
+ FAPI_INF("Copying OCC P-State Parameter Block" );
+ sizePStateBlock = sizeof(OCCPstateParmBlock);
+ ALIGN_DBWORD( sizeAligned, sizePStateBlock )
+
+ FAPI_DBG("OPPB size 0x%08x (%d)", sizeAligned, sizeAligned );
+ FAPI_DBG("OPSPB Actual size = 0x%08x (%d); After Alignment = 0x%08x (%d)",
+ sizePStateBlock, sizePStateBlock,
+ sizeAligned, sizeAligned );
+
+ // MAKE ASSERT
+ if (sizePStateBlock > OCC_PARAM_BLOCK_SIZE)
+ {
+ FAPI_ERR("OCCPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)",
+ sizePStateBlock, sizePStateBlock,
+ OCC_PARAM_BLOCK_SIZE, OCC_PARAM_BLOCK_SIZE);
+ }
+
+ // The PPMR offset is from the begining --- which is the ppmrHeader
+ io_ppmrHdr.g_ppmr_oppb_offset = pPpmr->occParmBlock - pPpmr->ppmrHeader;
+ io_ppmrHdr.g_ppmr_oppb_length = sizeAligned;
+ FAPI_DBG("OPPB ppmrRunningOffset 0x%08x", io_ppmrHdr.g_ppmr_oppb_offset);
+
+ memcpy( &pPpmr->occParmBlock, &pStateSupStruct.occppb, sizePStateBlock );
+
+ //-------------------------- OCC P-State Parameter Block Ends ------------------------------
+
+
+
+ io_ppmrHdr.g_ppmr_lppb_offset = CPMR_OFFSET + CPMR_CME_HCODE_OFFSET + localPspbStartIndex;
+ io_ppmrHdr.g_ppmr_lppb_length =
+ localPStateBlock; //FIXME RTC 159737 Need to clarify it from booting perspective
+
+
+ //------------------------------ OCC P-State Table Allocation ------------------------------
+
+ // The PPMR offset is from the begining --- which is the ppmrHeader
+ io_ppmrHdr.g_ppmr_pstables_offset = pPpmr->pstateTable - pPpmr->ppmrHeader;;
+ io_ppmrHdr.g_ppmr_pstables_length = sizeof(GeneratedPstateInfo);
+
+ //------------------------------ OCC P-State Table Allocation Ends -------------------------
+
+
+ //------------------------------ Calculating total PGPE Image Size in SRAM ------------------------
+
+ io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length) +
+ io_ppmrHdr.g_ppmr_gppb_length;
+
+ FAPI_DBG("OPPB pgpeRunningOffset 0x%08x io_ppmrHdr.g_ppmr_pgpe_sram_img_size 0x%08x",
+ pgpeRunningOffset, io_ppmrHdr.g_ppmr_pgpe_sram_img_size );
+
+ //Finally let us handle endianess
+ //CME Header
+ pCmeHdr->g_cme_pstate_region_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length);
+ pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset);
+
+ //PPMR Header
+ io_ppmrHdr.g_ppmr_magic_number = SWIZZLE_8_BYTE(PPMR_MAGIC_NUMBER);
+ io_ppmrHdr.g_ppmr_gppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_offset);
+ io_ppmrHdr.g_ppmr_gppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_length);
+ io_ppmrHdr.g_ppmr_oppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_offset);
+ io_ppmrHdr.g_ppmr_oppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_length);
+ io_ppmrHdr.g_ppmr_lppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_offset);
+ io_ppmrHdr.g_ppmr_lppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_length);
+ io_ppmrHdr.g_ppmr_pstables_offset = SWIZZLE_4_BYTE( io_ppmrHdr.g_ppmr_pstables_offset);
+ io_ppmrHdr.g_ppmr_pstables_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pstables_length);
+ io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pgpe_sram_img_size);
+ }
+ while(0);
+
+ fapi_try_exit:
+ FAPI_INF("buildParameterBlock exit");
+
+ return fapi2::current_err;
+ }
+
+//---------------------------------------------------------------------------
+
+ /**
+ * @brief copies override flavor of scan rings
+ * @param i_pImageIn points to start of hardware image.
+ * @param i_pOverride points to override rings.
+ * @param o_pImageOut points to HOMER image.
+ * @param i_ddLevel dd level associated with P9 chip.
+ * @param i_pBuf1 work buffer1
+ * @param i_bufSize1 work buffer1 size.
+ * @param i_pBuf2 work buffer2
+ * @param i_bufSize2 work buffer2 size.
+ * @param i_imgType image type to be built.
+ * @param o_qpmr temp instance of QpmrHeaderLayout_t
+ * @param i_platId platform associated with scan ring.
+ * @return IMG_BUILD_SUCCESS if successful else error code.
*/
uint32_t layoutCmnRingsForCme( Homerlayout_t* i_pHomer,
const P9FuncModel& i_chipState,
@@ -1587,7 +1982,6 @@ extern "C"
}
ALIGN_DWORD(tempRepairLength, tempSize);
-
ringLength += tempSize;
}
@@ -2007,7 +2401,7 @@ extern "C"
return rc;
}
- //------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
/**
* @brief creates a scan ring layout for quad common rings in HOMER.
@@ -2111,7 +2505,7 @@ extern "C"
return rc;
}
- //------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
/**
* @brief creates a scan ring layout for quad common rings in HOMER.
@@ -2169,7 +2563,6 @@ extern "C"
io_qpmrHdr,
i_imgType );
-
//Manage the Quad specific rings in HOMER
layoutInstRingsForSgpe( i_pHomer,
i_chipState,
@@ -2219,7 +2612,7 @@ extern "C"
return rc;
}
- //---------------------------------------------------------------------------
+//---------------------------------------------------------------------------
/**
* @brief updates the IVPR attributes for SGPE, PGPE.
* @brief i_pChipHomer points to start of HOMER
@@ -2227,6 +2620,7 @@ extern "C"
fapi2::ReturnCode updateGpeAttributes( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt )
{
QpmrHeaderLayout_t* pQpmrHdr = (QpmrHeaderLayout_t*)i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader;
+ PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) i_pChipHomer->ppmrRegion.ppmrHeader;
uint32_t attrVal = SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset);
attrVal |= (0x80000000 | ONE_MB);
@@ -2238,19 +2632,21 @@ extern "C"
FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal );
- attrVal = (uint8_t*)(i_pChipHomer->ppmrRegion.l1BootLoader) - (uint8_t*)(i_pChipHomer);
- attrVal |= 0x80000000;
+ attrVal = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset);
+ attrVal |= (0x80000000 | PPMR_OFFSET);
+
FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET,
i_procTgt,
attrVal ),
"Error from FAPI_ATTR_SET for attribute ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET");
FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal );
+
fapi_try_exit:
return fapi2::current_err;
}
- //---------------------------------------------------------------------------
+//---------------------------------------------------------------------------
/**
* @brief Set the Fabric System, Group and Chip IDs into SGPE and CME headers
* @brief i_pChipHomer points to start of HOMER
@@ -2290,11 +2686,11 @@ extern "C"
FAPI_DBG("Fabric Chip ID : 0x%01X", l_chip_id);
// Create a unit16_t Location Ids in the form of:
- // 0:3 Group ID (loaded from ATTR_PROC_FABRIC_GROUP_ID)
- // 4:6 Chip ID (loaded from ATTR_PROC_FABRIC_CHIP_ID)
+ // 0:3 Â Group ID (loaded from ATTR_PROC_FABRIC_GROUP_ID)
+ // 4:6 ÂChip ID (loaded from ATTR_PROC_FABRIC_CHIP_ID)
// 7 0
- // 8:12 System ID (loaded from ATTR_PROC_FABRIC_SYSTEM_ID)
- // 13:15 00
+ // 8:12 ÂSystem ID (loaded from ATTR_PROC_FABRIC_SYSTEM_ID)
+ // 13:15 Â 00
l_location_id.insert < 0, 4, 8 - 4, uint8_t > ( l_group_id );
l_location_id.insert < 4, 3, 8 - 3, uint8_t > ( l_chip_id );
@@ -2395,7 +2791,7 @@ extern "C"
return fapi2::current_err;
}
- //--------------------------------------------------------------------------------------------
+//--------------------------------------------------------------------------------------------
/**
* @brief populate L2 Epsilon SCOM register.
@@ -2589,7 +2985,7 @@ extern "C"
return fapi2::current_err;
}
- //---------------------------------------------------------------------------
+//---------------------------------------------------------------------------
/**
* @brief populate L3 Epsilon SCOM register.
@@ -2793,7 +3189,7 @@ extern "C"
return fapi2::current_err;
}
- //---------------------------------------------------------------------------
+//---------------------------------------------------------------------------
fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt,
void* const i_pImageIn,
@@ -2892,16 +3288,24 @@ extern "C"
FAPI_INF("CME built");
FAPI_INF("PGPE building");
- //FIXME RTC 148009 PGPE Header needs to be defined.
- ppeImgRc = buildPgpeImage( i_pImageIn, pChipHomer, i_imgType );
+ PpmrHeader_t l_ppmrHdr;
+ ppeImgRc = buildPgpeImage( i_pImageIn, pChipHomer, l_ppmrHdr, i_imgType );
FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ),
fapi2::PGPE_BUILD_FAIL()
.set_PGPE_FAIL_SECTN( ppeImgRc ),
"Failed to copy PGPE section in HOMER" );
- FAPI_INF("PGPE built");
+ //Update P State parameter block info in HOMER
+ retCode = buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType );
+
+ if( retCode )
+ {
+ FAPI_ERR("Failed to add parameter block");
+ break;
+ }
+ FAPI_INF("PGPE built");
//Let us add Scan Rings to the image.
uint8_t l_ringDebug = 0;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE,
@@ -2984,6 +3388,9 @@ extern "C"
//Update QPMR Header area in HOMER
updateQpmrHeader( pChipHomer, l_qpmrHdr );
+ //update PPMR Header area in HOMER
+ updatePpmrHeader( pChipHomer, l_ppmrHdr );
+
//Update L2 Epsilon SCOM Registers
retCode = populateEpsilonL2ScomReg( pChipHomer );
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk
index 0c20ee602..a09663fee 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.mk
@@ -24,9 +24,9 @@
# IBM_PROLOG_END_TAG
PROCEDURE = p9_hcode_image_build
HCODE_UTIL=$(ROOTPATH)/chips/p9/procedures/utils/stopreg/
+HCODE_UTIL+=$(ROOTPATH)/chips/p9/procedures/hwp/customize/
HCODE_UTIL+=$(ROOTPATH)/chips/p9/xip/
HCODE_UTIL+=$(ROOTPATH)/chips/p9/procedures/hwp/lib/
-HCODE_UTIL+=$(ROOTPATH)/chips/p9/utils/imageProcs/
HCODE_UTIL+=$(ROOTPATH)/tools/imageProcs/
HCODE_UTIL+=$(ROOTPATH)/chips/p9/procedures/hwp/customize/
HCODE_UTIL+=$(ROOTPATH)/chips/p9/common/include/
@@ -35,6 +35,7 @@ HCODE_UTIL+=$(ROOTPATH)/chips/p9/procedures/hwp/nest
lib$(PROCEDURE)_DEPLIBS += p9_scan_ring_util
lib$(PROCEDURE)_DEPLIBS += p9_xip_image
+lib$(PROCEDURE)_DEPLIBS +=p9_pstate_parameter_block
lib$(PROCEDURE)_DEPLIBS += p9_tor
lib$(PROCEDURE)_DEPLIBS += p9_ringId
lib$(PROCEDURE)_DEPLIBS += p9_stop_util
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C
index e6d9aaaa3..2e12b1943 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C
@@ -59,14 +59,16 @@ fapi2::ReturnCode
p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
PstateSuperStructure* io_pss)
{
+ int rc;
+ FAPI_INF("> p9_pstate_parameter_block");
+
- FAPI_INF("Populating magic number in Pstate Parameter block structure");
// -----------------------------------------------------------
// Clear the PstateSuperStructure and install the magic number
// -----------------------------------------------------------
memset(io_pss, 0, sizeof(PstateSuperStructure));
-
+ FAPI_INF("Populating magic number in Pstate Parameter block structure");
(*io_pss).magic = revle64(PSTATE_PARMSBLOCK_MAGIC);
//Local variables for Global,local and OCC parameter blocks
@@ -97,7 +99,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
IddqTable l_iddqt;
// Frequency step variable
- uint32_t l_frequency_step_khz;
+ double l_frequency_step_khz;
//VDM Parm block
VDMParmBlock l_vdmpb;
@@ -152,19 +154,19 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
// System power distribution parameters
// -----------------------------------------------
// VDD rail
- l_vdd_sysparm.loadline_uohm = attr.attr_proc_r_loadline_vdd_uohm;
- l_vdd_sysparm.distloss_uohm = attr.attr_proc_r_distloss_vdd_uohm;
- l_vdd_sysparm.distoffset_uv = attr.attr_proc_vrm_voffset_vdd_uv;
+ l_vdd_sysparm.loadline_uohm = revle32(attr.attr_proc_r_loadline_vdd_uohm);
+ l_vdd_sysparm.distloss_uohm = revle32(attr.attr_proc_r_distloss_vdd_uohm);
+ l_vdd_sysparm.distoffset_uv = revle32(attr.attr_proc_vrm_voffset_vdd_uv);
// VCS rail
- l_vcs_sysparm.loadline_uohm = attr.attr_proc_r_loadline_vcs_uohm;
- l_vcs_sysparm.distloss_uohm = attr.attr_proc_r_distloss_vcs_uohm;
- l_vcs_sysparm.distoffset_uv = attr.attr_proc_vrm_voffset_vcs_uv;
+ l_vcs_sysparm.loadline_uohm = revle32(attr.attr_proc_r_loadline_vcs_uohm);
+ l_vcs_sysparm.distloss_uohm = revle32(attr.attr_proc_r_distloss_vcs_uohm);
+ l_vcs_sysparm.distoffset_uv = revle32(attr.attr_proc_vrm_voffset_vcs_uv);
// VDN rail
- l_vdn_sysparm.loadline_uohm = attr.attr_proc_r_loadline_vdn_uohm;
- l_vdn_sysparm.distloss_uohm = attr.attr_proc_r_distloss_vdn_uohm;
- l_vdn_sysparm.distoffset_uv = attr.attr_proc_vrm_voffset_vdn_uv;
+ l_vdn_sysparm.loadline_uohm = revle32(attr.attr_proc_r_loadline_vdn_uohm);
+ l_vdn_sysparm.distloss_uohm = revle32(attr.attr_proc_r_distloss_vdn_uohm);
+ l_vdn_sysparm.distoffset_uv = revle32(attr.attr_proc_vrm_voffset_vdn_uv);
// ----------------
// get IQ (IDDQ) data
@@ -204,8 +206,12 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
// Global parameter block
// -----------------------------------------------
+ // Needs to be Endianness corrected going into the block
+
l_globalppb.magic = revle64(PSTATE_PARMSBLOCK_MAGIC);
+ l_globalppb.options.options = 0; // until options get defined.
+
// Pstate Options @todo RTC 161279, Check what needs to be populated here
// @todo RTC 161279 - Corresponds to Pstate 0 . Setting to ULTRA TURBO frequency point. REVIEW with Greg
@@ -216,11 +222,21 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
// frequency_step_khz
l_frequency_step_khz = (attr.attr_freq_proc_refclock_khz / attr.attr_proc_dpll_divider);
- l_globalppb.frequency_step_khz = l_frequency_step_khz;
+ l_globalppb.frequency_step_khz = revle32(l_frequency_step_khz);
+ l_globalppb.nest_frequency_mhz = revle32(attr.attr_nest_frequency_mhz);
+
+ // External VRM parameters
+ l_globalppb.ext_vrm_transition_start_ns = revle32(attr.attr_ext_vrm_transition_start_ns);
+ l_globalppb.ext_vrm_transition_rate_inc_uv_per_us = revle32(attr.attr_ext_vrm_transition_rate_inc_uv_per_us);
+ l_globalppb.ext_vrm_transition_rate_dec_uv_per_us = revle32(attr.attr_ext_vrm_transition_rate_dec_uv_per_us);
+ l_globalppb.ext_vrm_stabilization_time_us = revle32(attr.attr_ext_vrm_stabilization_time_us);
+ l_globalppb.ext_vrm_step_size_mv = revle32(attr.attr_ext_vrm_step_size_mv);
// -----------------------------------------------
// populate VpdOperatingPoint with biased MVPD attributes
// -----------------------------------------------
+
+ FAPI_INF("Load VPD");
// VPD operating point
FAPI_TRY(load_mvpd_operating_point(attr_mvpd_voltage_control, l_globalppb.operating_points, l_frequency_step_khz),
"Loading MVPD operating point failed");
@@ -232,8 +248,8 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
l_globalppb.ext_biases[i] = l_vpdbias[i];
l_globalppb.int_biases[i] = l_vpdbias[i];
- l_localppb.ext_biases[i] = l_vpdbias[i];
- l_localppb.int_biases[i] = l_vpdbias[i];
+ l_localppb.ext_biases[i] = l_vpdbias[i];
+ l_localppb.int_biases[i] = l_vpdbias[i];
}
l_globalppb.vdd_sysparm = l_vdd_sysparm;
@@ -241,10 +257,20 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
l_globalppb.vdn_sysparm = l_vdn_sysparm;
// safe_voltage_mv
- l_globalppb.safe_voltage_mv = attr.attr_pm_safe_voltage_mv;
+ l_globalppb.safe_voltage_mv = revle32(attr.attr_pm_safe_voltage_mv);
// safe_frequency_khz
- l_globalppb.safe_frequency_khz = attr.attr_pm_safe_frequency_mhz / 1000;
+ l_globalppb.safe_frequency_khz = revle32(attr.attr_pm_safe_frequency_mhz / 1000);
+
+ // nest_frequency_khz
+ l_globalppb.nest_frequency_mhz = revle32(attr.attr_nest_freq_mhz);
+
+ // @todo RTC 161279
+ l_globalppb.ext_vrm_transition_start_ns = revle32(8000);
+ l_globalppb.ext_vrm_transition_rate_inc_uv_per_us = revle32(10);
+ l_globalppb.ext_vrm_transition_rate_dec_uv_per_us = revle32(10);
+ l_globalppb.ext_vrm_stabilization_time_us = revle32(5);
+ l_globalppb.ext_vrm_step_size_mv = revle32(50);
// vrm_stepdelay_range -@todo RTC 161279 potential attributes to be defined
@@ -271,7 +297,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
// -----------------------------------------------
// Local parameter block
// -----------------------------------------------
- l_localppb.magic = revle64(PSTATE_PARMSBLOCK_MAGIC);
+ l_localppb.magic = revle64(LOCAL_PARMSBLOCK_MAGIC);
// QuadManagerFlags
l_localppb.qmflags = l_qm_flags;
@@ -294,7 +320,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
// -----------------------------------------------
// OCC parameter block
// -----------------------------------------------
- l_occppb.magic = revle64(PSTATE_PARMSBLOCK_MAGIC);
+ l_occppb.magic = revle64(OCC_PARMSBLOCK_MAGIC);
// VPD operating point
FAPI_TRY(load_mvpd_operating_point(attr_mvpd_voltage_control, l_occppb.operating_points, l_frequency_step_khz),
@@ -302,6 +328,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
l_occppb.vdd_sysparm = l_vdd_sysparm;
l_occppb.vcs_sysparm = l_vcs_sysparm;
+ l_occppb.vdn_sysparm = l_vdn_sysparm;
// Iddq Table
l_occppb.iddq = l_iddqt;
@@ -311,19 +338,30 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
l_occppb.wof.tdp_rdp_factor = revle32(attr.attr_tdp_rdp_current_factor);
// frequency_min_khz - Value from Power save operating point after biases
- l_occppb.frequency_min_khz = (attr_mvpd_voltage_control[POWERSAVE][0] / 1000);
+ l_occppb.frequency_min_khz = revle32(attr_mvpd_voltage_control[POWERSAVE][0] * 1000);
// frequency_max_khz - Value from Ultra Turbo operating point after biases
- l_occppb.frequency_max_khz = (attr_mvpd_voltage_control[ULTRA][0] / 1000);
+ l_occppb.frequency_max_khz = revle32(attr_mvpd_voltage_control[ULTRA][0] * 1000);
// frequency_step_khz
- l_occppb.frequency_step_khz = l_frequency_step_khz;
+ l_occppb.frequency_step_khz = revle32(l_frequency_step_khz);
// @todo RTC 161279 - Need Pstate 0 definition and freq2pstate function to be coded
- // pstate_min
+
+ Pstate pstate_min;
+ rc = freq2pState(&l_globalppb, revle32(l_occppb.frequency_min_khz), &pstate_min);
+
+ if (!rc)
+ {
+ FAPI_ERR("A Bad thing happened!");
+ }
+
+ l_occppb.pstate_min = pstate_min;
// pstate_max
+ oppb_print(&(l_occppb));
+
// -----------------------------------------------
// Populate Global,local and OCC parameter blocks into Pstate super structure
// -----------------------------------------------
@@ -333,6 +371,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_
fapi_try_exit:
+ FAPI_INF("< p9_pstate_parameter_block");
return fapi2::current_err;
}
// END OF PSTATE PARAMETER BLOCK function
@@ -375,13 +414,13 @@ proc_get_attributes ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_targe
FAPI_TRY(FAPI_ATTR_GET(fapi2::attr_name, target, io_attr->attr_assign),"Attribute read failed"); \
FAPI_INF("%-60s = 0x%08x %u", #attr_name, io_attr->attr_assign, io_attr->attr_assign);
-// Frequency Bias attributes
+ // Frequency Bias attributes
DATABLOCK_GET_ATTR(ATTR_FREQ_BIAS_ULTRATURBO, i_target, attr_freq_bias_ultraturbo);
DATABLOCK_GET_ATTR(ATTR_FREQ_BIAS_TURBO, i_target, attr_freq_bias_turbo);
DATABLOCK_GET_ATTR(ATTR_FREQ_BIAS_NOMINAL, i_target, attr_freq_bias_nominal);
DATABLOCK_GET_ATTR(ATTR_FREQ_BIAS_POWERSAVE, i_target, attr_freq_bias_powersave);
-// Voltage Bias attributes
+ // Voltage Bias attributes
DATABLOCK_GET_ATTR(ATTR_VOLTAGE_EXT_VDD_BIAS_ULTRATURBO, i_target, attr_voltage_ext_vdd_bias_ultraturbo);
DATABLOCK_GET_ATTR(ATTR_VOLTAGE_EXT_VDD_BIAS_TURBO, i_target, attr_voltage_ext_vdd_bias_turbo);
DATABLOCK_GET_ATTR(ATTR_VOLTAGE_EXT_VDD_BIAS_NOMINAL, i_target, attr_voltage_ext_vdd_bias_nominal);
@@ -394,16 +433,18 @@ proc_get_attributes ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_targe
DATABLOCK_GET_ATTR(ATTR_VOLTAGE_INT_VDD_BIAS_NOMINAL, i_target, attr_voltage_int_vdd_bias_nominal);
DATABLOCK_GET_ATTR(ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE, i_target, attr_voltage_int_vdd_bias_powersave);
-// Frequency attributes
+ // Frequency attributes
DATABLOCK_GET_ATTR(ATTR_FREQ_PROC_REFCLOCK_KHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
attr_freq_proc_refclock_khz);
+ DATABLOCK_GET_ATTR(ATTR_FREQ_PB_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ attr_nest_frequency_mhz);
DATABLOCK_GET_ATTR(ATTR_FREQ_CORE_CEILING_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), attr_freq_core_ceiling_mhz);
- DATABLOCK_GET_ATTR(ATTR_PM_SAFE_FREQUENCY_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), attr_pm_safe_frequency_mhz);
- DATABLOCK_GET_ATTR(ATTR_PM_SAFE_VOLTAGE_MV, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), attr_pm_safe_voltage_mv);
+ // @todo RTC 169768 Safe mode and use of boot mode
+// DATABLOCK_GET_ATTR(ATTR_PM_SAFE_FREQUENCY_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), attr_pm_safe_frequency_mhz);
+// DATABLOCK_GET_ATTR(ATTR_PM_SAFE_VOLTAGE_MV, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), attr_pm_safe_voltage_mv);
DATABLOCK_GET_ATTR(ATTR_FREQ_CORE_FLOOR_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), attr_freq_core_floor_mhz);
- DATABLOCK_GET_ATTR(ATTR_BOOT_FREQ_MHZ, i_target, attr_boot_freq_mhz);
-// Loadline, Distribution loss and Distribution offset attributes
+ // Loadline, Distribution loss and Distribution offset attributes
DATABLOCK_GET_ATTR(ATTR_PROC_R_LOADLINE_VDD_UOHM, i_target, attr_proc_r_loadline_vdd_uohm);
DATABLOCK_GET_ATTR(ATTR_PROC_R_DISTLOSS_VDD_UOHM, i_target, attr_proc_r_distloss_vdd_uohm);
DATABLOCK_GET_ATTR(ATTR_PROC_VRM_VOFFSET_VDD_UV, i_target, attr_proc_vrm_voffset_vdd_uv);
@@ -428,66 +469,18 @@ proc_get_attributes ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_targe
DATABLOCK_GET_ATTR(ATTR_TDP_RDP_CURRENT_FACTOR, i_target, attr_tdp_rdp_current_factor);
- // --------------------------------------------------------------
- // do basic attribute value checking and generate error if needed
- // --------------------------------------------------------------
-
-// @todo RTC 161279 - ssrivath Biasing checks either not required or need to be different in P9
-#if 0
-
- // ----------------------------------------------------
- // Check Valid Frequency and Voltage Biasing Attributes
- // - cannot have both up and down bias set
- // ----------------------------------------------------
- if (io_attr->attr_freq_ext_bias_up > 0 && io_attr->attr_freq_ext_bias_down > 0)
- {
- FAPI_ERR("**** ERROR : Frequency bias up and down both defined");
- FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PSTATE_DATABLOCK_FREQ_BIAS_ERROR);
- break;
- }
-
-#endif
+ // @todo RTC 169768 Safe mode and use of boot mode
- // ------------------------------------------------------
- // do attribute default value setting if the are set to 0 - REVIEW all defaults
- // ------------------------------------------------------
- if (io_attr->attr_freq_proc_refclock_khz == 0)
- {
- io_attr->attr_freq_proc_refclock_khz = 133;
- FAPI_INF("Attribute value was 0 - setting to default value ATTR_FREQ_PROC_REFCLOCK_KHZ = 133");
- }
-
- if (io_attr->attr_pm_safe_frequency_mhz == 0)
- {
- io_attr->attr_pm_safe_frequency_mhz = io_attr->attr_boot_freq_mhz;
- FAPI_INF("Attribute value was 0 - setting to default value ATTR_PM_SAFE_FREQUENCY_MHZ = ATTR_BOOT_FREQ_MHZ");
- }
-
- // @todo RTC 161279 - Loadline/Distloss defaults values need to be defined for P9
- if (io_attr->attr_proc_r_loadline_vdd_uohm == 0)
- {
- io_attr->attr_proc_r_loadline_vdd_uohm = 570;
- FAPI_INF("Attribute value was 0 - setting to default value ATTR_PROC_R_LOADLINE_VDD_UOHM = 570");
- }
-
- if (io_attr->attr_proc_r_loadline_vcs_uohm == 0)
- {
- io_attr->attr_proc_r_loadline_vcs_uohm = 570;
- FAPI_INF("Attribute value was 0 - setting to default value ATTR_PROC_R_LOADLINE_VCS_UOHM = 570");
- }
-
- if (io_attr->attr_proc_r_distloss_vdd_uohm == 0)
- {
- io_attr->attr_proc_r_distloss_vdd_uohm = 390;
- FAPI_INF("Attribute value was 0 - setting to default value ATTR_PROC_R_DISTLOSS_VDD_UOHM = 390");
- }
-
- if (io_attr->attr_proc_r_distloss_vcs_uohm == 0)
- {
- io_attr->attr_proc_r_distloss_vcs_uohm = 3500;
- FAPI_INF("Attribute value was 0 - setting to default value ATTR_PROC_R_DISTLOSS_VCS_UOHM = 3500");
- }
+ // Setting Safe Mode to the core floor frequency as this is the minimum
+ // allowed for this system.
+ io_attr->attr_pm_safe_frequency_mhz = io_attr->attr_freq_core_floor_mhz;
+ // Hardcode for now... @todo RTC 169800
+ io_attr->attr_ext_vrm_transition_start_ns = 8000;
+ io_attr->attr_ext_vrm_transition_rate_inc_uv_per_us = 10000; // 10mV/us
+ io_attr->attr_ext_vrm_transition_rate_dec_uv_per_us = 10000; // 10mV/us
+ io_attr->attr_ext_vrm_stabilization_time_us = 5;
+ io_attr->attr_ext_vrm_step_size_mv = 50;
fapi_try_exit:
return fapi2::current_err;
@@ -658,14 +651,17 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
IddqTable* io_iddqt)
{
- uint8_t* l_buffer_iq_c = reinterpret_cast<uint8_t*>(malloc(IQ_BUFFER_ALLOC));
- uint32_t l_record = 0;
- uint8_t* l_buffer_iq_inc;
- uint32_t l_bufferSize_iq = IQ_BUFFER_ALLOC;
- uint8_t i, j;
- uint8_t l_buffer_data;
- iddq_entry_t l_iddq_data;
+ uint8_t* l_buffer_iq_c = reinterpret_cast<uint8_t*>(malloc(IQ_BUFFER_ALLOC));
+ uint32_t l_record = 0;
+ uint8_t* l_buffer_iq_inc;
+ uint32_t l_bufferSize_iq = IQ_BUFFER_ALLOC;
+ uint8_t i, j;
+ uint8_t l_buffer_data;
+ iddq_entry_t l_iddq_data;
avgtemp_entry_t l_avgtemp_data;
+ const char* idd_meas_str[IDDQ_MEASUREMENTS] = IDDQ_ARRAY_VOLTAGES_STR;
+ char l_buffer_str[128]; // Temporary formatting string buffer
+ char l_line_str[128]; // Formatted output line string
// --------------------------------------------
// Process IQ Keyword (IDDQ) Data
@@ -714,60 +710,72 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
// get number of good quads per sort
uint8_t l_good_quads_per_sort = *l_buffer_iq_inc;
io_iddqt->good_quads_per_sort = l_good_quads_per_sort ;
- FAPI_INF(" IDDQ Version Number = %u", l_good_quads_per_sort);
l_buffer_iq_inc++;
// get number of normal cores per sort
uint8_t l_good_normal_cores_per_sort = *l_buffer_iq_inc;
io_iddqt->good_normal_cores_per_sort = l_good_normal_cores_per_sort ;
- FAPI_INF(" IDDQ Version Number = %u", l_good_normal_cores_per_sort);
l_buffer_iq_inc++;
// get number of good caches per sort
uint8_t l_good_caches_per_sort = *l_buffer_iq_inc;
io_iddqt->good_caches_per_sort = l_good_caches_per_sort ;
- FAPI_INF(" IDDQ Version Number = %u", l_good_caches_per_sort);
l_buffer_iq_inc++;
+ FAPI_INF(" Sort Info: Good Quads = %02d Good Caches = %02d Good Cores = %02d",
+ l_good_quads_per_sort,
+ l_good_caches_per_sort,
+ l_good_normal_cores_per_sort);
// get number of good normal cores in each quad
- for (i = 0; i < MAX_QUADS; i++)
+ strcpy(l_line_str, " Good normal cores:");
+ strcpy(l_buffer_str, "");
+
+ for (i = 0; i < MAXIMUM_QUADS; i++)
{
l_buffer_data = *l_buffer_iq_inc;
io_iddqt->good_normal_cores[i] = l_buffer_data;
- FAPI_INF("Num of good normal cores in quad %d = %u", i, l_buffer_data);
+ sprintf(l_buffer_str, " Quad %d = %u ", i, l_buffer_data);
+ strcat(l_line_str, l_buffer_str);
l_buffer_iq_inc++;
}
+ FAPI_INF("%s", l_line_str);
+
+
// get number of good caches in each quad
- for (i = 0; i < MAX_QUADS; i++)
+ strcpy(l_line_str, " Good caches: ");
+ strcpy(l_buffer_str, "");
+
+ for (i = 0; i < MAXIMUM_QUADS; i++)
{
l_buffer_data = *l_buffer_iq_inc;
io_iddqt->good_caches[i] = l_buffer_data;
- FAPI_INF("Num of good caches in quad %d = %u", i, l_buffer_data);
+ sprintf(l_buffer_str, " Quad %d = %u ", i, l_buffer_data);
+ strcat(l_line_str, l_buffer_str);
l_buffer_iq_inc++;
}
+ FAPI_INF("%s", l_line_str);
+
// get RDP TO TDP scalling factor
uint16_t l_rdp_to_tdp_scale_factor = *(reinterpret_cast<uint16_t*>(l_buffer_iq_inc));
io_iddqt->rdp_to_tdp_scale_factor = revle16(l_rdp_to_tdp_scale_factor);
- FAPI_INF("RDP TO TDP scalling factor = %u", l_rdp_to_tdp_scale_factor );
+ FAPI_INF(" RDP TO TDP scalling factor = %u", l_rdp_to_tdp_scale_factor );
l_buffer_iq_inc += 2;
// get WOF IDDQ margin factor
uint16_t l_wof_iddq_margin_factor = *(reinterpret_cast<uint16_t*>(l_buffer_iq_inc));
io_iddqt->wof_iddq_margin_factor = revle16(l_wof_iddq_margin_factor);
- FAPI_INF(" WOF IDDQ margin factor = %u", l_wof_iddq_margin_factor);
+ FAPI_INF(" WOF IDDQ margin factor = %u", l_wof_iddq_margin_factor);
l_buffer_iq_inc += 2;
// get Temperature scaling factor
uint16_t l_temperature_scale_factor = *(reinterpret_cast<uint16_t*>(l_buffer_iq_inc));
io_iddqt->temperature_scale_factor = revle16(l_temperature_scale_factor);
- FAPI_INF("Temperature scaling factor %u", l_temperature_scale_factor);
+ FAPI_INF(" Temperature scaling factor = %u", l_temperature_scale_factor);
l_buffer_iq_inc += 2;
- // get spare data
- FAPI_INF("10 bytes of spare data");
-
+ // get spare data - 10B
for (i = 0; i < 9; i++)
{
l_buffer_data = *l_buffer_iq_inc;
@@ -775,107 +783,194 @@ proc_get_mvpd_iddq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
l_buffer_iq_inc++;
}
+ // Put out the measurement voltages to the trace.
+ strcpy(l_line_str, " Measurment voltages: ");
+ strcpy(l_buffer_str, "");
+
+ for (i = 0; i < IDDQ_MEASUREMENTS; i++)
+ {
+ sprintf(l_buffer_str, " %sV", idd_meas_str[i]);
+ strcat(l_line_str, l_buffer_str);
+ }
+
+ FAPI_INF("%s", l_line_str);
+
// get IVDDQ measurements with all good cores ON
+ strcpy(l_line_str, " IDDQ all good cores ON: ");
+ strcpy(l_buffer_str, "");
+
for (i = 0; i < IDDQ_MEASUREMENTS; i++)
{
l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc));
io_iddqt->ivdd_all_good_cores_on_caches_on[i] = revle16(l_iddq_data);
- FAPI_INF(" IVDDQ with all good cores ON, Measurement %d = %u", i, l_iddq_data);
l_buffer_iq_inc += sizeof(iddq_entry_t);
+ sprintf(l_buffer_str, " %04u ", revle16(l_iddq_data));
+ strcat(l_line_str, l_buffer_str);
}
+ FAPI_INF("%s", l_line_str);
+
// get IVDDQ measurements with all cores and caches OFF
+ strcpy(l_line_str, " IVDDQ all cores and caches OFF: ");
+ strcpy(l_buffer_str, "");
+
for (i = 0; i < IDDQ_MEASUREMENTS; i++)
{
l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc));
io_iddqt->ivdd_all_cores_off_caches_off[i] = revle16(l_iddq_data);
- FAPI_INF("IVDDQ with all cores and caches OFF, Measurement %d = %u", i, l_iddq_data);
l_buffer_iq_inc += sizeof(iddq_entry_t);
+ sprintf(l_buffer_str, " %04u ", revle16(l_iddq_data));
+ strcat(l_line_str, l_buffer_str);
}
+ FAPI_INF("%s", l_line_str);;
+
// get IVDDQ measurements with all good cores OFF and caches ON
+ strcpy(l_line_str, " IVDDQ all good cores OFF and caches ON: ");
+ strcpy(l_buffer_str, "");
+
for (i = 0; i < IDDQ_MEASUREMENTS; i++)
{
l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc));
io_iddqt->ivdd_all_good_cores_off_good_caches_on[i] = revle16(l_iddq_data);
- FAPI_INF("IVDDQ with all good cores OFF and caches ON, Measurement %d = %u", i, l_iddq_data);
l_buffer_iq_inc += sizeof(iddq_entry_t);
+ sprintf(l_buffer_str, " %04u ", revle16(l_iddq_data));
+ strcat(l_line_str, l_buffer_str);
}
+ FAPI_INF("%s", l_line_str);
+
// get IVDDQ measurements with all good cores in each quad
- for (i = 0; i < MAX_QUADS; i++)
+ for (i = 0; i < MAXIMUM_QUADS; i++)
{
+ strcpy(l_line_str, " IVDDQ all good cores OFF and caches ON: ");
+ strcpy(l_buffer_str, "");
+ sprintf(l_buffer_str, "Quad %d:", i);
+ strcat(l_line_str, l_buffer_str);
+
for (j = 0; j < IDDQ_MEASUREMENTS; j++)
{
l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc));
io_iddqt->ivdd_quad_good_cores_on_good_caches_on[i][j] = revle16(l_iddq_data);
- FAPI_INF(" IVDDQ will all good cores ON , Quad %d, Measurement %d = %u", i, j, l_iddq_data);
l_buffer_iq_inc += sizeof(iddq_entry_t);
+ sprintf(l_buffer_str, " %04u ", revle16(l_iddq_data));
+ strcat(l_line_str, l_buffer_str);
}
+
+ FAPI_INF("%s", l_line_str);
}
// get IVDN data
- l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc));
- io_iddqt->ivdn = revle16(l_iddq_data);
- FAPI_INF("IVDN data = %u", l_iddq_data);
- l_buffer_iq_inc += sizeof(iddq_entry_t);
+ strcpy(l_line_str, " IVDN ");
+ strcpy(l_buffer_str, "");
+
+ for (i = 0; i < IDDQ_MEASUREMENTS; i++)
+ {
+ l_iddq_data = *(reinterpret_cast<iddq_entry_t*>(l_buffer_iq_inc));
+ io_iddqt->ivdn[i] = revle16(l_iddq_data);
+ l_buffer_iq_inc += sizeof(iddq_entry_t);
+ sprintf(l_buffer_str, " %04u ", revle16(l_iddq_data));
+ strcat(l_line_str, l_buffer_str);
+ }
+
+ FAPI_INF("%s", l_line_str);
+
+
// get average temperature measurements with all good cores ON
+ strcpy(l_line_str, " Measurment voltages: ");
+ strcpy(l_line_str, " Average temp all good cores ON: ");
+ strcpy(l_buffer_str, "");
+
for (i = 0; i < IDDQ_MEASUREMENTS; i++)
{
l_avgtemp_data = *(reinterpret_cast<avgtemp_entry_t*>(l_buffer_iq_inc));
- io_iddqt->avgtemp_all_good_cores_on[i] = revle16(l_avgtemp_data);
- FAPI_INF("Average temperature with all good cores ON, Measurement %d = %u", i, l_avgtemp_data);
- l_buffer_iq_inc += sizeof(avgtemp_entry_t);
+ io_iddqt->avgtemp_all_good_cores_on[i] = l_avgtemp_data;
+ sprintf(l_buffer_str, " %02u ", l_avgtemp_data);
+ strcat(l_line_str, l_buffer_str);
+ l_buffer_iq_inc += sizeof(l_avgtemp_data);
}
+ FAPI_INF("%s", l_line_str);
+
// get average temperature measurements with all cores and caches OFF
+ strcpy(l_line_str, " Average temp all cores OFF, caches OFF: ");
+ strcpy(l_buffer_str, "");
+
for (i = 0; i < IDDQ_MEASUREMENTS; i++)
{
l_avgtemp_data = *(reinterpret_cast<avgtemp_entry_t*>(l_buffer_iq_inc));
- io_iddqt->avgtemp_all_cores_off_caches_off[i] = revle16(l_avgtemp_data);
- FAPI_INF("Average temperature with all cores and caches OFF, Measurement %d = %u", i, l_avgtemp_data);
- l_buffer_iq_inc += sizeof(avgtemp_entry_t);
+ io_iddqt->avgtemp_all_cores_off_caches_off[i] = l_avgtemp_data;
+ l_buffer_iq_inc += sizeof(l_avgtemp_data);
+ sprintf(l_buffer_str, " %02u ", l_avgtemp_data);
+ strcat(l_line_str, l_buffer_str);
}
+ FAPI_INF("%s", l_line_str);
+
// get average temperature measurements with all good cores OFF and caches ON
+ strcpy(l_line_str, " Average temp all good cores OFF, caches ON: ");
+ strcpy(l_buffer_str, "");
+
for (i = 0; i < IDDQ_MEASUREMENTS; i++)
{
l_avgtemp_data = *(reinterpret_cast<avgtemp_entry_t*>(l_buffer_iq_inc));
- io_iddqt->avgtemp_all_good_cores_off[i] = revle16(l_avgtemp_data);
- FAPI_INF("Average temperature with all good cores OFF and caches ON, Measurement %d = %u", i, l_avgtemp_data);
- l_buffer_iq_inc += sizeof(avgtemp_entry_t);
+ io_iddqt->avgtemp_all_good_cores_off[i] = l_avgtemp_data;
+ l_buffer_iq_inc += sizeof(l_avgtemp_data);
+ sprintf(l_buffer_str, " %02u ", l_avgtemp_data);
+ strcat(l_line_str, l_buffer_str);
}
+ FAPI_INF("%s", l_line_str);
+
// get average temperature measurements with all good cores in each quad
- for (i = 0; i < MAX_QUADS; i++)
+ for (i = 0; i < MAXIMUM_QUADS; i++)
{
+ strcpy(l_line_str, " Average temp all good cores ON: ");
+ strcpy(l_buffer_str, "");
+ sprintf(l_buffer_str, "Quad %d: ", i);
+ strcat(l_line_str, l_buffer_str);
+
for (j = 0; j < IDDQ_MEASUREMENTS; j++)
{
l_avgtemp_data = *(reinterpret_cast<avgtemp_entry_t*>(l_buffer_iq_inc));
- io_iddqt->avgtemp_quad_good_cores_on[i][j] = revle16(l_avgtemp_data);
- FAPI_INF(" Average temperature will all good cores ON , Quad %d, Measurement %d = %u", i, j, l_avgtemp_data);
- l_buffer_iq_inc += sizeof(avgtemp_entry_t);
+ io_iddqt->avgtemp_quad_good_cores_on[i][j] = l_avgtemp_data;
+ l_buffer_iq_inc += sizeof(l_avgtemp_data);
+ sprintf(l_buffer_str, " %02u ", l_avgtemp_data);
+ strcat(l_line_str, l_buffer_str);
}
+
+ FAPI_INF("%s", l_line_str);
+ }
+
+ // get average nest temperature nest
+ strcpy(l_line_str, " Average temp Nest: ");
+ strcpy(l_buffer_str, "");
+
+ for (i = 0; i < IDDQ_MEASUREMENTS; i++)
+ {
+ l_avgtemp_data = *(reinterpret_cast<avgtemp_entry_t*>(l_buffer_iq_inc));
+ io_iddqt->avgtemp_vdn = revle16(l_avgtemp_data);
+ l_buffer_iq_inc += sizeof(l_avgtemp_data);
+ sprintf(l_buffer_str, " %02u ", l_avgtemp_data);
+ strcat(l_line_str, l_buffer_str);
}
- // get average temperature VDN data
- l_avgtemp_data = *(reinterpret_cast<avgtemp_entry_t*>(l_buffer_iq_inc));
- io_iddqt->avgtemp_vdn = revle16(l_avgtemp_data);
- FAPI_INF(" Average temperature VDN data = %u", l_avgtemp_data);
+ FAPI_INF("%s", l_line_str);
+
}
while(0);
-// Free up memory buffer
+ // Free up memory buffer
free(l_buffer_iq_c);
fapi_try_exit:
return fapi2::current_err;
} // proc_get_mvdp_iddq
-/// ssrivath END OF IDDQ READ FUNCTION
-//
-/// ssrivath START OF BIAS APPLICATION FUNCTION
+/// END OF IDDQ READ FUNCTION
+
+/// START OF BIAS APPLICATION FUNCTION
fapi2::ReturnCode
proc_get_extint_bias( uint32_t io_attr_mvpd_data[PV_D][PV_W],
@@ -989,10 +1084,6 @@ proc_get_extint_bias( uint32_t io_attr_mvpd_data[PV_D][PV_W],
/// ssrivath END OF BIAS APPLICATION FUNCTION
-#if 0
-ReturnCode proc_boost_gpst (PstateSuperStructure* pss,
- uint32_t attr_boost_percent)
-#endif
fapi2::ReturnCode
proc_chk_valid_poundv(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
@@ -1152,6 +1243,7 @@ load_mvpd_operating_point ( const uint32_t i_src[PV_D][PV_W],
VpdOperatingPoint* o_dest,
uint32_t i_frequency_step_khz)
{
+ FAPI_INF(">> load_mvpd_operating_point");
const uint8_t pv_op_order[VPD_PV_POINTS] = VPD_PV_ORDER;
for (uint32_t i = 0; i < VPD_PV_POINTS; i++)
@@ -1166,6 +1258,7 @@ load_mvpd_operating_point ( const uint32_t i_src[PV_D][PV_W],
o_dest[i].pstate = (i_src[ULTRA][0] - i_src[pv_op_order[i]][0]) * 1000 / i_frequency_step_khz;
}
+ FAPI_INF("<< load_mvpd_operating_point");
return fapi2::FAPI2_RC_SUCCESS;
} // end attr2wof
@@ -1229,7 +1322,7 @@ fapi2::ReturnCode
proc_res_clock_setup ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
ResonantClockingSetup* o_resclk_setup)
{
-
+ FAPI_INF(">> proc_res_clock_setup");
uint16_t l_steparray[RESCLK_STEPS];
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RESCLK_STEP_DELAY, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
@@ -1257,6 +1350,7 @@ proc_res_clock_setup ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_targ
}
fapi_try_exit:
+ FAPI_INF("<< proc_res_clock_setup");
return fapi2::current_err;
}
@@ -1264,7 +1358,7 @@ fapi2::ReturnCode
proc_get_ivrm_parms ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
IvrmParmBlock* o_ivrmpb)
{
-
+ FAPI_INF(">> proc_get_ivrm_parms");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IVRM_STRENGTH_LOOKUP, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
o_ivrmpb->strength_lookup));
@@ -1284,6 +1378,7 @@ proc_get_ivrm_parms ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_targe
o_ivrmpb->deadzone_mv));
fapi_try_exit:
+ FAPI_INF("<< proc_get_ivrm_parms");
return fapi2::current_err;
}
@@ -1307,6 +1402,9 @@ void p9_pstate_compute_vpd_pts(VpdOperatingPoint (*o_operating_points)[VPD_PV_PO
o_operating_points[VPD_PT_SET_RAW][pv_op_order[p]].ics_100ma = revle32(i_gppb->operating_points[p].ics_100ma);
o_operating_points[VPD_PT_SET_RAW][pv_op_order[p]].frequency_mhz = revle32(i_gppb->operating_points[p].frequency_mhz);
o_operating_points[VPD_PT_SET_RAW][pv_op_order[p]].pstate = i_gppb->operating_points[p].pstate;
+ FAPI_INF("Raw o_operating_points[%d][pv_op_order[%d]].pstate %u",
+ VPD_PT_SET_RAW, p,
+ o_operating_points[VPD_PT_SET_RAW][pv_op_order[p]].pstate);
}
//SYSTEM PARAMS APPLIED POINTS
@@ -1328,6 +1426,10 @@ void p9_pstate_compute_vpd_pts(VpdOperatingPoint (*o_operating_points)[VPD_PV_PO
o_operating_points[VPD_PT_SET_SYSP][pv_op_order[p]].ics_100ma = revle32(i_gppb->operating_points[p].ics_100ma);
o_operating_points[VPD_PT_SET_SYSP][pv_op_order[p]].frequency_mhz = revle32(i_gppb->operating_points[p].frequency_mhz);
o_operating_points[VPD_PT_SET_SYSP][pv_op_order[p]].pstate = i_gppb->operating_points[p].pstate;
+
+ FAPI_INF(" sys o_operating_points[%d][pv_op_order[%d]].pstate %u",
+ VPD_PT_SET_SYSP, p,
+ o_operating_points[VPD_PT_SET_SYSP][pv_op_order[p]].pstate);
}
//BIASED POINTS
@@ -1348,9 +1450,9 @@ void p9_pstate_compute_vpd_pts(VpdOperatingPoint (*o_operating_points)[VPD_PV_PO
{
o_operating_points[VPD_PT_SET_BIASED][pv_op_order[p]].pstate =
(((o_operating_points[VPD_PT_SET_BIASED][ULTRA].frequency_mhz -
- o_operating_points[VPD_PT_SET_BIASED][pv_op_order[p]].frequency_mhz) *
- 1000) /
+ o_operating_points[VPD_PT_SET_BIASED][pv_op_order[p]].frequency_mhz) * 1000) /
revle32(i_gppb->frequency_step_khz));
+
}
//BIASED POINTS and SYSTEM PARMS APPLIED POINTS
@@ -1376,6 +1478,7 @@ void p9_pstate_compute_vpd_pts(VpdOperatingPoint (*o_operating_points)[VPD_PV_PO
(o_operating_points[VPD_PT_SET_BIASED][pv_op_order[p]].frequency_mhz);
o_operating_points[VPD_PT_SET_BIASED_SYSP][pv_op_order[p]].pstate =
o_operating_points[VPD_PT_SET_BIASED][pv_op_order[p]].pstate;
+
}
}
@@ -1415,26 +1518,26 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
FAPI_INF("eVidFP[POWERSAVE] %u %04x", eVidFP[POWERSAVE], i_operating_points[VPD_PT_SET_RAW][POWERSAVE].vdd_mv);
FAPI_INF("eVidFP[NOMINAL] %u %04x", eVidFP[NOMINAL], i_operating_points[VPD_PT_SET_RAW][NOMINAL].vdd_mv);
- FAPI_INF("eVidFP[TURBO] %u", eVidFP[TURBO]);
- FAPI_INF("eVidFP[ULTRA] %u", eVidFP[ULTRA]);
+ FAPI_INF("eVidFP[TURBO] %u %04x", eVidFP[TURBO], i_operating_points[VPD_PT_SET_RAW][TURBO].vdd_mv);
+ FAPI_INF("eVidFP[ULTRA] %u %04x", eVidFP[ULTRA], i_operating_points[VPD_PT_SET_RAW][ULTRA].vdd_mv);
//Calculate slopes
tmp = (uint32_t)(eVidFP[NOMINAL] - eVidFP[POWERSAVE]) /
(uint32_t)(-i_operating_points[VPD_PT_SET_RAW][NOMINAL].pstate + i_operating_points[VPD_PT_SET_RAW][POWERSAVE].pstate);
o_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] = revle16((uint16_t)tmp);
- FAPI_INF("PsVSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] %u tmp %u",
+ FAPI_INF("PsVSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] %X tmp %X",
(revle16(o_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL])), (tmp));
tmp = (uint32_t)(eVidFP[TURBO] - eVidFP[NOMINAL]) /
(uint32_t)(-i_operating_points[VPD_PT_SET_RAW][TURBO].pstate + i_operating_points[VPD_PT_SET_RAW][NOMINAL].pstate);
o_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] = revle16((uint16_t)tmp);
- FAPI_INF("PsVSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] %u tmp %u",
+ FAPI_INF("PsVSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] %X tmp %X",
(revle16(o_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO])), (tmp));
tmp = (uint32_t)(eVidFP[ULTRA] - eVidFP[TURBO]) /
(uint32_t)(-i_operating_points[VPD_PT_SET_RAW][ULTRA].pstate + i_operating_points[VPD_PT_SET_RAW][TURBO].pstate);
o_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] = revle16((uint16_t)tmp);
- FAPI_INF("PsVSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] %u tmp %u",
+ FAPI_INF("PsVSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] %X tmp %X",
(revle16(o_gppb->PsVSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA])), (tmp));
//Calculate inverted slopes
@@ -1443,7 +1546,7 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
/ (uint32_t) (i_operating_points[VPD_PT_SET_RAW][NOMINAL].vdd_mv -
i_operating_points[VPD_PT_SET_RAW][POWERSAVE].vdd_mv);
o_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] = revle16((uint16_t)tmp);
- FAPI_INF("VPsSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] %u tmp %u",
+ FAPI_INF("VPsSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL] %X tmp %X",
(revle16(o_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_POWERSAVE_NOMINAL])), (tmp));
tmp = (uint32_t)((-i_operating_points[VPD_PT_SET_RAW][TURBO].pstate +
@@ -1451,7 +1554,7 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
/ (uint32_t) (i_operating_points[VPD_PT_SET_RAW][TURBO].vdd_mv -
i_operating_points[VPD_PT_SET_RAW][NOMINAL].vdd_mv);
o_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] = revle16((uint16_t)tmp);
- FAPI_INF("VPsSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] %u tmp %u",
+ FAPI_INF("VPsSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO] %X tmp %X",
(revle16(o_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_NOMINAL_TURBO])), (tmp));
tmp = (uint32_t)((-i_operating_points[VPD_PT_SET_RAW][ULTRA].pstate +
@@ -1459,7 +1562,7 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
/ (uint32_t) (i_operating_points[VPD_PT_SET_RAW][ULTRA].vdd_mv -
i_operating_points[VPD_PT_SET_RAW][TURBO].vdd_mv);
o_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] = revle16((uint16_t)tmp);
- FAPI_INF("VPsSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] %u tmp %u",
+ FAPI_INF("VPsSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA] %X tmp %X",
(revle16(o_gppb->VPsSlopes[VPD_SLOPES_RAW][REGION_TURBO_ULTRA])), (tmp));
//
@@ -1477,24 +1580,30 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
FAPI_INF("eVidFP[ULTRA] Biased %u", eVidFP[ULTRA]);
//Calculate slopes
+ FAPI_INF(" num %u denom %u %u %u",
+ (uint32_t)(eVidFP[NOMINAL] - eVidFP[POWERSAVE]),
+ (uint32_t)(-i_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate +
+ i_operating_points[VPD_PT_SET_BIASED][POWERSAVE].pstate),
+ (uint32_t)(-i_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate),
+ (uint32_t)i_operating_points[VPD_PT_SET_BIASED][POWERSAVE].pstate);
tmp = (uint32_t)(eVidFP[NOMINAL] - eVidFP[POWERSAVE]) /
(uint32_t)(-i_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate +
i_operating_points[VPD_PT_SET_BIASED][POWERSAVE].pstate);
o_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] = revle16((uint16_t)tmp);
- FAPI_INF("PsVSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] %u tmp %u",
+ FAPI_INF("PsVSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] %X tmp %X",
(revle16(o_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL])), (tmp));
tmp = (uint32_t)(eVidFP[TURBO] - eVidFP[NOMINAL]) /
(uint32_t)(-i_operating_points[VPD_PT_SET_BIASED][TURBO].pstate +
i_operating_points[VPD_PT_SET_BIASED][NOMINAL].pstate);
o_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] = revle16((uint16_t)tmp);
- FAPI_INF("PsVSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] %u tmp %u",
+ FAPI_INF("PsVSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] %X tmp %X",
(revle16(o_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO])), (tmp));
tmp = (uint32_t)(eVidFP[ULTRA] - eVidFP[TURBO]) /
(uint32_t)(-i_operating_points[VPD_PT_SET_BIASED][ULTRA].pstate + i_operating_points[VPD_PT_SET_BIASED][TURBO].pstate);
o_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] = revle16((uint16_t)tmp);
- FAPI_INF("PsVSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] %u tmp %u",
+ FAPI_INF("PsVSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] %X tmp %X",
(revle16(o_gppb->PsVSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA])), (tmp));
//Calculate inverted slopes
@@ -1503,7 +1612,7 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
/ (uint32_t) (i_operating_points[VPD_PT_SET_BIASED][NOMINAL].vdd_mv -
i_operating_points[VPD_PT_SET_BIASED][POWERSAVE].vdd_mv);
o_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] = revle16((uint16_t)tmp);
- FAPI_INF ("VPsSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] %u tmp %u",
+ FAPI_INF ("VPsSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL] %X tmp %X",
(revle16(o_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_POWERSAVE_NOMINAL])), (tmp));
tmp = (uint32_t)((-i_operating_points[VPD_PT_SET_BIASED][TURBO].pstate +
@@ -1511,7 +1620,7 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
/ (uint32_t) (i_operating_points[VPD_PT_SET_BIASED][TURBO].vdd_mv -
i_operating_points[VPD_PT_SET_BIASED][NOMINAL].vdd_mv);
o_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] = revle16((uint16_t)tmp);
- FAPI_INF("VPsSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] %u tmp %u",
+ FAPI_INF("VPsSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO] %X tmp %X",
(revle16(o_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_NOMINAL_TURBO])), (tmp));
tmp = (uint32_t)((-i_operating_points[VPD_PT_SET_BIASED][ULTRA].pstate +
@@ -1519,7 +1628,7 @@ void p9_pstate_compute_PsV_slopes(VpdOperatingPoint i_operating_points[][4],
/ (uint32_t) (i_operating_points[VPD_PT_SET_BIASED][ULTRA].vdd_mv -
i_operating_points[VPD_PT_SET_BIASED][TURBO].vdd_mv);
o_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] = revle16((uint16_t)tmp);
- FAPI_INF("VPsSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] %u tmp %u",
+ FAPI_INF("VPsSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA] %X tmp %X",
(revle16(o_gppb->VPsSlopes[VPD_SLOPES_BIASED][REGION_TURBO_ULTRA])), (tmp));
}
@@ -1536,7 +1645,6 @@ gppb_print(GlobalPstateParmBlock* i_gppb)
char l_temp_buffer[BUFFSIZE];
// Put out the endian-corrected scalars
-
FAPI_INF("---------------------------------------------------------------------------------------");
FAPI_INF("Global Pstate Parameter Block @ %p", i_gppb);
FAPI_INF("---------------------------------------------------------------------------------------");
@@ -1648,7 +1756,7 @@ gppb_print(GlobalPstateParmBlock* i_gppb)
revle32(i_gppb->vrm_stepdelay_value),
revle32(i_gppb->vrm_stepdelay_value));
- FAPI_INF("External VRM Parameters:\n");
+ FAPI_INF("External VRM Parameters:");
FAPI_INF(" VRM Transition Start %04X (%3d)",
revle32(i_gppb->ext_vrm_transition_start_ns),
revle32(i_gppb->ext_vrm_transition_start_ns));
@@ -1670,51 +1778,50 @@ gppb_print(GlobalPstateParmBlock* i_gppb)
revle32(i_gppb->nest_frequency_mhz));
FAPI_INF("PsVSlopes: ");
- strcpy(l_buffer, " Regions ");
+
+ strcpy(l_buffer, " Regions ");
for (uint32_t j = 0; j < VPD_NUM_SLOPES_REGION; ++j)
{
- sprintf(l_temp_buffer, " %d ", j);
+ sprintf(l_temp_buffer, " %d ", j);
strcat(l_buffer, l_temp_buffer);
}
FAPI_INF("%s", l_buffer);
- for (uint32_t i = 0; i < VPD_NUM_SLOPES_SET; i++)
+ for (uint32_t i = 0; i < VPD_NUM_SLOPES_SET; ++i)
{
sprintf(l_buffer, " Set %d : ", i);
- for (uint32_t j = 0; j < VPD_NUM_SLOPES_REGION; j++)
+ for (uint32_t j = 0; j < VPD_NUM_SLOPES_REGION; ++j)
{
- sprintf(l_temp_buffer, " %04X (%4d) ",
- revle32(i_gppb->PsVSlopes[i][j]),
- revle32(i_gppb->PsVSlopes[i][j]));
+ sprintf(l_temp_buffer, " %04X ",
+ revle16(i_gppb->PsVSlopes[i][j]));
strcat(l_buffer, l_temp_buffer);
}
FAPI_INF("%s", l_buffer);
}
- FAPI_INF("%s", l_buffer);
-
FAPI_INF("VPsSlopes: ");
- strcpy(l_buffer, " Regions ");
+ strcpy(l_buffer, " Regions ");
for (uint32_t j = 0; j < VPD_NUM_SLOPES_REGION; ++j)
{
- sprintf(l_temp_buffer, " %d ", j);
+ sprintf(l_temp_buffer, " %d ", j);
strcat(l_buffer, l_temp_buffer);
}
- for (uint32_t i = 0; i < VPD_NUM_SLOPES_SET; i++)
+ FAPI_INF("%s", l_buffer);
+
+ for (uint32_t i = 0; i < VPD_NUM_SLOPES_SET; ++i)
{
sprintf(l_buffer, " Set %d : ", i);
- for (uint32_t j = 0; j < VPD_NUM_SLOPES_REGION; j++)
+ for (uint32_t j = 0; j < VPD_NUM_SLOPES_REGION; ++j)
{
- sprintf(l_temp_buffer, " %04X (%4d) ",
- revle32(i_gppb->VPsSlopes[i][j]),
- revle32(i_gppb->VPsSlopes[i][j]));
+ sprintf(l_temp_buffer, " %04X ",
+ revle16(i_gppb->VPsSlopes[i][j]));
strcat(l_buffer, l_temp_buffer);
}
@@ -1847,6 +1954,7 @@ oppb_print(OCCPstateParmBlock* i_oppb)
}
+
// Convert frequency to Pstate number
///
/// \param stream The output stream
@@ -1879,4 +1987,3 @@ int freq2pState (const GlobalPstateParmBlock* gppb,
return rc;
}
-
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H
index ed2327856..0b9a2a0e2 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H
@@ -180,6 +180,7 @@ typedef struct
// uint32_t attr_freq_proc_refclock;
uint32_t attr_freq_proc_refclock_khz;
uint32_t attr_proc_dpll_divider;
+ uint32_t attr_nest_frequency_mhz;
// Frequency Bias attributes
int8_t attr_freq_bias_ultraturbo;
@@ -187,6 +188,13 @@ typedef struct
int8_t attr_freq_bias_nominal;
int8_t attr_freq_bias_powersave;
+// External Voltage Timing attributes
+ uint32_t attr_ext_vrm_transition_start_ns;
+ uint32_t attr_ext_vrm_transition_rate_inc_uv_per_us;
+ uint32_t attr_ext_vrm_transition_rate_dec_uv_per_us;
+ uint32_t attr_ext_vrm_stabilization_time_us;
+ uint32_t attr_ext_vrm_step_size_mv;
+
// Voltage Bias attributes
int8_t attr_voltage_ext_vdd_bias_ultraturbo;
int8_t attr_voltage_ext_vdd_bias_turbo;
@@ -205,9 +213,10 @@ typedef struct
uint32_t attr_pm_safe_frequency_mhz;
uint32_t attr_pm_safe_voltage_mv;
-// uint32_t attr_freq_core_floor;
+ uint32_t attr_freq_core_floor;
uint32_t attr_freq_core_floor_mhz;
uint32_t attr_boot_freq_mhz;
+ uint32_t attr_nest_freq_mhz;
// Resonant clock frequency attrmbutes
uint32_t attr_pm_resonant_clock_full_clock_sector_buffer_frequency_khz;
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk
index 756059f81..3faafe8ca 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.mk
@@ -31,4 +31,5 @@ $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(PPB_INCLUDES))
#$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib)
lib$(PROCEDURE)_DEPLIBS+=p9_pm_utils
lib$(PROCEDURE)_DEPLIBS+=p9_pm_get_poundv_bucket
+#lib$(PROCEDURE)_DEPLIBS+=p9_pstate_utils
$(call BUILD_PROCEDURE)
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