Updates MCA write and read timings

Allows LRDIMM's to pass MCBIST writes and reads
Updates initfile code to use new attributes

Change-Id: I69c19bdc66ca3ab1ace61bbc49101f6ca8267065
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68568
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68573
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
index 4efcb0e96..1a27cd2f7 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
@@ -62,10 +62,10 @@ constexpr uint64_t literal_2401 = 2401;
 constexpr uint64_t literal_2666 = 2666;
 constexpr uint64_t literal_9 = 9;
 constexpr uint64_t literal_10 = 10;
+constexpr uint64_t literal_11 = 11;
 constexpr uint64_t literal_24 = 24;
 constexpr uint64_t literal_266 = 266;
 constexpr uint64_t literal_1866 = 1866;
-constexpr uint64_t literal_11 = 11;
 constexpr uint64_t literal_0b1000 = 0b1000;
 constexpr uint64_t literal_0b011000 = 0b011000;
 constexpr uint64_t literal_0x02 = 0x02;
@@ -146,8 +146,8 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
         uint64_t l_def_MSS_FREQ_EQ_2133 = ((l_TGT1_ATTR_MSS_FREQ >= literal_1867) && (l_TGT1_ATTR_MSS_FREQ < literal_2134));
         uint64_t l_def_MSS_FREQ_EQ_2400 = ((l_TGT1_ATTR_MSS_FREQ >= literal_2134) && (l_TGT1_ATTR_MSS_FREQ < literal_2401));
         uint64_t l_def_MSS_FREQ_EQ_2666 = (l_TGT1_ATTR_MSS_FREQ >= literal_2666);
-        fapi2::ATTR_MSS_VPD_MR_DPHY_WLO_Type l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO));
+        fapi2::ATTR_MSS_EFF_DPHY_WLO_Type l_TGT2_ATTR_MSS_EFF_DPHY_WLO;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_EFF_DPHY_WLO));
         fapi2::ATTR_EFF_DRAM_CWL_Type l_TGT2_ATTR_EFF_DRAM_CWL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CWL, TGT2, l_TGT2_ATTR_EFF_DRAM_CWL));
         uint64_t l_def_RANK_SWITCH_TCK = (literal_4 + ((l_TGT1_ATTR_MSS_FREQ - literal_1866) / literal_266));
@@ -458,33 +458,33 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
             else if ((((l_def_MSS_FREQ_EQ_1866 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
             else if ((((l_def_MSS_FREQ_EQ_2133 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
             else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
             else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_11 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
 
             if ((l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1))
             {
                 l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT2_ATTR_EFF_DRAM_CWL[l_def_PORT_INDEX] +
-                        l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO[l_def_PORT_INDEX]) - literal_8) );
+                        l_TGT2_ATTR_MSS_EFF_DPHY_WLO[l_def_PORT_INDEX]) - literal_8) );
             }
             else if ((l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] != literal_1))
             {
                 l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT2_ATTR_EFF_DRAM_CWL[l_def_PORT_INDEX] +
-                        l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO[l_def_PORT_INDEX]) - literal_9) );
+                        l_TGT2_ATTR_MSS_EFF_DPHY_WLO[l_def_PORT_INDEX]) - literal_8) );
             }
 
             l_scom_buffer.insert<24, 6, 58, uint64_t>(literal_24 );