dd2 inits

Change-Id: Ice48f5752dcf18926b07fdd35bcc124c984ae2c3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39732
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39734
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

2 files changed, 230 insertions, 12 deletions

diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
index f116a11cd..cfbf17e55 100644
--- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
@@ -67,6 +67,7 @@ target_type 4 TARGET_TYPE_PROC_CHIP;
 define MCBIST = TGT1; # If referencing Attr from mcbist, add "MCBIST." in front
 define MCS = TGT2; # If referencing Attr from mcs, add "MCS." in front
 define SYS = TGT3; # If referencing Attr from system, add "SYS." in front
+define PROC = TGT4; # If referencing Attr from chip, add "PROC." in front
 
 define def_IS_HW  = SYS.ATTR_IS_SIMULATION == 0;
 define def_IS_SIM = SYS.ATTR_IS_SIMULATION == 1;
@@ -722,6 +723,44 @@ ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] {
 # ASYNC SETTINGS
 ##################
 
+# DD1
+#    ASYNC DIALS LIST
+#         L  = MBSECCQ_val_to_data_delay
+#         D  = MBSECCQ_nest_val_to_data_delay
+#         dn = MBSECCQ_delay_nonbypass
+#         h  = MBSECCQ_delay_valid_1x
+#    SETTINGS TABLE
+#         Keep the stable default values we've been running for DD1
+#              L  = 3
+#              D  = 0
+#              dn = 0 (0ff)
+#              h  = 0 (0ff)
+#         For performance testing put tuned 2400 settings in risk level 100
+#              L  = 5
+#              D  = 1
+#              dn = 0 (0ff)
+#              h  = 0 (0ff)
+# DD2
+#    ASYNC DIALS LIST
+#         L  = MBSECCQ_val_to_data_delay
+#         T  = MBSECCQ_bypass_tenure_3 (NEW FOR DD2)
+#         D  = MBSECCQ_nest_val_to_data_delay
+#         dn = MBSECCQ_delay_nonbypass
+#         h  = MBSECCQ_delay_valid_1x
+#    SETTINGS TABLE
+#         Optimized For   | L T      D dn    h       | mfreq, assume nfreq 2GHz | m/n min   m/n max
+#         -----------------------------------------------------------------------------------------
+#         sync            | 5 2(off) 0 1(on) 0(off)  |                          |
+#         1866 m : 2000 n | 5 2(off) 2 1(on) 0(off)  | 1.818 < mfreq < 2.000    |  909       963
+#         1:1 async ratio | 5 3(on)  2 1(on) 0(off)  | 1.818 < mfreq < 2.286    |  963      1038
+#         2133 m : 2000 n | 5 2(off) 0 1(on) 0.5(on) | 2.000 < mfreq < 2.167    | 1038      1084
+#         (Gap filler)    | 5 3(on)  2 1(on) 0(off)  | 1.818 < mfreq < 2.286    | 1084      1143
+#         2400 m : 2000 n | 5 3(on)  0 1(on) 0(off)  | 2.286 < mfreq < 2.667    | 1143      1250
+#         2667 m : 2000 n | 6 3(on)  1 1(on) 0(off)  | 2.500 < mfreq < 2.769    | 1250      1385
+
+
+# helpful expressions
+define def_mn_freq_ratio = (1000 * MCBIST.ATTR_MSS_FREQ) / SYS.ATTR_FREQ_PB_MHZ;
 define def_perf_tune_case = (MCBIST.ATTR_MSS_FREQ==2400) && (SYS.ATTR_FREQ_PB_MHZ==2000) && (SYS.ATTR_RISK_LEVEL>0);
 
 
@@ -752,6 +791,61 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE
   spyv;
   OFF; # untuned and tuned same value
 }
+
+
+# DD2
+# (note hierarchies for ECC scoms are slightly different in dd2)
+
+# "L" field
+ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv, expr;
+  5,      (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  5,      (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio < 1250); # async 2400m/2000n and below
+  6,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250);                               # async 2666m/2000n
+}
+
+# "T" field (new for DD2)
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv, expr;
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0)                                && (def_mn_freq_ratio <  963); # async 1866m/2000n
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >=  963) && (def_mn_freq_ratio < 1038); # async 1:1 optimized
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1038) && (def_mn_freq_ratio < 1084); # async 2133m/2000n
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1084) && (def_mn_freq_ratio < 1143); # async gap filler
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1143) && (def_mn_freq_ratio < 1250); # async 2400m/2000n
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250) && (def_mn_freq_ratio < 1385); # async 2666m/2000n
+}
+
+# "D" field
+ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv, expr;
+  0,      (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  2,      (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio <  963); # async 1866m/2000n
+  2,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >=  963) && (def_mn_freq_ratio < 1038); # async 1:1 optimized
+  0,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1038) && (def_mn_freq_ratio < 1084); # async 2133m/2000n
+  2,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1084) && (def_mn_freq_ratio < 1143); # async gap filler
+  0,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1143) && (def_mn_freq_ratio < 1250); # async 2400m/2000n
+  1,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250);                               # async 2666m/2000n
+}
+
+# "dn" field
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv;
+  ON; # same across all frequency settings
+}
+
+# "h" field
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv, expr;
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio <  963); # async 1866m/2000n
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >=  963) && (def_mn_freq_ratio < 1038); # async 1:1 optimized
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1038) && (def_mn_freq_ratio < 1084); # async 2133m/2000n
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1084) && (def_mn_freq_ratio < 1143); # async gap filler
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1143) && (def_mn_freq_ratio < 1250); # async 2400m/2000n
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250);                               # async 2666m/2000n
+}
+
 ############################
 # DD2 REFRESH BLOCK SETTINGS
 ############################
@@ -874,20 +968,20 @@ ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_REFRESH_BLOCK_CONFIG [when=S] {
 
 # Force clock enable high DD1 Periodics Issue
 
-espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S]{
+espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S && ATTR_CHIP_EC_FEATURE_HW384794]{
   spyv;
   ON;
 }
 
 # HW366164 - SRQ Fullness Control
 
-ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S && ATTR_CHIP_EC_FEATURE_HW366164] {
+ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S] { # still applies to dd2
   spyv;
   0b0100;
 }
 
-# Number of RMW buffers available
-
+# Number of RMW buffers available at 28
+# DD1 and DD2
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF [when=S] {
   spyv;
   0b11100;
@@ -895,8 +989,7 @@ ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF [when=S] {
 
 # All rctrl ops through tag FIFO (bit 0)
 # Serialize CMDLIST pf drop through rctrl (bit 1)
-# (bit 0 keep at 0)
-ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_RCTRL_CONFIG [when=S] {
+ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_RCTRL_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_HW375732] {
   spyv;
   0b110;
 }
@@ -908,9 +1001,15 @@ ispy  MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_
 }
 
 # AMO Caching disabled
-ispy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES [when=S && ATTR_CHIP_EC_FEATURE_HW401780] {
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES [when=S] {
+  spyv, expr;
+  0b0000000000000000000000000,     (ATTR_CHIP_EC_FEATURE_HW401780==1); # DD1
+  0b1100111111111111111111111,     (ATTR_CHIP_EC_FEATURE_HW401780!=1); # DD2
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_AMO_LIMIT_SEL [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
   spyv;
-  0b0000000000000000000000000;
+  0x8;
 }
 
 # Noise Window DIsable (HW406577)
@@ -918,3 +1017,77 @@ ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_ENABLE_UE_NOISE_WINDOW [when=S && ATTR_CHIP_EC
   spyv;
   0b0;
 }
+
+##################
+# DD2 NEW SETTINGS
+##################
+
+ispy MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OPT_RD_SIZE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b011;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_AMO_SIZE_SELECT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  128B_RW_64B_DATA;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF0_AMO_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b100000;
+}
+
+espy MCP.PORT0.WRITE.NEW_WRITE_64B_MODE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_FORCE_PF_DROP0 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  OFF;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE0 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  1;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE1 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  3;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE2 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  5;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE3 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  7;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_ENABLE_REFRESH_BLOCK_DISP [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  OFF;
+}
+
+#################
+# DD2 WORKAROUNDS
+#################
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_DISABLE_WRTO_IG [when=S && ATTR_CHIP_EC_FEATURE_HW401131] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_AMO_MSI_RMW_ONLY [when=S && ATTR_CHIP_EC_FEATURE_HW399466] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CL0 [when=S && ATTR_CHIP_EC_FEATURE_HW355538] {
+  spyv;
+  ON;
+}
+
diff --git a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
index ae7477f64..965c54d25 100644
--- a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
@@ -82,7 +82,7 @@ espy MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_FP_M_BIT [when=S] {
 }
 
 # HW376110
-ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_HW376110] {
+ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S] { # still applies for dd2
   spyv;
   0b0111;
 }
@@ -104,12 +104,57 @@ ispy MC01.PBI01.SCOMFIR.MCMODE2_DISABLE_MDI0 [when=S && ATTR_CHIP_EC_FEATURE_HW4
 # when a prefetch gets dropped. DROP_CNT_THRESH determines the rate the counter decrements (in units
 # of 4 nest clocks) -- here, 8 * 4 nclks = 32 nclks, 32 nclks * 6 counts => takes 192 nest clocks
 # to drop a prefetch. This dial may need to be tuned for performance.
-espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_CMDLIST [when=S && ATTR_CHIP_EC_FEATURE_HW398139] {
+espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_CMDLIST [when=S] { # enable for dd1 and dd2
   spyv;
   ON;
 }
 
-ispy MC01.PBI01.SCOMFIR.MCPERF1_PF_DROP_CNT_THRESH [when=S && ATTR_CHIP_EC_FEATURE_HW398139] {
+ispy MC01.PBI01.SCOMFIR.MCPERF1_PF_DROP_CNT_THRESH [when=S] {
+  spyv, expr;
+  8,      (ATTR_CHIP_EC_FEATURE_HW398139==1); # dd1 (arbitrarily chosen, empirically found to be stable)
+  25,     (ATTR_CHIP_EC_FEATURE_HW398139!=1); # dd2 (performance chosen)
+}
+
+##################
+# DD2 NEW SETTINGS
+##################
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_ENABLE_CENTAUR_SYNC [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_ENABLE_64_128B_READ [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
   spyv;
-  8;
+  ON;
 }
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+ispy MC01.PBI01.SCOMFIR.MCPERF1_WRQ_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b001111;
+}
+
+ispy MC01.PBI01.SCOMFIR.MCMODE2_COLLISION_MODES [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b0000000000001000;
+}
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_CENTAURP_ENABLE_ECRESP [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  OFF;
+}
+
+espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PREFETCH_PROMOTE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+#################
+# DD2 WORKAROUNDS
+#################
+