dd2 inits

Change-Id: Ice48f5752dcf18926b07fdd35bcc124c984ae2c3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39732
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39734
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

5 files changed, 656 insertions, 73 deletions

diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
index f116a11cd..cfbf17e55 100644
--- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile
@@ -67,6 +67,7 @@ target_type 4 TARGET_TYPE_PROC_CHIP;
 define MCBIST = TGT1; # If referencing Attr from mcbist, add "MCBIST." in front
 define MCS = TGT2; # If referencing Attr from mcs, add "MCS." in front
 define SYS = TGT3; # If referencing Attr from system, add "SYS." in front
+define PROC = TGT4; # If referencing Attr from chip, add "PROC." in front
 
 define def_IS_HW  = SYS.ATTR_IS_SIMULATION == 0;
 define def_IS_SIM = SYS.ATTR_IS_SIMULATION == 1;
@@ -722,6 +723,44 @@ ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] {
 # ASYNC SETTINGS
 ##################
 
+# DD1
+#    ASYNC DIALS LIST
+#         L  = MBSECCQ_val_to_data_delay
+#         D  = MBSECCQ_nest_val_to_data_delay
+#         dn = MBSECCQ_delay_nonbypass
+#         h  = MBSECCQ_delay_valid_1x
+#    SETTINGS TABLE
+#         Keep the stable default values we've been running for DD1
+#              L  = 3
+#              D  = 0
+#              dn = 0 (0ff)
+#              h  = 0 (0ff)
+#         For performance testing put tuned 2400 settings in risk level 100
+#              L  = 5
+#              D  = 1
+#              dn = 0 (0ff)
+#              h  = 0 (0ff)
+# DD2
+#    ASYNC DIALS LIST
+#         L  = MBSECCQ_val_to_data_delay
+#         T  = MBSECCQ_bypass_tenure_3 (NEW FOR DD2)
+#         D  = MBSECCQ_nest_val_to_data_delay
+#         dn = MBSECCQ_delay_nonbypass
+#         h  = MBSECCQ_delay_valid_1x
+#    SETTINGS TABLE
+#         Optimized For   | L T      D dn    h       | mfreq, assume nfreq 2GHz | m/n min   m/n max
+#         -----------------------------------------------------------------------------------------
+#         sync            | 5 2(off) 0 1(on) 0(off)  |                          |
+#         1866 m : 2000 n | 5 2(off) 2 1(on) 0(off)  | 1.818 < mfreq < 2.000    |  909       963
+#         1:1 async ratio | 5 3(on)  2 1(on) 0(off)  | 1.818 < mfreq < 2.286    |  963      1038
+#         2133 m : 2000 n | 5 2(off) 0 1(on) 0.5(on) | 2.000 < mfreq < 2.167    | 1038      1084
+#         (Gap filler)    | 5 3(on)  2 1(on) 0(off)  | 1.818 < mfreq < 2.286    | 1084      1143
+#         2400 m : 2000 n | 5 3(on)  0 1(on) 0(off)  | 2.286 < mfreq < 2.667    | 1143      1250
+#         2667 m : 2000 n | 6 3(on)  1 1(on) 0(off)  | 2.500 < mfreq < 2.769    | 1250      1385
+
+
+# helpful expressions
+define def_mn_freq_ratio = (1000 * MCBIST.ATTR_MSS_FREQ) / SYS.ATTR_FREQ_PB_MHZ;
 define def_perf_tune_case = (MCBIST.ATTR_MSS_FREQ==2400) && (SYS.ATTR_FREQ_PB_MHZ==2000) && (SYS.ATTR_RISK_LEVEL>0);
 
 
@@ -752,6 +791,61 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE
   spyv;
   OFF; # untuned and tuned same value
 }
+
+
+# DD2
+# (note hierarchies for ECC scoms are slightly different in dd2)
+
+# "L" field
+ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv, expr;
+  5,      (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  5,      (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio < 1250); # async 2400m/2000n and below
+  6,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250);                               # async 2666m/2000n
+}
+
+# "T" field (new for DD2)
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv, expr;
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0)                                && (def_mn_freq_ratio <  963); # async 1866m/2000n
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >=  963) && (def_mn_freq_ratio < 1038); # async 1:1 optimized
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1038) && (def_mn_freq_ratio < 1084); # async 2133m/2000n
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1084) && (def_mn_freq_ratio < 1143); # async gap filler
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1143) && (def_mn_freq_ratio < 1250); # async 2400m/2000n
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250) && (def_mn_freq_ratio < 1385); # async 2666m/2000n
+}
+
+# "D" field
+ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv, expr;
+  0,      (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  2,      (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio <  963); # async 1866m/2000n
+  2,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >=  963) && (def_mn_freq_ratio < 1038); # async 1:1 optimized
+  0,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1038) && (def_mn_freq_ratio < 1084); # async 2133m/2000n
+  2,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1084) && (def_mn_freq_ratio < 1143); # async gap filler
+  0,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1143) && (def_mn_freq_ratio < 1250); # async 2400m/2000n
+  1,      (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250);                               # async 2666m/2000n
+}
+
+# "dn" field
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv;
+  ON; # same across all frequency settings
+}
+
+# "h" field
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+  spyv, expr;
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio <  963); # async 1866m/2000n
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >=  963) && (def_mn_freq_ratio < 1038); # async 1:1 optimized
+  ON,     (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1038) && (def_mn_freq_ratio < 1084); # async 2133m/2000n
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1084) && (def_mn_freq_ratio < 1143); # async gap filler
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1143) && (def_mn_freq_ratio < 1250); # async 2400m/2000n
+  OFF,    (PROC.ATTR_MC_SYNC_MODE==0) && (def_mn_freq_ratio >= 1250);                               # async 2666m/2000n
+}
+
 ############################
 # DD2 REFRESH BLOCK SETTINGS
 ############################
@@ -874,20 +968,20 @@ ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_REFRESH_BLOCK_CONFIG [when=S] {
 
 # Force clock enable high DD1 Periodics Issue
 
-espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S]{
+espy  MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OE_ALWAYS_ON [when=S && ATTR_CHIP_EC_FEATURE_HW384794]{
   spyv;
   ON;
 }
 
 # HW366164 - SRQ Fullness Control
 
-ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S && ATTR_CHIP_EC_FEATURE_HW366164] {
+ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S] { # still applies to dd2
   spyv;
   0b0100;
 }
 
-# Number of RMW buffers available
-
+# Number of RMW buffers available at 28
+# DD1 and DD2
 ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF [when=S] {
   spyv;
   0b11100;
@@ -895,8 +989,7 @@ ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF [when=S] {
 
 # All rctrl ops through tag FIFO (bit 0)
 # Serialize CMDLIST pf drop through rctrl (bit 1)
-# (bit 0 keep at 0)
-ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_RCTRL_CONFIG [when=S] {
+ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_RCTRL_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_HW375732] {
   spyv;
   0b110;
 }
@@ -908,9 +1001,15 @@ ispy  MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_
 }
 
 # AMO Caching disabled
-ispy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES [when=S && ATTR_CHIP_EC_FEATURE_HW401780] {
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES [when=S] {
+  spyv, expr;
+  0b0000000000000000000000000,     (ATTR_CHIP_EC_FEATURE_HW401780==1); # DD1
+  0b1100111111111111111111111,     (ATTR_CHIP_EC_FEATURE_HW401780!=1); # DD2
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_AMO_LIMIT_SEL [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
   spyv;
-  0b0000000000000000000000000;
+  0x8;
 }
 
 # Noise Window DIsable (HW406577)
@@ -918,3 +1017,77 @@ ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_ENABLE_UE_NOISE_WINDOW [when=S && ATTR_CHIP_EC
   spyv;
   0b0;
 }
+
+##################
+# DD2 NEW SETTINGS
+##################
+
+ispy MCP.PORT0.SRQ.MBA_FARB0Q_CFG_OPT_RD_SIZE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b011;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_AMO_SIZE_SELECT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  128B_RW_64B_DATA;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF0_AMO_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b100000;
+}
+
+espy MCP.PORT0.WRITE.NEW_WRITE_64B_MODE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCAMOC_FORCE_PF_DROP0 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  OFF;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE0 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  1;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE1 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  3;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE2 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  5;
+}
+
+ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE3 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  7;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_ENABLE_REFRESH_BLOCK_DISP [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  OFF;
+}
+
+#################
+# DD2 WORKAROUNDS
+#################
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_DISABLE_WRTO_IG [when=S && ATTR_CHIP_EC_FEATURE_HW401131] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_AMO_MSI_RMW_ONLY [when=S && ATTR_CHIP_EC_FEATURE_HW399466] {
+  spyv;
+  ON;
+}
+
+espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CL0 [when=S && ATTR_CHIP_EC_FEATURE_HW355538] {
+  spyv;
+  ON;
+}
+
diff --git a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
index ae7477f64..965c54d25 100644
--- a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile
@@ -82,7 +82,7 @@ espy MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_FP_M_BIT [when=S] {
 }
 
 # HW376110
-ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_HW376110] {
+ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S] { # still applies for dd2
   spyv;
   0b0111;
 }
@@ -104,12 +104,57 @@ ispy MC01.PBI01.SCOMFIR.MCMODE2_DISABLE_MDI0 [when=S && ATTR_CHIP_EC_FEATURE_HW4
 # when a prefetch gets dropped. DROP_CNT_THRESH determines the rate the counter decrements (in units
 # of 4 nest clocks) -- here, 8 * 4 nclks = 32 nclks, 32 nclks * 6 counts => takes 192 nest clocks
 # to drop a prefetch. This dial may need to be tuned for performance.
-espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_CMDLIST [when=S && ATTR_CHIP_EC_FEATURE_HW398139] {
+espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PF_DROP_CMDLIST [when=S] { # enable for dd1 and dd2
   spyv;
   ON;
 }
 
-ispy MC01.PBI01.SCOMFIR.MCPERF1_PF_DROP_CNT_THRESH [when=S && ATTR_CHIP_EC_FEATURE_HW398139] {
+ispy MC01.PBI01.SCOMFIR.MCPERF1_PF_DROP_CNT_THRESH [when=S] {
+  spyv, expr;
+  8,      (ATTR_CHIP_EC_FEATURE_HW398139==1); # dd1 (arbitrarily chosen, empirically found to be stable)
+  25,     (ATTR_CHIP_EC_FEATURE_HW398139!=1); # dd2 (performance chosen)
+}
+
+##################
+# DD2 NEW SETTINGS
+##################
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_ENABLE_CENTAUR_SYNC [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_ENABLE_64_128B_READ [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
   spyv;
-  8;
+  ON;
 }
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+ispy MC01.PBI01.SCOMFIR.MCPERF1_WRQ_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b001111;
+}
+
+ispy MC01.PBI01.SCOMFIR.MCMODE2_COLLISION_MODES [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  0b0000000000001000;
+}
+
+espy MC01.PBI01.SCOMFIR.MCMODE0_CENTAURP_ENABLE_ECRESP [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  OFF;
+}
+
+espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PREFETCH_PROMOTE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+  spyv;
+  ON;
+}
+
+#################
+# DD2 WORKAROUNDS
+#################
+
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
index bb90c5ee7..7aad7d3bb 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C
@@ -29,6 +29,7 @@
 
 using namespace fapi2;
 
+constexpr uint64_t literal_0b100000 = 0b100000;
 constexpr uint64_t literal_1 = 1;
 constexpr uint64_t literal_2 = 2;
 constexpr uint64_t literal_0 = 0;
@@ -43,19 +44,21 @@ constexpr uint64_t literal_0b011 = 0b011;
 constexpr uint64_t literal_0b0100 = 0b0100;
 constexpr uint64_t literal_0b11100 = 0b11100;
 constexpr uint64_t literal_0b110 = 0b110;
+constexpr uint64_t literal_3 = 3;
+constexpr uint64_t literal_5 = 5;
+constexpr uint64_t literal_7 = 7;
 constexpr uint64_t literal_0b0000000000000000000000000 = 0b0000000000000000000000000;
+constexpr uint64_t literal_0b1100111111111111111111111 = 0b1100111111111111111111111;
 constexpr uint64_t literal_0x1 = 0x1;
 constexpr uint64_t literal_6 = 6;
+constexpr uint64_t literal_0x8 = 0x8;
 constexpr uint64_t literal_17 = 17;
 constexpr uint64_t literal_1867 = 1867;
-constexpr uint64_t literal_7 = 7;
 constexpr uint64_t literal_2134 = 2134;
 constexpr uint64_t literal_2401 = 2401;
 constexpr uint64_t literal_2666 = 2666;
-constexpr uint64_t literal_3 = 3;
 constexpr uint64_t literal_9 = 9;
 constexpr uint64_t literal_24 = 24;
-constexpr uint64_t literal_5 = 5;
 constexpr uint64_t literal_267 = 267;
 constexpr uint64_t literal_1866 = 1866;
 constexpr uint64_t literal_10 = 10;
@@ -76,6 +79,13 @@ constexpr uint64_t literal_768 = 768;
 constexpr uint64_t literal_939 = 939;
 constexpr uint64_t literal_2000 = 2000;
 constexpr uint64_t literal_2400 = 2400;
+constexpr uint64_t literal_1250 = 1250;
+constexpr uint64_t literal_1000 = 1000;
+constexpr uint64_t literal_963 = 963;
+constexpr uint64_t literal_1038 = 1038;
+constexpr uint64_t literal_1084 = 1084;
+constexpr uint64_t literal_1143 = 1143;
+constexpr uint64_t literal_1385 = 1385;
 
 fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
                               const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT2,
@@ -105,6 +115,8 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
         uint64_t l_def_refblock_off_special_case = (((l_def_is_dual_slot == literal_0)
                 && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_4))
                 && (l_def_SLOT0_DRAM_STACK_HEIGHT == literal_2));
+        fapi2::ATTR_CHIP_EC_FEATURE_HW401780_Type l_TGT4_ATTR_CHIP_EC_FEATURE_HW401780;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW401780, TGT4, l_TGT4_ATTR_CHIP_EC_FEATURE_HW401780));
         fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT3, l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0));
         uint64_t l_def_MC_EPSILON_CFG_T0 = ((l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0 + literal_6) / literal_4);
@@ -183,8 +195,20 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, TGT3, l_TGT3_ATTR_FREQ_PB_MHZ));
         uint64_t l_def_perf_tune_case = (((l_TGT1_ATTR_MSS_FREQ == literal_2400) && (l_TGT3_ATTR_FREQ_PB_MHZ == literal_2000))
                                          && (l_TGT3_ATTR_RISK_LEVEL > literal_0));
+        fapi2::ATTR_MC_SYNC_MODE_Type l_TGT4_ATTR_MC_SYNC_MODE;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, TGT4, l_TGT4_ATTR_MC_SYNC_MODE));
+        uint64_t l_def_mn_freq_ratio = ((literal_1000 * l_TGT1_ATTR_MSS_FREQ) / l_TGT3_ATTR_FREQ_PB_MHZ);
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5010823ull, l_scom_buffer ));
+
+                l_scom_buffer.insert<22, 6, 58, uint64_t>(literal_0b100000 );
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5010823ull, l_scom_buffer));
+            }
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5010824ull, l_scom_buffer ));
 
             if ((l_def_NUM_RANKS == literal_1))
@@ -262,23 +286,67 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
                 l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b100 );
             }
 
+            l_scom_buffer.insert<28, 4, 60, uint64_t>(literal_0b0100 );
+            l_scom_buffer.insert<50, 5, 59, uint64_t>(literal_0b11100 );
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                l_scom_buffer.insert<28, 4, 60, uint64_t>(literal_0b0100 );
+                l_scom_buffer.insert<37, 3, 61, uint64_t>(literal_0b110 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                l_scom_buffer.insert<0, 3, 61, uint64_t>(literal_1 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                l_scom_buffer.insert<3, 3, 61, uint64_t>(literal_3 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                l_scom_buffer.insert<6, 3, 61, uint64_t>(literal_5 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                l_scom_buffer.insert<9, 3, 61, uint64_t>(literal_7 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_DISP_OFF = 0x0;
+                l_scom_buffer.insert<18, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_DISP_OFF );
             }
 
-            l_scom_buffer.insert<50, 5, 59, uint64_t>(literal_0b11100 );
-            l_scom_buffer.insert<37, 3, 61, uint64_t>(literal_0b110 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010824ull, l_scom_buffer));
         }
         {
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
-            {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x5010825ull, l_scom_buffer ));
+            FAPI_TRY(fapi2::getScom( TGT0, 0x5010825ull, l_scom_buffer ));
 
+            if ((l_TGT4_ATTR_CHIP_EC_FEATURE_HW401780 == literal_1))
+            {
                 l_scom_buffer.insert<4, 25, 39, uint64_t>(literal_0b0000000000000000000000000 );
-                FAPI_TRY(fapi2::putScom(TGT0, 0x5010825ull, l_scom_buffer));
             }
+            else if ((l_TGT4_ATTR_CHIP_EC_FEATURE_HW401780 != literal_1))
+            {
+                l_scom_buffer.insert<4, 25, 39, uint64_t>(literal_0b1100111111111111111111111 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_128B_RW_64B_DATA = 0x1;
+                l_scom_buffer.insert<29, 3, 61, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_128B_RW_64B_DATA );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCAMOC_FORCE_PF_DROP0_OFF = 0x0;
+                l_scom_buffer.insert<1, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCAMOC_FORCE_PF_DROP0_OFF );
+            }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x5010825ull, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5010826ull, l_scom_buffer ));
@@ -292,6 +360,21 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010826ull, l_scom_buffer));
         }
         {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x501082bull, l_scom_buffer ));
+
+                l_scom_buffer.insert<45, 1, 63, uint64_t>(literal_0x8 );
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_DISABLE_WRTO_IG_ON = 0x1;
+                l_scom_buffer.insert<44, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_DISABLE_WRTO_IG_ON );
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY_ON = 0x1;
+                l_scom_buffer.insert<41, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY_ON );
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CL0_ON = 0x1;
+                l_scom_buffer.insert<31, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CL0_ON );
+                FAPI_TRY(fapi2::putScom(TGT0, 0x501082bull, l_scom_buffer));
+            }
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x701090aull, l_scom_buffer ));
 
             if (l_def_IS_SIM)
@@ -464,8 +547,17 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
                 l_scom_buffer.insert<17, 1, 63, uint64_t>(literal_0b0 );
             }
 
-            constexpr auto l_MCP_PORT0_SRQ_MBA_FARB0Q_CFG_OE_ALWAYS_ON_ON = 0x1;
-            l_scom_buffer.insert<55, 1, 63, uint64_t>(l_MCP_PORT0_SRQ_MBA_FARB0Q_CFG_OE_ALWAYS_ON_ON );
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
+                constexpr auto l_MCP_PORT0_SRQ_MBA_FARB0Q_CFG_OE_ALWAYS_ON_ON = 0x1;
+                l_scom_buffer.insert<55, 1, 63, uint64_t>(l_MCP_PORT0_SRQ_MBA_FARB0Q_CFG_OE_ALWAYS_ON_ON );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                l_scom_buffer.insert<61, 3, 61, uint64_t>(literal_0b011 );
+            }
+
             FAPI_TRY(fapi2::putScom(TGT0, 0x7010913ull, l_scom_buffer));
         }
         {
@@ -814,10 +906,10 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
             FAPI_TRY(fapi2::putScom(TGT0, 0x7010935ull, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x7010a0aull, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x7010a0aull, l_scom_buffer ));
-
                 if ((l_def_perf_tune_case == literal_0))
                 {
                     l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_3 );
@@ -826,7 +918,10 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
                 {
                     l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_5 );
                 }
+            }
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
                 if ((l_def_perf_tune_case == literal_0))
                 {
                     l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_0 );
@@ -835,13 +930,180 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0,
                 {
                     l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_1 );
                 }
+            }
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
                 constexpr auto l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0;
                 l_scom_buffer.insert<22, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_NONBYPASS_OFF );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
                 constexpr auto l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
                 l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if ((l_TGT4_ATTR_MC_SYNC_MODE == literal_1))
+                {
+                    l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_5 );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio < literal_1250)))
+                {
+                    l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_5 );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1250)))
+                {
+                    l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_6 );
+                }
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if ((l_TGT4_ATTR_MC_SYNC_MODE == literal_1))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_OFF = 0x0;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_OFF );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio < literal_963)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_OFF = 0x0;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_OFF );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_963))
+                          && (l_def_mn_freq_ratio < literal_1038)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON = 0x1;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1038))
+                          && (l_def_mn_freq_ratio < literal_1084)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_OFF = 0x0;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_OFF );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1084))
+                          && (l_def_mn_freq_ratio < literal_1143)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON = 0x1;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1143))
+                          && (l_def_mn_freq_ratio < literal_1250)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON = 0x1;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1250))
+                          && (l_def_mn_freq_ratio < literal_1385)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON = 0x1;
+                    l_scom_buffer.insert<40, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_BYPASS_TENURE_3_ON );
+                }
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if ((l_TGT4_ATTR_MC_SYNC_MODE == literal_1))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_0 );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio < literal_963)))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_2 );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_963))
+                          && (l_def_mn_freq_ratio < literal_1038)))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_2 );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1038))
+                          && (l_def_mn_freq_ratio < literal_1084)))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_0 );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1084))
+                          && (l_def_mn_freq_ratio < literal_1143)))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_2 );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1143))
+                          && (l_def_mn_freq_ratio < literal_1250)))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_0 );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1250)))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_1 );
+                }
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_NONBYPASS_ON = 0x1;
+                l_scom_buffer.insert<22, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_NONBYPASS_ON );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if ((l_TGT4_ATTR_MC_SYNC_MODE == literal_1))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio < literal_963)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_963))
+                          && (l_def_mn_freq_ratio < literal_1038)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1038))
+                          && (l_def_mn_freq_ratio < literal_1084)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_ON = 0x1;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_ON );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1084))
+                          && (l_def_mn_freq_ratio < literal_1143)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+                }
+                else if ((((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1143))
+                          && (l_def_mn_freq_ratio < literal_1250)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+                }
+                else if (((l_TGT4_ATTR_MC_SYNC_MODE == literal_0) && (l_def_mn_freq_ratio >= literal_1250)))
+                {
+                    constexpr auto l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                    l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_ECC_SCOM_MBSECCQ_DELAY_VALID_1X_OFF );
+                }
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
                 l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0b0 );
-                FAPI_TRY(fapi2::putScom(TGT0, 0x7010a0aull, l_scom_buffer));
+            }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x7010a0aull, l_scom_buffer));
+        }
+        {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x7010a38ull, l_scom_buffer ));
+
+                constexpr auto l_MCP_PORT0_WRITE_NEW_WRITE_64B_MODE_ON = 0x1;
+                l_scom_buffer.insert<9, 1, 63, uint64_t>(l_MCP_PORT0_WRITE_NEW_WRITE_64B_MODE_ON );
+                FAPI_TRY(fapi2::putScom(TGT0, 0x7010a38ull, l_scom_buffer));
             }
         }
 
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mcs_scom.C
index 07fe70221..07faf268d 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mcs_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mcs_scom.C
@@ -31,8 +31,12 @@ using namespace fapi2;
 
 constexpr uint64_t literal_0b0111 = 0b0111;
 constexpr uint64_t literal_0 = 0;
+constexpr uint64_t literal_1 = 1;
 constexpr uint64_t literal_8 = 8;
+constexpr uint64_t literal_25 = 25;
+constexpr uint64_t literal_0b001111 = 0b001111;
 constexpr uint64_t literal_0b0001100000000 = 0b0001100000000;
+constexpr uint64_t literal_0b0000000000001000 = 0b0000000000001000;
 
 fapi2::ReturnCode p9_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0,
                               const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2)
@@ -42,33 +46,58 @@ fapi2::ReturnCode p9_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0,
         fapi2::ATTR_NAME_Type l_chip_id;
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT2, l_chip_id));
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec));
+        fapi2::ATTR_CHIP_EC_FEATURE_HW398139_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW398139, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139));
         fapi2::ATTR_RISK_LEVEL_Type l_TGT1_ATTR_RISK_LEVEL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, TGT1, l_TGT1_ATTR_RISK_LEVEL));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5010810ull, l_scom_buffer ));
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            l_scom_buffer.insert<46, 4, 60, uint64_t>(literal_0b0111 );
+            l_scom_buffer.insert<62, 1, 63, uint64_t>(literal_0 );
+            constexpr auto l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PF_DROP_CMDLIST_ON = 0x1;
+            l_scom_buffer.insert<61, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PF_DROP_CMDLIST_ON );
+
+            if ((l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139 == literal_1))
             {
-                l_scom_buffer.insert<46, 4, 60, uint64_t>(literal_0b0111 );
+                l_scom_buffer.insert<32, 7, 57, uint64_t>(literal_8 );
+            }
+            else if ((l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139 != literal_1))
+            {
+                l_scom_buffer.insert<32, 7, 57, uint64_t>(literal_25 );
             }
 
-            l_scom_buffer.insert<62, 1, 63, uint64_t>(literal_0 );
-
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
             {
-                constexpr auto l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PF_DROP_CMDLIST_ON = 0x1;
-                l_scom_buffer.insert<61, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PF_DROP_CMDLIST_ON );
+                l_scom_buffer.insert<55, 6, 58, uint64_t>(literal_0b001111 );
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
             {
-                l_scom_buffer.insert<32, 7, 57, uint64_t>(literal_8 );
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PREFETCH_PROMOTE_ON = 0x1;
+                l_scom_buffer.insert<63, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCPERF1_ENABLE_PREFETCH_PROMOTE_ON );
             }
 
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010810ull, l_scom_buffer));
         }
         {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5010811ull, l_scom_buffer ));
+
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_CENTAUR_SYNC_ON = 0x1;
+                l_scom_buffer.insert<20, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_CENTAUR_SYNC_ON );
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_64_128B_READ_ON = 0x1;
+                l_scom_buffer.insert<9, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_64_128B_READ_ON );
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE_ON = 0x1;
+                l_scom_buffer.insert<8, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE_ON );
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF = 0x0;
+                l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF );
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5010811ull, l_scom_buffer));
+            }
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5010812ull, l_scom_buffer ));
 
             constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE1_DISABLE_FP_M_BIT_ON = 0x1;
@@ -76,17 +105,22 @@ fapi2::ReturnCode p9_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0,
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010812ull, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x5010813ull, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x5010813ull, l_scom_buffer ));
-
                 if ((l_TGT1_ATTR_RISK_LEVEL == literal_0))
                 {
                     l_scom_buffer.insert<1, 13, 51, uint64_t>(literal_0b0001100000000 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x5010813ull, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                l_scom_buffer.insert<24, 16, 48, uint64_t>(literal_0b0000000000001000 );
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x5010813ull, l_scom_buffer));
         }
 
     };
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index d2700cfbc..1b4bc6faf 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -393,23 +393,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW376110</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-        HW376110
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>LESS_THAN</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW375534</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -427,23 +410,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW366164</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-        HW366164 - SRQ Fullness Control
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>LESS_THAN</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW366248</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2692,6 +2658,40 @@
   </attribute>
 
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW384794</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Workaround for defect where clock enables to PHY were incorrectly driven
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW375732</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Workaround for Data mismatch discovered by Geyzer at certain async frequency ratios
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2936,6 +2936,23 @@
   </attribute>
 
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW401131</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Since amo cache clean line disabled for dd2, fix for HW401131 must also be disabled.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2985,6 +3002,58 @@
       </chip>
     </chipEcFeature>
   </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW399466</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Enable fix for HW399466 where all read data for amo smi ops is sent to rmw buffer.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW355538</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Enable fix for HW355538 that enables write MDI to 1 for retry UE.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Not workaround or defect related. Just new dials to be set that are new in memory controller for DD2.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <!-- ******************************************************************** -->
   <!-- End Memory Section                                                   -->
   <!-- ******************************************************************** -->