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author | Shelton Leung <sleung@us.ibm.com> | 2017-08-14 12:38:29 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-31 13:57:37 -0400 |
commit | 449ed13c95fa006286a38827c6703788ff640757 (patch) | |
tree | f7ea12996ded3037e8d6b87b6ac1dfc14e185b3c /src/import/chips/p9/initfiles | |
parent | e1678bffbd5cba43911f7e6f670ac3c3bb68af39 (diff) | |
download | talos-hostboot-449ed13c95fa006286a38827c6703788ff640757.tar.gz talos-hostboot-449ed13c95fa006286a38827c6703788ff640757.zip |
enable MC timeout detection
Change-Id: Ifeb1a990280301b4aef7ab0e74a698f65c8f5f06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44607
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44613
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/initfiles')
-rw-r--r-- | src/import/chips/p9/initfiles/p9n.mcs.scom.initfile | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile index 1cac62958..9eedf66f3 100644 --- a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile +++ b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile @@ -74,6 +74,62 @@ define MCBIST = TGT3; # If referencing Attr from mcbist, add "MCBIST." in front +############################## +# NON BUG SETTINGS ADJUSTMENTS +############################## + +# Enable memory controller hang counters +define def_ENABLE_MCU_TIMEOUTS = 1; + +# Use PB-initiated hang mechanism +espy MC01.PBI01.SCOMFIR.MCTO_SELECT_PB_HANG_PULSE [when=S] { + spyv, expr; + ON, (def_ENABLE_MCU_TIMEOUTS==1); +} +espy MC01.PBI01.SCOMFIR.MCTO_SELECT_LOCAL_HANG_PULSE [when=S] { + spyv; + OFF; +} + +# Enable all CLSTATE hang mechanisms +espy MC01.PBI01.SCOMFIR.MCTO_ENABLE_NONMIRROR_HANG [when=S] { + spyv, expr; + ON, (def_ENABLE_MCU_TIMEOUTS==1); # Hang for all non-mirrored operations +} +espy MC01.PBI01.SCOMFIR.MCTO_ENABLE_APO_HANG [when=S] { + spyv, expr; + ON, (def_ENABLE_MCU_TIMEOUTS==1); # Hang for address protection only CLSTATE machines +} + +# Use RPT_HANG.POLL to trigger PB hang +ispy MC01.PBI01.SCOMFIR.MCTO_RPTHANG_SELECT [when=S && !ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd1 name + spyv; + 0b01; # 0.87381ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_RPT_HANG_SELECT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd2 name + spyv; + 0b01; # 0.87381ms +} + +# Setup hang compare values +# Count a single pulse and let the secondary counters scale it +ispy MC01.PBI01.SCOMFIR.MCTO_COMP_MASK [when=S && !ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd1 name + spyv, expr; + 1, (def_ENABLE_MCU_TIMEOUTS==1); # 0.87381ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_HANG_COMP [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd2 name + spyv, expr; + 1, (def_ENABLE_MCU_TIMEOUTS==1); # 0.87381ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_TIMEOUT_VALUE [when=S && !ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd1 name + spyv, expr; + 7, (def_ENABLE_MCU_TIMEOUTS==1); # 6.11669ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_CL_TIMEOUT_VALUE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd2 name + spyv, expr; + 7, (def_ENABLE_MCU_TIMEOUTS==1); # 6.11669ms +} + ########################## # DD1 WORKAROUNDS |