diff options
| -rw-r--r-- | src/import/chips/p9/initfiles/p9n.mcs.scom.initfile | 56 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C | 71 |
2 files changed, 127 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile index 1cac62958..9eedf66f3 100644 --- a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile +++ b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile @@ -74,6 +74,62 @@ define MCBIST = TGT3; # If referencing Attr from mcbist, add "MCBIST." in front +############################## +# NON BUG SETTINGS ADJUSTMENTS +############################## + +# Enable memory controller hang counters +define def_ENABLE_MCU_TIMEOUTS = 1; + +# Use PB-initiated hang mechanism +espy MC01.PBI01.SCOMFIR.MCTO_SELECT_PB_HANG_PULSE [when=S] { + spyv, expr; + ON, (def_ENABLE_MCU_TIMEOUTS==1); +} +espy MC01.PBI01.SCOMFIR.MCTO_SELECT_LOCAL_HANG_PULSE [when=S] { + spyv; + OFF; +} + +# Enable all CLSTATE hang mechanisms +espy MC01.PBI01.SCOMFIR.MCTO_ENABLE_NONMIRROR_HANG [when=S] { + spyv, expr; + ON, (def_ENABLE_MCU_TIMEOUTS==1); # Hang for all non-mirrored operations +} +espy MC01.PBI01.SCOMFIR.MCTO_ENABLE_APO_HANG [when=S] { + spyv, expr; + ON, (def_ENABLE_MCU_TIMEOUTS==1); # Hang for address protection only CLSTATE machines +} + +# Use RPT_HANG.POLL to trigger PB hang +ispy MC01.PBI01.SCOMFIR.MCTO_RPTHANG_SELECT [when=S && !ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd1 name + spyv; + 0b01; # 0.87381ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_RPT_HANG_SELECT [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd2 name + spyv; + 0b01; # 0.87381ms +} + +# Setup hang compare values +# Count a single pulse and let the secondary counters scale it +ispy MC01.PBI01.SCOMFIR.MCTO_COMP_MASK [when=S && !ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd1 name + spyv, expr; + 1, (def_ENABLE_MCU_TIMEOUTS==1); # 0.87381ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_HANG_COMP [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd2 name + spyv, expr; + 1, (def_ENABLE_MCU_TIMEOUTS==1); # 0.87381ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_TIMEOUT_VALUE [when=S && !ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd1 name + spyv, expr; + 7, (def_ENABLE_MCU_TIMEOUTS==1); # 6.11669ms +} +ispy MC01.PBI01.SCOMFIR.MCTO_CL_TIMEOUT_VALUE [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] { # dd2 name + spyv, expr; + 7, (def_ENABLE_MCU_TIMEOUTS==1); # 6.11669ms +} + ########################## # DD1 WORKAROUNDS diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C index 7d320eee8..f0423935a 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C @@ -40,6 +40,8 @@ constexpr uint64_t literal_0b0001100000000 = 0b0001100000000; constexpr uint64_t literal_1350 = 1350; constexpr uint64_t literal_1000 = 1000; constexpr uint64_t literal_0b0000000000001000 = 0b0000000000001000; +constexpr uint64_t literal_0b01 = 0b01; +constexpr uint64_t literal_7 = 7; fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2, @@ -59,6 +61,7 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0 fapi2::ATTR_MSS_FREQ_Type l_TGT3_ATTR_MSS_FREQ; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_FREQ, TGT3, l_TGT3_ATTR_MSS_FREQ)); uint64_t l_def_mn_freq_ratio = ((literal_1000 * l_TGT3_ATTR_MSS_FREQ) / l_TGT1_ATTR_FREQ_PB_MHZ); + uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1; fapi2::buffer<uint64_t> l_scom_buffer; { FAPI_TRY(fapi2::getScom( TGT0, 0x5010810ull, l_scom_buffer )); @@ -150,6 +153,74 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0 FAPI_TRY(fapi2::putScom(TGT0, 0x5010813ull, l_scom_buffer)); } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501081bull, l_scom_buffer )); + + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_SELECT_PB_HANG_PULSE_ON = 0x1; + l_scom_buffer.insert<0, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_SELECT_PB_HANG_PULSE_ON ); + } + + constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_SELECT_LOCAL_HANG_PULSE_OFF = 0x0; + l_scom_buffer.insert<1, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_SELECT_LOCAL_HANG_PULSE_OFF ); + + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_NONMIRROR_HANG_ON = 0x1; + l_scom_buffer.insert<32, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_NONMIRROR_HANG_ON ); + } + + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_APO_HANG_ON = 0x1; + l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_APO_HANG_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) + { + l_scom_buffer.insert<2, 2, 62, uint64_t>(literal_0b01 ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) ) + { + l_scom_buffer.insert<2, 2, 62, uint64_t>(literal_0b01 ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) + { + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + l_scom_buffer.insert<24, 8, 56, uint64_t>(literal_1 ); + } + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) ) + { + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + l_scom_buffer.insert<24, 8, 56, uint64_t>(literal_1 ); + } + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) + { + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + l_scom_buffer.insert<5, 3, 61, uint64_t>(literal_7 ); + } + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) ) + { + if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1)) + { + l_scom_buffer.insert<5, 3, 61, uint64_t>(literal_7 ); + } + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x501081bull, l_scom_buffer)); + } }; fapi_try_exit: |
