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| author | Dan Crowell <dcrowell@us.ibm.com> | 2019-05-02 10:41:38 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-11 09:35:07 -0500 |
| commit | fa1b266a6293e69f6a67d392d272f90623c28111 (patch) | |
| tree | a10d1a8094bea103f56650cee44d5808ebe3e539 /src/import/chips/p9/common/include | |
| parent | 621e0bac1f53170756cc2dd54e53e6febfd903ba (diff) | |
| download | talos-hostboot-fa1b266a6293e69f6a67d392d272f90623c28111.tar.gz talos-hostboot-fa1b266a6293e69f6a67d392d272f90623c28111.zip | |
Synch up OMI and MCA frequencies
There is an intrinsic link between ATTR_FREQ_MCA_MHZ and
ATTR_FREQ_OMI_MHZ and ATTR_MC_PLL_BUCKET.
-ATTR_MC_PLL_BUCKET will be read-only, platforms will return the
value based on ATTR_FREQ_OMI_MHZ.
-ATTR_FREQ_MCA_MHZ will be read-only (again), platforms will return
the value based on ATTR_FREQ_OMI_MHZ.
-ATTR_FREQ_OMI_MHZ will be writeable, defaulted by mrw/config file,
written by mss_freq_system.
-OMI_PLL_FREQ_LIST was be expanded to include the value of
ATTR_FREQ_MCA_MHZ. Platforms will use ATTR_FREQ_OMI_MHZ (and VCO)
as the key into OMI_PLL_FREQ_LIST to determine the value of
ATTR_MC_PLL_BUCKET and ATTR_FREQ_MCA_MHZ
Change-Id: I17681b8b1ff8ad6b195fc741e20e48ac60ce1c99
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76877
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: Steven B. Janssen <janssens@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76904
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common/include')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_frequency_buckets.H | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/import/chips/p9/common/include/p9_frequency_buckets.H b/src/import/chips/p9/common/include/p9_frequency_buckets.H index 5053eb332..2ac8574d5 100644 --- a/src/import/chips/p9/common/include/p9_frequency_buckets.H +++ b/src/import/chips/p9/common/include/p9_frequency_buckets.H @@ -68,22 +68,25 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = // OMI bucket descriptor struct OmiBucketDescriptor_t { - uint32_t freq; // Frequency in MHz - uint32_t vco; // VCO selector + uint32_t omifreq; // OMI Frequency in MHz + uint32_t vco; // VCO selector + + uint32_t mcafreq; // MCA Frequency in MHz }; //MC PLL frequency in MHz for Axone // index is bucket number // OMI -> ATTR_FREQ_OMI_MHZ // VCO -> ATTR_OMI_PLL_VCO +// MCA -> ATTR_FREQ_MCA_MHZ const OmiBucketDescriptor_t OMI_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = { - // OMI VCO Data rate MCA_FREQ - { 19200, 0 }, // ->DDR4-2400 1200 - { 21330, 0 }, // ->DDR4-2667 1333 - { 23460, 0 }, // ->DDR4-2933 1466 - { 23460, 1 }, // ->DDR4-2933 1466 - { 25600, 1 } // ->DDR4-3200 1600 + // OMI VCO MCA Data rate + { 19200, 0, 1200 }, // ->DDR4-2400 + { 21330, 0, 1333 }, // ->DDR4-2667 + { 23460, 0, 1466 }, // ->DDR4-2933 + { 23460, 1, 1466 }, // ->DDR4-2933 + { 25600, 1, 1600 } // ->DDR4-3200 }; // constant definining number of OBUS PLL frequency options ('buckets') |
