Synch up OMI and MCA frequencies

There is an intrinsic link between ATTR_FREQ_MCA_MHZ and
ATTR_FREQ_OMI_MHZ and ATTR_MC_PLL_BUCKET.
-ATTR_MC_PLL_BUCKET will be read-only, platforms will return the
 value based on ATTR_FREQ_OMI_MHZ.
-ATTR_FREQ_MCA_MHZ will be read-only (again), platforms will return
 the value based on ATTR_FREQ_OMI_MHZ.
-ATTR_FREQ_OMI_MHZ will be writeable, defaulted by mrw/config file,
 written by mss_freq_system.
-OMI_PLL_FREQ_LIST was be expanded to include the value of
 ATTR_FREQ_MCA_MHZ. Platforms will use ATTR_FREQ_OMI_MHZ (and VCO)
 as the key into OMI_PLL_FREQ_LIST to determine the value of
 ATTR_MC_PLL_BUCKET and ATTR_FREQ_MCA_MHZ

Change-Id: I17681b8b1ff8ad6b195fc741e20e48ac60ce1c99
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76877
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: Steven B. Janssen <janssens@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76904
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 27 insertions, 19 deletions

diff --git a/src/import/chips/p9/common/include/p9_frequency_buckets.H b/src/import/chips/p9/common/include/p9_frequency_buckets.H
index 5053eb332..2ac8574d5 100644
--- a/src/import/chips/p9/common/include/p9_frequency_buckets.H
+++ b/src/import/chips/p9/common/include/p9_frequency_buckets.H
@@ -68,22 +68,25 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] =
 // OMI bucket descriptor
 struct OmiBucketDescriptor_t
 {
-    uint32_t freq; // Frequency in MHz
-    uint32_t vco;  // VCO selector
+    uint32_t omifreq; // OMI Frequency in MHz
+    uint32_t vco;     // VCO selector
+
+    uint32_t mcafreq; // MCA Frequency in MHz
 };
 
 //MC PLL frequency in MHz for Axone
 // index is bucket number
 // OMI -> ATTR_FREQ_OMI_MHZ
 // VCO -> ATTR_OMI_PLL_VCO
+// MCA -> ATTR_FREQ_MCA_MHZ
 const OmiBucketDescriptor_t OMI_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] =
 {
-    //  OMI    VCO       Data rate   MCA_FREQ
-    { 19200, 0 }, // ->DDR4-2400   1200
-    { 21330, 0 }, // ->DDR4-2667   1333
-    { 23460, 0 }, // ->DDR4-2933   1466
-    { 23460, 1 }, // ->DDR4-2933   1466
-    { 25600, 1 }  // ->DDR4-3200   1600
+    //  OMI    VCO   MCA          Data rate
+    { 19200,   0,    1200 }, // ->DDR4-2400
+    { 21330,   0,    1333 }, // ->DDR4-2667
+    { 23460,   0,    1466 }, // ->DDR4-2933
+    { 23460,   1,    1466 }, // ->DDR4-2933
+    { 25600,   1,    1600 }  // ->DDR4-3200
 };
 
 // constant definining number of OBUS PLL frequency options ('buckets')
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 4ceceb46e..e9796443b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -50,21 +50,23 @@
   <id>ATTR_FREQ_MCA_MHZ</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>
-    The frequency of the memory controller channel. In synchronous mode,
-    this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set
-    per pair of memory channels if operating in asynchronous mode,
-    but this configuration is not anticipated. This clock drives the MCU queues,
-    and all the associated logic that drives the inputs to the DMI and reads
-    its outputs.
+    The frequency of the memory controller channel.
+    NIMBUS: In synchronous mode, this is equivalent to ATTR_FREQ_PB_MHZ. This
+      may be independently set per pair of memory channels if operating in
+      asynchronous mode, but this configuration is not anticipated.
+    CUMULUS: This clock drives the MCU queues, and all the associated logic
+      that drives the inputs to the DMI and reads its outputs.
+    AXONE: This is tied to the OMI frequency (MCAx16=OMI).
   </description>
   <valueType>uint32</valueType>
   <enum>
-    2000 = 2000,
-    2400 = 2400,
+    1200 = 1200,
     1333 = 1333,
-    1600 = 1600
+    1466 = 1466,
+    1600 = 1600,
+    2000 = 2000,
+    2400 = 2400
   </enum>
-  <writeable/>
   <platInit/>
 </attribute>
 <!-- ********************************************************************** -->
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index 92286ce9a..c77fbcb99 100755
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -753,7 +753,10 @@
 <attribute>
   <id>ATTR_MC_PLL_BUCKET</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
-  <description>MC pll bucket selection in async mode for Cumulus</description>
+  <description>MC pll bucket selection.
+     See MEM_PLL_FREQ_LIST for Cumulus.
+     See OMI_PLL_FREQ_LIST for Axone.
+  </description>
   <valueType>uint8</valueType>
   <platInit/>
 </attribute>