Fix more exp_draminit parameters

Change-Id: I1183b37048b6075bd85276058f123883efb351e9
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79299
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: RYAN P. KING <rpking@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79320
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

3 files changed, 75 insertions, 25 deletions

diff --git a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H
index aab5715b2..206a847e3 100644
--- a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H
+++ b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H
@@ -465,25 +465,43 @@ typedef struct __attribute__((packed)) user_input_msdg
     uint16_t InitPhyVref[MSDG_MAX_PSTATE];
 
     // Enter desired ODT[3:0] value when writing to ranks
-    // OdtWrMapCs[i][3:0] ODT value when writing to rank 0
-    // OdtWrMapCs[i][7:4] ODT value when writing to rank 1
-    // OdtWrMapCs[i][11:8] ODT value when writing to rank 2
-    // OdtWrMapCs[i][15:12] ODT value when writing to rank 3
-    // [0] - ODT value for P0
-    // [1] - ODT value for P1
-    // [2] - ODT value for P2
-    // [3] - ODT value for P3
+    // in normal mode (2 rank)
+    // OdtWrMapCs BIT [1:0] ODT_A/B[1:0] value when writing to rank 0
+    // OdtWrMapCs BIT [5:4] ODT_A/B[1:0] value when writing to rank 1
+    // If EncodedQuadCs = 1
+    // OdtWrMapCs BIT [1:0] ODT_A/B[1:0] value when writing to rank 0
+    // OdtWrMapCs BIT [5:4] ODT_A/B[1:0] value when writing to rank 1
+    // OdtWrMapCs BIT [9:8] ODT_A/B[1:0] value when writing to rank 2
+    // OdtWrMapCs BIT [13:12] ODT_A/B[1:0] value when writing to rank 3
+    // If Rank4Mode = 1
+    // OdtWrMapCs BIT [1:0] ODT_A[1:0] value when writing to rank 0
+    // OdtWrMapCs BIT [3:2] ODT_B[1:0] value when writing to rank 0
+    // OdtWrMapCs BIT [5:4] ODT_A[1:0] value when writing to rank 1
+    // OdtWrMapCs BIT [7:6] ODT_B[1:0] value when writing to rank 1
+    // OdtWrMapCs BIT [9:8] ODT_A[1:0] value when writing to rank 2
+    // OdtWrMapCs BIT [11:10] ODT_B[1:0] value when writing to rank 2
+    // OdtWrMapCs BIT [13:12] ODT_A[1:0] value when writing to rank 3
+    // OdtWrMapCs BIT [15:14] ODT_B[1:0] value when writing to rank 3
     uint16_t OdtWrMapCs[MSDG_MAX_PSTATE];
 
-    // Enter desired ODT[3:0] value when writing to ranks
-    // OdtRdMapCs[i][3:0] ODT value when writing to rank 0
-    // OdtRdMapCs[i][7:4] ODT value when writing to rank 1
-    // OdtRdMapCs[i][11:8] ODT value when writing to rank 2
-    // OdtRdMapCs[i][15:12] ODT value when writing to rank 3
-    // [0] - ODT value for P0
-    // [1] - ODT value for P1
-    // [2] - ODT value for P2
-    // [3] - ODT value for P3
+    // Enter desired ODT[3:0] value when reading from ranks
+    // in normal mode (2 rank)
+    // OdtRdMapCs BIT [1:0] ODT_A/B[1:0] value when reading from rank 0
+    // OdtRdMapCs BIT [5:4] ODT_A/B[1:0] value when reading from rank 1
+    // If EncodedQuadCs = 1
+    // OdtRdMapCs BIT [1:0] ODT_A/B[1:0] value when reading from rank 0
+    // OdtRdMapCs BIT [5:4] ODT_A/B[1:0] value when reading from rank 1
+    // OdtRdMapCs BIT [9:8] ODT_A/B[1:0] value when reading from rank 2
+    // OdtRdMapCs BIT [13:12] ODT_A/B[1:0] value when reading from rank 3
+    // If Rank4Mode = 1
+    // OdtRdMapCs BIT [1:0] ODT_A[1:0] value when reading from rank 0
+    // OdtRdMapCs BIT [3:2] ODT_B[1:0] value when reading from rank 0
+    // OdtRdMapCs BIT [5:4] ODT_A[1:0] value when reading from rank 1
+    // OdtRdMapCs BIT [7:6] ODT_B[1:0] value when reading from rank 1
+    // OdtRdMapCs BIT [9:8] ODT_A[1:0] value when reading from rank 2
+    // OdtRdMapCs BIT [11:10] ODT_B[1:0] value when reading from rank 2
+    // OdtRdMapCs BIT [13:12] ODT_A[1:0] value when reading from rank 3
+    // OdtRdMapCs BIT [15:14] ODT_B[1:0] value when reading from rank 3
     uint16_t OdtRdMapCs[MSDG_MAX_PSTATE];
 
     // Enable geardown mode during training/dfi_bist.
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C
index a0b62b533..cf09e0a45 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C
@@ -129,13 +129,13 @@ fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_t
     static const uint8_t VREF_RANGE_BIT_LEFT_ALGINED = 1;
 
     // Get the data
-    uint8_t l_phy_vref[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0};
+    uint8_t l_vref_dq[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0};
 
     uint8_t l_range = 0;
     uint8_t l_value = 0;
     fapi2::buffer<uint8_t> l_combined_vref;
 
-    FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, l_phy_vref));
+    FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, l_vref_dq));
 
     // Piece together the field
     FAPI_TRY(i_efd_data->wr_vref_dq_range(l_range));
@@ -145,10 +145,10 @@ fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_t
     l_combined_vref.writeBit<VREF_RANGE_BIT_LEFT_ALGINED>(l_range);
 
     // Insert
-    l_phy_vref[i_efd_data->get_rank()] = l_combined_vref;
+    l_vref_dq[i_efd_data->get_rank()] = l_combined_vref;
 
     // Set the attribute
-    FAPI_TRY(mss::attr::set_exp_init_vref_dq(i_target, l_phy_vref));
+    FAPI_TRY(mss::attr::set_exp_init_vref_dq(i_target, l_vref_dq));
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
index fac27601b..e310ee220 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
@@ -134,6 +134,18 @@ enum msdg_enable
 };
 
 ///
+/// @brief defines fields for the ODT RD/WR params
+///
+enum odt_fields
+{
+    FLD_LENGTH = 4,
+    RANK3 = 12,
+    RANK2 = 8,
+    RANK1 = 4,
+    RANK0 = 0,
+};
+
+///
 /// @brief host_fw_command_struct structure setup
 /// @param[in] i_cmd_data_crc the command data CRC
 /// @param[out] o_cmd the command parameters to set
@@ -180,8 +192,8 @@ struct phy_params_t
     uint8_t iv_num_pstate[MAX_DIMM_PER_PORT];
     uint64_t iv_frequency;
     uint8_t iv_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
-    uint8_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
-    uint8_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
+    uint16_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
+    uint16_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
     uint8_t iv_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
     uint8_t iv_atx_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
     uint8_t iv_atx_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
@@ -834,7 +846,17 @@ class phy_params
         ///
         fapi2::ReturnCode set_OdtWrMapCs(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.OdtWrMapCs[0] = iv_params.iv_odt_wr_map_cs[0][0];
+            fapi2::buffer<uint16_t> odt_wr_map_cs_buff;
+
+            // TK - Changes needed for Dual Drop / 4U in the future.
+            // Will likely require ODT RD/WR attribute changes
+            odt_wr_map_cs_buff.insert<odt_fields::RANK3, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][3]);
+            odt_wr_map_cs_buff.insert<odt_fields::RANK2, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][2]);
+            odt_wr_map_cs_buff.insert<odt_fields::RANK1, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][1]);
+            odt_wr_map_cs_buff.insert<odt_fields::RANK0, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][0]);
+
+            odt_wr_map_cs_buff.reverse();
+            io_phy_params.OdtWrMapCs[0] = odt_wr_map_cs_buff;
             return fapi2::FAPI2_RC_SUCCESS;
         }
 
@@ -845,7 +867,17 @@ class phy_params
         ///
         fapi2::ReturnCode set_OdtRdMapCs(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.OdtRdMapCs[0] = iv_params.iv_odt_rd_map_cs[0][0];
+            fapi2::buffer<uint16_t> odt_rd_map_cs_buff;
+
+            // TK - Changes needed for Dual Drop / 4U in the future.
+            // Will likely require ODT RD/WR attribute changes
+            odt_rd_map_cs_buff.insert<odt_fields::RANK3, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][3]);
+            odt_rd_map_cs_buff.insert<odt_fields::RANK2, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][2]);
+            odt_rd_map_cs_buff.insert<odt_fields::RANK1, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][1]);
+            odt_rd_map_cs_buff.insert<odt_fields::RANK0, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][0]);
+
+            odt_rd_map_cs_buff.reverse();
+            io_phy_params.OdtRdMapCs[0] = odt_rd_map_cs_buff;
             return fapi2::FAPI2_RC_SUCCESS;
         }