diff options
7 files changed, 342 insertions, 75 deletions
diff --git a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H index aab5715b2..206a847e3 100644 --- a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H +++ b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H @@ -465,25 +465,43 @@ typedef struct __attribute__((packed)) user_input_msdg uint16_t InitPhyVref[MSDG_MAX_PSTATE]; // Enter desired ODT[3:0] value when writing to ranks - // OdtWrMapCs[i][3:0] ODT value when writing to rank 0 - // OdtWrMapCs[i][7:4] ODT value when writing to rank 1 - // OdtWrMapCs[i][11:8] ODT value when writing to rank 2 - // OdtWrMapCs[i][15:12] ODT value when writing to rank 3 - // [0] - ODT value for P0 - // [1] - ODT value for P1 - // [2] - ODT value for P2 - // [3] - ODT value for P3 + // in normal mode (2 rank) + // OdtWrMapCs BIT [1:0] ODT_A/B[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [5:4] ODT_A/B[1:0] value when writing to rank 1 + // If EncodedQuadCs = 1 + // OdtWrMapCs BIT [1:0] ODT_A/B[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [5:4] ODT_A/B[1:0] value when writing to rank 1 + // OdtWrMapCs BIT [9:8] ODT_A/B[1:0] value when writing to rank 2 + // OdtWrMapCs BIT [13:12] ODT_A/B[1:0] value when writing to rank 3 + // If Rank4Mode = 1 + // OdtWrMapCs BIT [1:0] ODT_A[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [3:2] ODT_B[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [5:4] ODT_A[1:0] value when writing to rank 1 + // OdtWrMapCs BIT [7:6] ODT_B[1:0] value when writing to rank 1 + // OdtWrMapCs BIT [9:8] ODT_A[1:0] value when writing to rank 2 + // OdtWrMapCs BIT [11:10] ODT_B[1:0] value when writing to rank 2 + // OdtWrMapCs BIT [13:12] ODT_A[1:0] value when writing to rank 3 + // OdtWrMapCs BIT [15:14] ODT_B[1:0] value when writing to rank 3 uint16_t OdtWrMapCs[MSDG_MAX_PSTATE]; - // Enter desired ODT[3:0] value when writing to ranks - // OdtRdMapCs[i][3:0] ODT value when writing to rank 0 - // OdtRdMapCs[i][7:4] ODT value when writing to rank 1 - // OdtRdMapCs[i][11:8] ODT value when writing to rank 2 - // OdtRdMapCs[i][15:12] ODT value when writing to rank 3 - // [0] - ODT value for P0 - // [1] - ODT value for P1 - // [2] - ODT value for P2 - // [3] - ODT value for P3 + // Enter desired ODT[3:0] value when reading from ranks + // in normal mode (2 rank) + // OdtRdMapCs BIT [1:0] ODT_A/B[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [5:4] ODT_A/B[1:0] value when reading from rank 1 + // If EncodedQuadCs = 1 + // OdtRdMapCs BIT [1:0] ODT_A/B[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [5:4] ODT_A/B[1:0] value when reading from rank 1 + // OdtRdMapCs BIT [9:8] ODT_A/B[1:0] value when reading from rank 2 + // OdtRdMapCs BIT [13:12] ODT_A/B[1:0] value when reading from rank 3 + // If Rank4Mode = 1 + // OdtRdMapCs BIT [1:0] ODT_A[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [3:2] ODT_B[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [5:4] ODT_A[1:0] value when reading from rank 1 + // OdtRdMapCs BIT [7:6] ODT_B[1:0] value when reading from rank 1 + // OdtRdMapCs BIT [9:8] ODT_A[1:0] value when reading from rank 2 + // OdtRdMapCs BIT [11:10] ODT_B[1:0] value when reading from rank 2 + // OdtRdMapCs BIT [13:12] ODT_A[1:0] value when reading from rank 3 + // OdtRdMapCs BIT [15:14] ODT_B[1:0] value when reading from rank 3 uint16_t OdtRdMapCs[MSDG_MAX_PSTATE]; // Enable geardown mode during training/dfi_bist. diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C index a0b62b533..cf09e0a45 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C @@ -129,13 +129,13 @@ fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_t static const uint8_t VREF_RANGE_BIT_LEFT_ALGINED = 1; // Get the data - uint8_t l_phy_vref[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0}; + uint8_t l_vref_dq[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0}; uint8_t l_range = 0; uint8_t l_value = 0; fapi2::buffer<uint8_t> l_combined_vref; - FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, l_phy_vref)); + FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, l_vref_dq)); // Piece together the field FAPI_TRY(i_efd_data->wr_vref_dq_range(l_range)); @@ -145,10 +145,10 @@ fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_t l_combined_vref.writeBit<VREF_RANGE_BIT_LEFT_ALGINED>(l_range); // Insert - l_phy_vref[i_efd_data->get_rank()] = l_combined_vref; + l_vref_dq[i_efd_data->get_rank()] = l_combined_vref; // Set the attribute - FAPI_TRY(mss::attr::set_exp_init_vref_dq(i_target, l_phy_vref)); + FAPI_TRY(mss::attr::set_exp_init_vref_dq(i_target, l_vref_dq)); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H index fac27601b..e310ee220 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H @@ -134,6 +134,18 @@ enum msdg_enable }; /// +/// @brief defines fields for the ODT RD/WR params +/// +enum odt_fields +{ + FLD_LENGTH = 4, + RANK3 = 12, + RANK2 = 8, + RANK1 = 4, + RANK0 = 0, +}; + +/// /// @brief host_fw_command_struct structure setup /// @param[in] i_cmd_data_crc the command data CRC /// @param[out] o_cmd the command parameters to set @@ -180,8 +192,8 @@ struct phy_params_t uint8_t iv_num_pstate[MAX_DIMM_PER_PORT]; uint64_t iv_frequency; uint8_t iv_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint16_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint16_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_atx_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_atx_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; @@ -834,7 +846,17 @@ class phy_params /// fapi2::ReturnCode set_OdtWrMapCs(user_input_msdg& io_phy_params) const { - io_phy_params.OdtWrMapCs[0] = iv_params.iv_odt_wr_map_cs[0][0]; + fapi2::buffer<uint16_t> odt_wr_map_cs_buff; + + // TK - Changes needed for Dual Drop / 4U in the future. + // Will likely require ODT RD/WR attribute changes + odt_wr_map_cs_buff.insert<odt_fields::RANK3, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][3]); + odt_wr_map_cs_buff.insert<odt_fields::RANK2, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][2]); + odt_wr_map_cs_buff.insert<odt_fields::RANK1, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][1]); + odt_wr_map_cs_buff.insert<odt_fields::RANK0, odt_fields::FLD_LENGTH>(iv_params.iv_odt_wr_map_cs[0][0]); + + odt_wr_map_cs_buff.reverse(); + io_phy_params.OdtWrMapCs[0] = odt_wr_map_cs_buff; return fapi2::FAPI2_RC_SUCCESS; } @@ -845,7 +867,17 @@ class phy_params /// fapi2::ReturnCode set_OdtRdMapCs(user_input_msdg& io_phy_params) const { - io_phy_params.OdtRdMapCs[0] = iv_params.iv_odt_rd_map_cs[0][0]; + fapi2::buffer<uint16_t> odt_rd_map_cs_buff; + + // TK - Changes needed for Dual Drop / 4U in the future. + // Will likely require ODT RD/WR attribute changes + odt_rd_map_cs_buff.insert<odt_fields::RANK3, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][3]); + odt_rd_map_cs_buff.insert<odt_fields::RANK2, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][2]); + odt_rd_map_cs_buff.insert<odt_fields::RANK1, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][1]); + odt_rd_map_cs_buff.insert<odt_fields::RANK0, odt_fields::FLD_LENGTH>(iv_params.iv_odt_rd_map_cs[0][0]); + + odt_rd_map_cs_buff.reverse(); + io_phy_params.OdtRdMapCs[0] = odt_rd_map_cs_buff; return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H index 5de4f0da2..d78a0aa95 100644 --- a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H +++ b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H @@ -595,7 +595,28 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->phy_odt_impedance(o_setting); + uint8_t l_odt_impedance = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > ODT_IMP_MAP = + { + // {key byte, PHY ODT IMP (ohms)} + {0b00000, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS_DISABLE}, + {0b00001, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS_OHM_40}, + {0b00010, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS_OHM_60}, + {0b00011, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS_OHM_80}, + {0b00100, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS_OHM_120}, + {0b00101, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS_OHM_240}, + + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->phy_odt_impedance(l_odt_impedance)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, ODT_IMP_MAP, mss::SET_SI_MC_RCV_IMP_DQ_DQS, l_odt_impedance, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -645,7 +666,41 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->phy_drive_impedance_pull_up(o_setting); + uint8_t l_phy_drv_imp_pu; + + static const std::vector< std::pair<uint16_t, uint16_t> > PHY_DRV_IMP_PU_MAP = + { + // {key byte, DRV IMP PU (ohms)} + {0b000000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_DISABLE}, + {0b000001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_28}, + {0b000010, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_30}, + {0b000011, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_32}, + {0b000100, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_34}, + {0b000101, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_36}, + {0b000110, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_40}, + {0b000111, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_43}, + {0b001000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_48}, + {0b001001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_53}, + {0b001010, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_60}, + {0b001011, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_68}, + {0b001100, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_80}, + {0b001101, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_96}, + {0b001110, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_120}, + {0b001111, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_160}, + {0b010000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_240}, + {0b010001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP_OHM_480}, + + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->phy_drive_impedance_pull_up(l_phy_drv_imp_pu)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, PHY_DRV_IMP_PU_MAP, mss::SET_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, + static_cast<uint16_t>(l_phy_drv_imp_pu), o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -695,7 +750,41 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->phy_drive_impedance_pull_down(o_setting); + uint8_t l_phy_drv_imp_pd = 0; + + static const std::vector< std::pair<uint16_t, uint16_t> > PHY_DRV_IMP_PD_MAP = + { + // {key byte, DRV IMP PD (ohms)} + {0b000000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_DISABLE}, + {0b000001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_28}, + {0b000010, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_30}, + {0b000011, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_32}, + {0b000100, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_34}, + {0b000101, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_36}, + {0b000110, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_40}, + {0b000111, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_43}, + {0b001000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_48}, + {0b001001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_53}, + {0b001010, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_60}, + {0b001011, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_68}, + {0b001100, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_80}, + {0b001101, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_96}, + {0b001110, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_120}, + {0b001111, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_160}, + {0b010000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_240}, + {0b010001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN_OHM_480}, + + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->phy_drive_impedance_pull_down(l_phy_drv_imp_pd)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, PHY_DRV_IMP_PD_MAP, mss::SET_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, + static_cast<uint16_t>(l_phy_drv_imp_pd), o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -796,7 +885,29 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->atx_impedance(o_setting); + uint8_t l_atx_impedance = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > ATX_IMP_MAP = + { + // {key byte, ATX IMP (ohm)} + {0b0000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_DISABLE}, + {0b0001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_OHM_20}, + {0b0010, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_OHM_24}, + {0b0011, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_OHM_30}, + {0b0100, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_OHM_40}, + {0b0101, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_OHM_60}, + {0b0110, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR_OHM_120}, + + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->atx_impedance(l_atx_impedance)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, ATX_IMP_MAP, mss::SET_SI_MC_DRV_IMP_CMD_ADDR, l_atx_impedance, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -896,7 +1007,29 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->ck_impedance(o_setting); + uint8_t l_ck_impedance = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > CK_IMP_MAP = + { + // {key byte, CK IMP (ohm)} + {0b0000, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_DISABLE}, + {0b0001, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_OHM_20}, + {0b0010, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_OHM_24}, + {0b0011, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_OHM_30}, + {0b0100, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_OHM_40}, + {0b0101, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_OHM_60}, + {0b0110, fapi2::ENUM_ATTR_MEM_SI_MC_DRV_IMP_CLK_OHM_120}, + + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->ck_impedance(l_ck_impedance)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, CK_IMP_MAP, mss::SET_SI_MC_DRV_IMP_CLK, l_ck_impedance, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -996,7 +1129,29 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->alert_odt_impedance(o_setting); + uint8_t l_alert_odt_imp = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > ALERT_ODT_IMP_MAP = + { + // {key byte, ALERT ODT IMP (ohms)} + {0b0000, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_DISABLE}, + {0b0001, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_OHM_40}, + {0b0010, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_OHM_48}, + {0b0011, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_OHM_60}, + {0b0100, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_OHM_80}, + {0b0101, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_OHM_120}, + {0b0110, fapi2::ENUM_ATTR_MEM_SI_MC_RCV_IMP_ALERT_N_OHM_240}, + + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->alert_odt_impedance(l_alert_odt_imp)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, ALERT_ODT_IMP_MAP, mss::SET_SI_MC_RCV_IMP_ALERT_N, l_alert_odt_imp, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -1046,7 +1201,27 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->dram_rtt_nom(o_setting); + uint8_t l_rtt_nom = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > RTT_NOM_MAP = + { + {0b0000, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_DISABLE}, + {0b0001, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_OHM34}, + {0b0010, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_OHM40}, + {0b0011, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_OHM60}, + {0b0100, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_OHM80}, + {0b0101, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_OHM120}, + {0b0110, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_NOM_OHM240}, + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->dram_rtt_nom(l_rtt_nom)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, RTT_NOM_MAP, mss::SET_SI_DRAM_RTT_NOM, l_rtt_nom, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -1096,7 +1271,24 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->dram_rtt_wr(o_setting); + uint8_t l_rtt_wr = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > RTT_WR_MAP = + { + {0b0000, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_WR_DISABLE}, + {0b0001, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_WR_OHM80}, + {0b0010, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_WR_OHM120}, + {0b0011, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_WR_OHM240}, + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->dram_rtt_wr(l_rtt_wr)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, RTT_WR_MAP, mss::SET_SI_DRAM_RTT_WR, l_rtt_wr, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -1146,7 +1338,29 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->dram_rtt_park(o_setting); + uint8_t l_rtt_park = 0; + + static const std::vector< std::pair<uint8_t, uint8_t> > RTT_PARK_MAP = + { + // {key byte, RTT PARK (ohms)} + {0b0000, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_DISABLE}, + {0b0001, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM34}, + {0b0010, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM40}, + {0b0011, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM48}, + {0b0100, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM60}, + {0b0101, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM80}, + {0b0110, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM120}, + {0b0111, fapi2::ENUM_ATTR_MEM_SI_DRAM_RTT_PARK_OHM240}, + // All others reserved + }; + const auto l_ocmb = i_efd_data->get_ocmb_target(); + + FAPI_TRY(i_efd_data->dram_rtt_park(l_rtt_park)); + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, RTT_PARK_MAP, mss::SET_SI_DRAM_RTT_PARK, l_rtt_park, o_setting)); + + fapi_try_exit: + return fapi2::current_err; } }; @@ -1299,7 +1513,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> { static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_DIC_MAP = { - // {key byte, capacity in GBs} + // {key byte, DRAM DIC (ohms)} {0, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_DISABLE}, {1, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_OHM34}, {2, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_OHM48}, @@ -1364,7 +1578,6 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR> static fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - fapi2::buffer<uint8_t> l_buffer; uint8_t l_value = 0; switch(i_efd_data->get_rank()) @@ -1735,7 +1948,7 @@ struct attrEngineTraits<attr_engine_derived_fields, HEIGHT_3DS> static const std::vector< std::pair<uint16_t, uint16_t> > HEIGHT_3DS_MAP = { - // {key byte, device width (bits)} + // {key byte, 3DS HEIGHT} {1, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_PLANAR}, {2, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H2}, {4, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H4}, diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index ecc9af5ff..6051f7d39 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -3724,20 +3724,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint16_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and /// Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_down(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) + uint16_t (&o_array)[4]) { - uint8_t l_value[2][4] = {}; + uint16_t l_value[2][4] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -3749,19 +3749,19 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint16_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and /// Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_down(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) + uint16_t (&o_array)[2][4]) { - uint8_t l_value[2][4] = {}; + uint16_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -3773,20 +3773,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint16_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data /// Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_up(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) + uint16_t (&o_array)[4]) { - uint8_t l_value[2][4] = {}; + uint16_t l_value[2][4] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -3798,19 +3798,19 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint16_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data /// Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_up(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) + uint16_t (&o_array)[2][4]) { - uint8_t l_value[2][4] = {}; + uint16_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H index 1acdc554d..447e661dc 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H @@ -294,11 +294,11 @@ class readerTraits { public: - static constexpr size_t COMPARISON_VAL = 0x00; + static constexpr size_t COMPARISON_VAL = 0x0F; static constexpr const char* FIELD_STR = "PHY Slew Rate DQ_DQS"; template <typename T> - using COMPARISON_OP = std::equal_to<T>; + using COMPARISON_OP = std::less_equal<T>; }; /// @@ -332,11 +332,11 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS { public: - static constexpr size_t COMPARISON_VAL = 0x00; + static constexpr size_t COMPARISON_VAL = 0x0E; static constexpr const char* FIELD_STR = "ATX Slew rate"; template <typename T> - using COMPARISON_OP = std::equal_to<T>; + using COMPARISON_OP = std::less_equal<T>; }; /// @@ -370,11 +370,11 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS { public: - static constexpr size_t COMPARISON_VAL = 0x00; + static constexpr size_t COMPARISON_VAL = 0x0E; static constexpr const char* FIELD_STR = "CK Slew rate"; template <typename T> - using COMPARISON_OP = std::equal_to<T>; + using COMPARISON_OP = std::less_equal<T>; }; /// @@ -408,11 +408,11 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS { public: - static constexpr size_t COMPARISON_VAL = 0x00; + static constexpr size_t COMPARISON_VAL = 0x07; static constexpr const char* FIELD_STR = "DRAM RTT Nom"; template <typename T> - using COMPARISON_OP = std::equal_to<T>; + using COMPARISON_OP = std::less_equal<T>; }; /// @@ -503,11 +503,11 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS { public: - static constexpr size_t COMPARISON_VAL = 0x00; + static constexpr size_t COMPARISON_VAL = 0x04; static constexpr const char* FIELD_STR = "DRAM RTT WR"; template <typename T> - using COMPARISON_OP = std::equal_to<T>; + using COMPARISON_OP = std::less_equal<T>; }; /// @@ -598,11 +598,11 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS { public: - static constexpr size_t COMPARISON_VAL = 0x00; + static constexpr size_t COMPARISON_VAL = 0x07; static constexpr const char* FIELD_STR = "DRAM RTT Park"; template <typename T> - using COMPARISON_OP = std::equal_to<T>; + using COMPARISON_OP = std::less_equal<T>; }; /// diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index d8410a5a0..38eccdbe3 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -140,7 +140,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> + <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_dram_rtt_nom</mssAccessorName> <array>2 4</array> @@ -172,7 +172,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0, HIGHZ = 1, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> + <enum>DISABLE = 0, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_dram_rtt_wr</mssAccessorName> <array>2 4</array> @@ -249,7 +249,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, OHM_20 = 20, OHM_24 = 24, OHM_30 = 30, OHM_40 = 40, OHM_60 = 60, OHM_120 = 120</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_clk</mssAccessorName> <array>2 4</array> @@ -265,7 +265,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, OHM_20 = 20, OHM_24 = 24, OHM_30 = 30, OHM_40 = 40, OHM_60 = 60, OHM_120 = 120</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cmd_addr</mssAccessorName> <array>2 4</array> @@ -311,9 +311,11 @@ Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> - <valueType>uint8</valueType> + <valueType>uint16</valueType> <writeable/> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, OHM_28 = 28, OHM_30 = 30, OHM_32 = 32, OHM_34 = 34, OHM_36 = 36, OHM_40 = 40, OHM_43 = 43, + OHM_48 = 48, OHM_53 = 53, OHM_60 = 60, OHM_68 = 68, OHM_80 = 80, OHM_96 = 96, OHM_120 = 120, OHM_160 = 160, + OHM_240 = 240, OHM_480 = 480</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_dq_dqs_pull_down</mssAccessorName> <array>2 4</array> @@ -327,9 +329,11 @@ Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> - <valueType>uint8</valueType> + <valueType>uint16</valueType> <writeable/> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, OHM_28 = 28, OHM_30 = 30, OHM_32 = 32, OHM_34 = 34, OHM_36 = 36, OHM_40 = 40, OHM_43 = 43, + OHM_48 = 48, OHM_53 = 53, OHM_60 = 60, OHM_68 = 68, OHM_80 = 80, OHM_96 = 96, OHM_120 = 120, OHM_160 = 160, + OHM_240 = 240, OHM_480 = 480</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_dq_dqs_pull_up</mssAccessorName> <array>2 4</array> @@ -424,7 +428,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, OHM_40 = 40, OHM_48 = 48, OHM_60 = 60, OHM_80 = 80, OHM_120 = 120, OHM_240 = 240</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_rcv_imp_alert_n</mssAccessorName> <array>2 4</array> @@ -440,7 +444,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0</enum> + <enum>DISABLE = 0, OHM_40 = 40, OHM_60 = 60, OHM_80 = 80, OHM_120 = 120, OHM_240 = 240</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_rcv_imp_dq_dqs</mssAccessorName> <array>2 4</array> |
