Adds explorer CCS specialization

Change-Id: I859140b161f6a465d68883021465318b328d4a0d
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77260
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77273
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>

8 files changed, 683 insertions, 2 deletions

diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C
new file mode 100644
index 000000000..26855282e
--- /dev/null
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C
@@ -0,0 +1,166 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file ccs_explorer.C
+/// @brief Run and manage the CCS engine
+///
+// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+
+#include <lib/shared/exp_defaults.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <generic/memory/lib/ccs/ccs.H>
+#include <lib/ccs/ccs_explorer.H>
+#include <lib/utils/mss_exp_conversions.H>
+
+// Generates linkage
+constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::EXPLORER>::CS_N[];
+constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::EXPLORER>::CS_ND[];
+
+namespace mss
+{
+namespace ccs
+{
+
+///
+/// @brief Cleans up from a CCS execution - multiple ports - EXPLORER specialization
+/// @param[in] i_program the vector of instructions
+/// @param[in] i_ports the vector of ports
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+template<>
+fapi2::ReturnCode cleanup_from_execute<fapi2::TARGET_TYPE_MEM_PORT, mss::mc_type::EXPLORER>
+(const ccs::program& i_program,
+ const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> >& i_ports)
+{
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Determine the CCS failure type
+/// @param[in] i_target OCMB target
+/// @param[in] i_type the failure type
+/// @param[in] i_port The port the CCS instruction is training
+/// @return ReturnCode associated with the fail.
+/// @note FFDC is handled here, caller doesn't need to do it
+///
+template<>
+fapi2::ReturnCode fail_type( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+                             const uint64_t i_type,
+                             const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port )
+{
+    typedef ccsTraits<mss::mc_type::EXPLORER> TT;
+
+    // Including the PORT_TARGET here and below at CAL_TIMEOUT since these problems likely lie at the MCA level
+    // So we disable the PORT and hopefully that's it
+    // If the problem lies with the MCBIST, it'll just have to loop
+    FAPI_ASSERT(TT::STAT_READ_MISCOMPARE != i_type,
+                fapi2::MSS_EXP_CCS_READ_MISCOMPARE()
+                .set_MC_TARGET(i_target)
+                .set_FAIL_TYPE(i_type)
+                .set_PORT_TARGET(i_port),
+                "%s CCS FAIL Read Miscompare", mss::c_str(i_port));
+
+    // This error is likely due to a bad CCS engine/ MCBIST
+    FAPI_ASSERT(TT::STAT_UE_SUE != i_type,
+                fapi2::MSS_EXP_CCS_UE_SUE()
+                .set_FAIL_TYPE(i_type)
+                .set_MC_TARGET(i_target),
+                "%s CCS FAIL UE or SUE Error", mss::c_str(i_target));
+
+    // Problem with the CCS engine
+    FAPI_ASSERT(TT::STAT_HUNG != i_type,
+                fapi2::MSS_EXP_CCS_HUNG().set_MC_TARGET(i_target),
+                "%s CCS appears hung", mss::c_str(i_target));
+fapi_try_exit:
+    // Due to the PRD update, we need to check for FIR's
+    // If any FIR's have lit up, this CCS fail could have been caused by the FIR
+    // So, let PRD retrigger this step to see if we can resolve the issue
+    return mss::check::fir_or_pll_fail<mss::mc_type::EXPLORER>(i_target, fapi2::current_err);
+}
+
+///
+/// @brief EXP specialization for modeq_copy_cke_to_spare_cke
+/// @param[in] fapi2::Target<TARGET_TYPE_OCMB_CHIP>& the target to effect
+/// @param[in,out] the buffer representing the mode register
+/// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports
+/// @note no-op for p9n
+///
+template<>
+void copy_cke_to_spare_cke<fapi2::TARGET_TYPE_OCMB_CHIP>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&,
+        fapi2::buffer<uint64_t>&, states )
+{
+    return;
+}
+
+///
+/// @brief Updates the initial delays based upon the total delays passed in - EXP specialization
+/// @param[in] i_target the target type on which to operate
+/// @param[in] i_delay the calculated delays from CCS
+/// @param[in,out] io_program the program for which to update the delays
+/// @return FAPI2_RC_SUCCSS iff ok
+///
+template<>
+fapi2::ReturnCode update_initial_delays<fapi2::TARGET_TYPE_OCMB_CHIP, mss::mc_type::EXPLORER>
+( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+  const uint64_t i_delay,
+  ccs::program& io_program)
+{
+    // Check our program for any delays. If there isn't a iv_initial_delay configured, then
+    // we use the delay we just summed from the instructions.
+    if (io_program.iv_poll.iv_initial_delay == 0)
+    {
+        io_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, i_delay);
+    }
+
+    if (io_program.iv_poll.iv_initial_sim_delay == 0)
+    {
+        io_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(i_delay);
+    }
+
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Select the port(s) to be used by the CCS - EXPLORER specialization
+/// @param[in] i_target the target to effect
+/// @param[in] i_ports the buffer representing the ports
+///
+template<>
+fapi2::ReturnCode select_ports<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+        uint64_t i_ports)
+{
+    // No broadcast mode, only one port, so no port selection
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+} // namespace ccs
+} // namespace mss
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H
new file mode 100644
index 000000000..e02292508
--- /dev/null
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file ccs_explorer.H
+/// @brief Run and manage the CCS engine
+///
+// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#ifndef _MSS_CCS_EXPLORER_H_
+#define _MSS_CCS_EXPLORER_H_
+
+#include <fapi2.H>
+#include <lib/ccs/ccs_traits_explorer.H>
+#include <generic/memory/lib/ccs/ccs.H>
+
+namespace mss
+{
+namespace ccs
+{
+
+// This file ties the two needed header files together
+
+} // namespace ccs
+} // namespace mss
+
+#endif
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H
new file mode 100644
index 000000000..965b98057
--- /dev/null
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H
@@ -0,0 +1,269 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file ccs_traits_nimbus.H
+/// @brief Run and manage the CCS engine
+///
+// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: HB:FSP
+
+#ifndef _MSS_CCS_TRAITS_EXP_H_
+#define _MSS_CCS_TRAITS_EXP_H_
+
+#include <fapi2.H>
+#include <explorer_scom_addresses.H>
+#include <explorer_scom_addresses_fld.H>
+#include <lib/shared/exp_consts.H>
+#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
+#include <generic/memory/lib/mss_generic_attribute_getters.H>
+#include <generic/memory/lib/ccs/ccs_traits.H>
+
+///
+/// @class ccsTraits
+/// @brief Explorer CCS Engine traits
+///
+template<>
+class ccsTraits<mss::mc_type::EXPLORER>
+{
+    public:
+        static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT;
+        static constexpr uint64_t MODEQ_REG = EXPLR_MCBIST_CCS_MODEQ;
+        static constexpr uint64_t MCB_CNTL_REG = EXPLR_MCBIST_MCB_CNTLQ;
+        static constexpr uint64_t CNTLQ_REG = EXPLR_MCBIST_CCS_CNTLQ;
+        static constexpr uint64_t STATQ_REG = EXPLR_MCBIST_CCS_STATQ;
+
+        static constexpr uint64_t PORTS_PER_MC_TARGET = mss::exp::MAX_PORT_PER_OCMB;
+        static constexpr uint64_t CCS_MAX_DIMM_PER_PORT = mss::exp::MAX_DIMM_PER_PORT;
+        static constexpr uint64_t CCS_MAX_MRANK_PER_PORT = mss::exp::MAX_MRANK_PER_PORT;
+        static constexpr uint64_t CCS_MAX_RANK_PER_DIMM = mss::exp::MAX_RANK_PER_DIMM;
+        static constexpr uint64_t CCS_MAX_RANKS_DIMM1 = mss::exp::MAX_RANKS_DIMM1;
+
+        static constexpr uint64_t NTTM_READ_DELAY = 0x40;
+        static constexpr uint64_t NTTM_MODE_FORCE_READ = 33;
+
+
+        // Command Pass Disable Delay Time for Explorer - really a JEDEC timing
+        static constexpr uint64_t TIMING_TCPDED = 4;
+
+        enum
+        {
+            // Non address values that are needed for helper functions
+
+            // ODT values used for beautification
+            // Attribute locations
+            ATTR_ODT_DIMM0_R0 = 0,
+            ATTR_ODT_DIMM0_R1 = 1,
+            ATTR_ODT_DIMM1_R0 = 4,
+            ATTR_ODT_DIMM1_R1 = 5,
+
+            // Right justified output - makes it so we can use insertFromRight
+            CCS_ODT_DIMM0_R0 = 4,
+            CCS_ODT_DIMM0_R1 = 5,
+            CCS_ODT_DIMM1_R0 = 6,
+            CCS_ODT_DIMM1_R1 = 7,
+
+            // Default ODT cycle length is 5 - one for the preamble and 4 for the data
+            DEFAULT_ODT_CYCLE_LEN = 5,
+
+            // CCS MODEQ
+            STOP_ON_ERR = EXPLR_MCBIST_CCS_MODEQ_STOP_ON_ERR,
+            UE_DISABLE = EXPLR_MCBIST_CCS_MODEQ_UE_DISABLE,
+            DATA_COMPARE_BURST_SEL = EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL,
+            DATA_COMPARE_BURST_SEL_LEN = EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN,
+            DDR_CAL_TIMEOUT_CNT = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT,
+            DDR_CAL_TIMEOUT_CNT_LEN = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN,
+            CFG_PARITY_AFTER_CMD = EXPLR_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD,
+            COPY_CKE_TO_SPARE_CKE = EXPLR_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE,
+            DISABLE_ECC_ARRAY_CHK = EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK,
+            DISABLE_ECC_ARRAY_CORRECTION = EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION,
+            CFG_DGEN_FIXED_MODE = EXPLR_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE,
+            DDR_CAL_TIMEOUT_CNT_MULT = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT,
+            DDR_CAL_TIMEOUT_CNT_MULT_LEN = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN,
+            IDLE_PAT_ADDRESS_0_13 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13,
+            IDLE_PAT_ADDRESS_0_13_LEN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN,
+            IDLE_PAT_ADDRESS_17 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17,
+            IDLE_PAT_BANK_GROUP_1 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1,
+            IDLE_PAT_BANK_0_1 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1,
+            IDLE_PAT_BANK_0_1_LEN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN,
+            IDLE_PAT_BANK_GROUP_0 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0,
+            IDLE_PAT_ACTN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN,
+            IDLE_PAT_ADDRESS_16 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16,
+            IDLE_PAT_ADDRESS_15 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15,
+            IDLE_PAT_ADDRESS_14 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14,
+            NTTM_MODE = EXPLR_MCBIST_CCS_MODEQ_NTTM_MODE,
+            NTTM_RW_DATA_DLY = EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY,
+            NTTM_RW_DATA_DLY_LEN = EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN,
+            IDLE_PAT_BANK_2 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2,
+            DDR_PARITY_ENABLE = EXPLR_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE,
+            IDLE_PAT_PARITY = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY,
+
+            // CCS CNTL
+            CCS_START = EXPLR_MCBIST_CCS_CNTLQ_START,
+            CCS_STOP = EXPLR_MCBIST_CCS_CNTLQ_STOP,
+
+            // CCS STATQ
+            CCS_IN_PROGRESS = EXPLR_MCBIST_CCS_STATQ_IP,
+
+            // ARR0
+            ARR0_DDR_ADDRESS_0_13 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13,
+            ARR0_DDR_ADDRESS_0_13_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN,
+            ARR0_DDR_ADDRESS_0_9 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, // Useful for rd/wr cmds
+            ARR0_DDR_ADDRESS_0_9_LEN = 10, // CA bits are 9:0, total length of 10
+            ARR0_DDR_ADDRESS_10 = 10, // ADR10 is the 10th bit from the left in Nimbus ARR0
+            ARR0_DDR_ADDRESS_17 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17,
+            ARR0_DDR_BANK_GROUP_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1,
+            ARR0_DDR_RESETN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_RESETN,
+            ARR0_DDR_BANK_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1,
+            ARR0_DDR_BANK_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN,
+            ARR0_DDR_BANK_GROUP_0 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0,
+            ARR0_DDR_ACTN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ACTN,
+            ARR0_DDR_ADDRESS_16 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16,
+            ARR0_DDR_ADDRESS_15 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15,
+            ARR0_DDR_ADDRESS_14 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14,
+            ARR0_DDR_CKE = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE,
+            ARR0_DDR_CKE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN,
+            ARR0_DDR_CSN_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1,
+            ARR0_DDR_CSN_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN,
+            ARR0_DDR_CID_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1,
+            ARR0_DDR_CID_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN,
+            ARR0_DDR_CSN_2_3 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3,
+            ARR0_DDR_CSN_2_3_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN,
+            ARR0_DDR_CID_2 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_2,
+            ARR0_DDR_ODT = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT,
+            ARR0_DDR_ODT_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN,
+            ARR0_DDR_CAL_TYPE = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE,
+            ARR0_DDR_CAL_TYPE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN,
+            ARR0_DDR_PARITY = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_PARITY,
+            ARR0_DDR_BANK_2 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2,
+            ARR0_LOOP_BREAK_MODE = EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE,
+            ARR0_LOOP_BREAK_MODE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN,
+
+            // ARR1
+            ARR1_IDLES = EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES,
+            ARR1_IDLES_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES_LEN,
+            ARR1_REPEAT_CMD_CNT = EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT,
+            ARR1_REPEAT_CMD_CNT_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN,
+            ARR1_READ_OR_WRITE_DATA = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA,
+            ARR1_READ_OR_WRITE_DATA_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN,
+            ARR1_READ_COMPARE_REQUIRED = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED,
+            ARR1_DDR_CAL_RANK = EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK,
+            ARR1_DDR_CAL_RANK_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN,
+            ARR1_DDR_CALIBRATION_ENABLE = EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE,
+            ARR1_END = EXPLR_MCBIST_CCS_INST_ARR1_00_END,
+            ARR1_GOTO_CMD = EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD,
+            ARR1_GOTO_CMD_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN,
+
+            // CCS array constants
+            CCS_ARRAY_LEN = 32,
+            CCS_ARR0_START = EXPLR_MCBIST_CCS_INST_ARR0_00,
+            CCS_ARR1_START = EXPLR_MCBIST_CCS_INST_ARR1_00,
+        };
+
+        ///
+        /// @brief Enums for CCS return codes
+        ///
+        enum
+        {
+            // Success is defined as done-bit set, no others.
+            STAT_QUERY_SUCCESS   = 0x4000000000000000,
+
+            // Bit positions 3:5
+            STAT_ERR_MASK        = 0x1800000000000000,
+            STAT_READ_MISCOMPARE = 0x1000000000000000,
+            STAT_UE_SUE          = 0x0800000000000000,
+
+            // If the fail type isn't one of these, we're hung
+            STAT_HUNG = 0x0ull,
+        };
+
+
+        // CSN Regular Settings
+        static constexpr std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] =
+        {
+            // CS0 L, CS1 H, CID0-> L => Rank 0
+            { 0b01, 0b00 },
+
+            // CS0 L, CS1 H, CID0-> H => Rank 1
+            { 0b01, 0b11 },
+
+            // CS0 H, CS1 L, CID0-> L => Rank 2
+            { 0b10, 0b00 },
+
+            // CS0 H, CS1 L, CID0-> H => Rank 3
+            { 0b10, 0b11 },
+        };
+
+
+        // CSN Setup for Dual Direct Mode
+        // For DIMM0 .first is the CSN_0_1 setting, .second is the CSN_2_3 setting.
+        // For DIMM1 .first is the CSN_2_3 setting, .second is the CSN_0_1 setting.
+        static constexpr std::pair<uint64_t, uint64_t> CS_ND[mss::MAX_RANK_PER_DIMM] =
+        {
+            // CS0 L CS1 H => CS2 => H CS3 => H Rank 0
+            { 0b01, 0b11 },
+
+            // CS0 H CS1 L => CS2 => H CS3 => H Rank 1
+            { 0b10, 0b11 },
+
+            // CS0 H CS1 H => CS2 => L CS3 => H Rank 2
+            { 0b11, 0b01 },
+
+            // CS0 H CS1 H => CS2 => H CS3 => L Rank 3
+            { 0b11, 0b10 },
+        };
+
+        ///
+        /// @brief Gets the attribute for checking our rank configuration
+        /// @param[in] i_target the port target on which to operate
+        /// @param[out] o_ranks the rank data
+        /// @return SUCCESS iff the code executes successfully
+        ///
+        static fapi2::ReturnCode get_rank_config_attr(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
+                uint8_t (&o_array)[2])
+        {
+            return mss::attr::get_num_master_ranks_per_dimm(i_target, o_array);
+        }
+
+        ///
+        /// @brief Gets the attribute for checking our rank configuration
+        /// @param[in] i_target the port target on which to operate
+        /// @param[out] o_ranks the rank data
+        /// @return The fully setup nimbus error
+        ///
+        static fapi2::EXP_CCS_HUNG_TRYING_TO_STOP setup_trying_to_stop_err(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&
+                i_target)
+        {
+            return fapi2::EXP_CCS_HUNG_TRYING_TO_STOP().set_MC_TARGET(i_target);
+        }
+
+        // Lab values
+        static constexpr uint64_t LAB_MRS_CMD = 0x000008F000000000;
+};
+
+#endif
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H
index efbec9b09..cf990c94d 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H
@@ -102,9 +102,11 @@ class portTraits< mss::mc_type::EXPLORER >
             DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE,
             RCD_RECOVERY_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY,
 
+            RECR_ENABLE_UE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW,
             RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION,
             RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION,
             RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN,
+
             DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY,
             DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN,
             DSM0Q_WRDONE_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY,
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H
index 7a56d4cc6..70830f58f 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H
@@ -126,6 +126,13 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP>
 
         // All of the pattern registers are calculated off of this base
         static constexpr uint64_t PATTERN0_REG = EXPLR_MCBIST_MCBFD0Q;
+        static constexpr uint64_t PATTERN1_REG = EXPLR_MCBIST_MCBFD1Q;
+        static constexpr uint64_t PATTERN2_REG = EXPLR_MCBIST_MCBFD2Q;
+        static constexpr uint64_t PATTERN3_REG = EXPLR_MCBIST_MCBFD3Q;
+        static constexpr uint64_t PATTERN4_REG = EXPLR_MCBIST_MCBFD4Q;
+        static constexpr uint64_t PATTERN5_REG = EXPLR_MCBIST_MCBFD5Q;
+        static constexpr uint64_t PATTERN6_REG = EXPLR_MCBIST_MCBFD6Q;
+        static constexpr uint64_t PATTERN7_REG = EXPLR_MCBIST_MCBFD7Q;
 
         static constexpr uint64_t DATA_ROTATE_CNFG_REG = EXPLR_MCBIST_MCBDRCRQ;
         static constexpr uint64_t DATA_ROTATE_SEED_REG = EXPLR_MCBIST_MCBDRSRQ;
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H
index 4d7a7d4cc..0678d94af 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H
@@ -122,6 +122,8 @@ enum sizes
     MAX_DIMM_PER_PORT = 2,
     MAX_RANK_PER_DIMM = 4,
     MAX_BITS_PER_PORT = 80,
+    MAX_RANKS_DIMM1 = 2,
+    MAX_MRANK_PER_PORT = MAX_DIMM_PER_PORT * MAX_RANK_PER_DIMM,
 };
 
 ///
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H
index 42648c785..d4bfd3387 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H
@@ -42,9 +42,9 @@
 namespace mss
 {
 
-constexpr fapi2::TargetType DEFAULT_MEM_PORT_TARGET = fapi2::TARGET_TYPE_MEM_PORT;
-
 constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::EXPLORER;
+constexpr fapi2::TargetType DEFAULT_MC_TARGET = fapi2::TARGET_TYPE_OCMB_CHIP;
+constexpr fapi2::TargetType DEFAULT_MEM_PORT_TARGET = fapi2::TARGET_TYPE_MEM_PORT;
 
 } // ns mss
 
diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml
index 25ca0fbfc..c6a941e2d 100644
--- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml
+++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml
@@ -216,4 +216,186 @@
     </deconfigure>
   </hwpError>
 
+  <registerFfdc>
+    <id>REG_FFDC_EXP_CCS_FAILURE</id>
+    <scomRegister>EXPLR_MCBIST_CCS_MODEQ</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_STATQ</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_CNTLQ</scomRegister>
+    <scomRegister>EXPLR_MCBIST_MCBMCATQ</scomRegister>
+
+    <!-- Instructions -->
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_00</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_01</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_02</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_03</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_04</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_05</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_06</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_07</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_08</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_09</scomRegister>
+
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_10</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_11</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_12</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_13</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_14</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_15</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_16</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_17</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_18</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_19</scomRegister>
+
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_20</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_21</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_22</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_23</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_24</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_25</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_26</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_27</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_28</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_29</scomRegister>
+
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_30</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_31</scomRegister>
+
+    <!-- Control array -->
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_00</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_01</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_02</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_03</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_04</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_05</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_06</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_07</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_08</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_09</scomRegister>
+
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_10</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_11</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_12</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_13</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_14</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_15</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_16</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_17</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_18</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_19</scomRegister>
+
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_20</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_21</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_22</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_23</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_24</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_25</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_26</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_27</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_28</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_29</scomRegister>
+
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_30</scomRegister>
+    <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_31</scomRegister>
+
+    <!-- to get the CCS state machine hung state -->
+    <scomRegister>EXPLR_MCBIST_MBA_MCBERRPT0Q</scomRegister>
+    <scomRegister>EXPLR_MCBIST_MBA_MCBERRPT1Q</scomRegister>
+  </registerFfdc>
+
+  <hwpError>
+    <rc>RC_MSS_EXP_CCS_READ_MISCOMPARE</rc>
+    <description>
+        CCS reports a read miscompare.
+    </description>
+    <ffdc>FAIL_TYPE</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_EXP_CCS_FAILURE</id>
+      <target>MC_TARGET</target>
+      <targetType>TARGET_TYPE_OCMB_CHIP</targetType>
+    </collectRegisterFfdc>
+    <callout>
+      <target>PORT_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>PORT_TARGET</target>
+    </deconfigure>
+    <gard>
+        <target>PORT_TARGET</target>
+    </gard>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_EXP_CCS_UE_SUE</rc>
+    <description>
+        CCS reports a UE or SUE in the CCS program array
+        Chould be an indicator of corruption in the CCS program
+    </description>
+    <ffdc>FAIL_TYPE</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_EXP_CCS_FAILURE</id>
+      <target>MC_TARGET</target>
+      <targetType>TARGET_TYPE_OCMB_CHIP</targetType>
+    </collectRegisterFfdc>
+    <callout>
+      <target>MC_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>MC_TARGET</target>
+    </deconfigure>
+    <gard>
+        <target>MC_TARGET</target>
+    </gard>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_EXP_CCS_HUNG</rc>
+    <description>
+        Software reported that the machine is not seeing the CCS finish in the alloted time
+    </description>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_EXP_CCS_FAILURE</id>
+      <target>MC_TARGET</target>
+      <targetType>TARGET_TYPE_OCMB_CHIP</targetType>
+    </collectRegisterFfdc>
+   <callout>
+      <target>MC_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>MC_TARGET</target>
+    </deconfigure>
+    <gard>
+        <target>MC_TARGET</target>
+    </gard>
+    <callout>
+        <procedure>CODE</procedure>
+        <priority>MEDIUM</priority>
+    </callout>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_EXP_CCS_HUNG_TRYING_TO_STOP</rc>
+    <description>
+        CCS failed to return from in-progress status while trying to stop a previous program
+        Software reported that CCS did not finish in alloted time after manually triggering stop
+    </description>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_EXP_CCS_FAILURE</id>
+      <target>MC_TARGET</target>
+      <targetType>TARGET_TYPE_OCMB_CHIP</targetType>
+    </collectRegisterFfdc>
+    <callout>
+      <target>MC_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>MC_TARGET</target>
+    </deconfigure>
+    <gard>
+        <target>MC_TARGET</target>
+    </gard>
+  </hwpError>
+
 </hwpErrors>