diff options
26 files changed, 750 insertions, 57 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C new file mode 100644 index 000000000..26855282e --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C @@ -0,0 +1,166 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_explorer.C +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> + +#include <lib/shared/exp_defaults.H> +#include <lib/ccs/ccs_traits_explorer.H> +#include <generic/memory/lib/ccs/ccs.H> +#include <lib/ccs/ccs_explorer.H> +#include <lib/utils/mss_exp_conversions.H> + +// Generates linkage +constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::EXPLORER>::CS_N[]; +constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::EXPLORER>::CS_ND[]; + +namespace mss +{ +namespace ccs +{ + +/// +/// @brief Cleans up from a CCS execution - multiple ports - EXPLORER specialization +/// @param[in] i_program the vector of instructions +/// @param[in] i_ports the vector of ports +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode cleanup_from_execute<fapi2::TARGET_TYPE_MEM_PORT, mss::mc_type::EXPLORER> +(const ccs::program& i_program, + const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> >& i_ports) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Determine the CCS failure type +/// @param[in] i_target OCMB target +/// @param[in] i_type the failure type +/// @param[in] i_port The port the CCS instruction is training +/// @return ReturnCode associated with the fail. +/// @note FFDC is handled here, caller doesn't need to do it +/// +template<> +fapi2::ReturnCode fail_type( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_type, + const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port ) +{ + typedef ccsTraits<mss::mc_type::EXPLORER> TT; + + // Including the PORT_TARGET here and below at CAL_TIMEOUT since these problems likely lie at the MCA level + // So we disable the PORT and hopefully that's it + // If the problem lies with the MCBIST, it'll just have to loop + FAPI_ASSERT(TT::STAT_READ_MISCOMPARE != i_type, + fapi2::MSS_EXP_CCS_READ_MISCOMPARE() + .set_MC_TARGET(i_target) + .set_FAIL_TYPE(i_type) + .set_PORT_TARGET(i_port), + "%s CCS FAIL Read Miscompare", mss::c_str(i_port)); + + // This error is likely due to a bad CCS engine/ MCBIST + FAPI_ASSERT(TT::STAT_UE_SUE != i_type, + fapi2::MSS_EXP_CCS_UE_SUE() + .set_FAIL_TYPE(i_type) + .set_MC_TARGET(i_target), + "%s CCS FAIL UE or SUE Error", mss::c_str(i_target)); + + // Problem with the CCS engine + FAPI_ASSERT(TT::STAT_HUNG != i_type, + fapi2::MSS_EXP_CCS_HUNG().set_MC_TARGET(i_target), + "%s CCS appears hung", mss::c_str(i_target)); +fapi_try_exit: + // Due to the PRD update, we need to check for FIR's + // If any FIR's have lit up, this CCS fail could have been caused by the FIR + // So, let PRD retrigger this step to see if we can resolve the issue + return mss::check::fir_or_pll_fail<mss::mc_type::EXPLORER>(i_target, fapi2::current_err); +} + +/// +/// @brief EXP specialization for modeq_copy_cke_to_spare_cke +/// @param[in] fapi2::Target<TARGET_TYPE_OCMB_CHIP>& the target to effect +/// @param[in,out] the buffer representing the mode register +/// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports +/// @note no-op for p9n +/// +template<> +void copy_cke_to_spare_cke<fapi2::TARGET_TYPE_OCMB_CHIP>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + fapi2::buffer<uint64_t>&, states ) +{ + return; +} + +/// +/// @brief Updates the initial delays based upon the total delays passed in - EXP specialization +/// @param[in] i_target the target type on which to operate +/// @param[in] i_delay the calculated delays from CCS +/// @param[in,out] io_program the program for which to update the delays +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode update_initial_delays<fapi2::TARGET_TYPE_OCMB_CHIP, mss::mc_type::EXPLORER> +( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_delay, + ccs::program& io_program) +{ + // Check our program for any delays. If there isn't a iv_initial_delay configured, then + // we use the delay we just summed from the instructions. + if (io_program.iv_poll.iv_initial_delay == 0) + { + io_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, i_delay); + } + + if (io_program.iv_poll.iv_initial_sim_delay == 0) + { + io_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(i_delay); + } + + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Select the port(s) to be used by the CCS - EXPLORER specialization +/// @param[in] i_target the target to effect +/// @param[in] i_ports the buffer representing the ports +/// +template<> +fapi2::ReturnCode select_ports<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint64_t i_ports) +{ + // No broadcast mode, only one port, so no port selection + return fapi2::FAPI2_RC_SUCCESS; +} + +} // namespace ccs +} // namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H new file mode 100644 index 000000000..e02292508 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_explorer.H +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_CCS_EXPLORER_H_ +#define _MSS_CCS_EXPLORER_H_ + +#include <fapi2.H> +#include <lib/ccs/ccs_traits_explorer.H> +#include <generic/memory/lib/ccs/ccs.H> + +namespace mss +{ +namespace ccs +{ + +// This file ties the two needed header files together + +} // namespace ccs +} // namespace mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H new file mode 100644 index 000000000..965b98057 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H @@ -0,0 +1,269 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_traits_nimbus.H +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_CCS_TRAITS_EXP_H_ +#define _MSS_CCS_TRAITS_EXP_H_ + +#include <fapi2.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/ccs/ccs_traits.H> + +/// +/// @class ccsTraits +/// @brief Explorer CCS Engine traits +/// +template<> +class ccsTraits<mss::mc_type::EXPLORER> +{ + public: + static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + static constexpr uint64_t MODEQ_REG = EXPLR_MCBIST_CCS_MODEQ; + static constexpr uint64_t MCB_CNTL_REG = EXPLR_MCBIST_MCB_CNTLQ; + static constexpr uint64_t CNTLQ_REG = EXPLR_MCBIST_CCS_CNTLQ; + static constexpr uint64_t STATQ_REG = EXPLR_MCBIST_CCS_STATQ; + + static constexpr uint64_t PORTS_PER_MC_TARGET = mss::exp::MAX_PORT_PER_OCMB; + static constexpr uint64_t CCS_MAX_DIMM_PER_PORT = mss::exp::MAX_DIMM_PER_PORT; + static constexpr uint64_t CCS_MAX_MRANK_PER_PORT = mss::exp::MAX_MRANK_PER_PORT; + static constexpr uint64_t CCS_MAX_RANK_PER_DIMM = mss::exp::MAX_RANK_PER_DIMM; + static constexpr uint64_t CCS_MAX_RANKS_DIMM1 = mss::exp::MAX_RANKS_DIMM1; + + static constexpr uint64_t NTTM_READ_DELAY = 0x40; + static constexpr uint64_t NTTM_MODE_FORCE_READ = 33; + + + // Command Pass Disable Delay Time for Explorer - really a JEDEC timing + static constexpr uint64_t TIMING_TCPDED = 4; + + enum + { + // Non address values that are needed for helper functions + + // ODT values used for beautification + // Attribute locations + ATTR_ODT_DIMM0_R0 = 0, + ATTR_ODT_DIMM0_R1 = 1, + ATTR_ODT_DIMM1_R0 = 4, + ATTR_ODT_DIMM1_R1 = 5, + + // Right justified output - makes it so we can use insertFromRight + CCS_ODT_DIMM0_R0 = 4, + CCS_ODT_DIMM0_R1 = 5, + CCS_ODT_DIMM1_R0 = 6, + CCS_ODT_DIMM1_R1 = 7, + + // Default ODT cycle length is 5 - one for the preamble and 4 for the data + DEFAULT_ODT_CYCLE_LEN = 5, + + // CCS MODEQ + STOP_ON_ERR = EXPLR_MCBIST_CCS_MODEQ_STOP_ON_ERR, + UE_DISABLE = EXPLR_MCBIST_CCS_MODEQ_UE_DISABLE, + DATA_COMPARE_BURST_SEL = EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL, + DATA_COMPARE_BURST_SEL_LEN = EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN, + DDR_CAL_TIMEOUT_CNT = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT, + DDR_CAL_TIMEOUT_CNT_LEN = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN, + CFG_PARITY_AFTER_CMD = EXPLR_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD, + COPY_CKE_TO_SPARE_CKE = EXPLR_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE, + DISABLE_ECC_ARRAY_CHK = EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK, + DISABLE_ECC_ARRAY_CORRECTION = EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION, + CFG_DGEN_FIXED_MODE = EXPLR_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE, + DDR_CAL_TIMEOUT_CNT_MULT = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT, + DDR_CAL_TIMEOUT_CNT_MULT_LEN = EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN, + IDLE_PAT_ADDRESS_0_13 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13, + IDLE_PAT_ADDRESS_0_13_LEN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN, + IDLE_PAT_ADDRESS_17 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17, + IDLE_PAT_BANK_GROUP_1 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1, + IDLE_PAT_BANK_0_1 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1, + IDLE_PAT_BANK_0_1_LEN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN, + IDLE_PAT_BANK_GROUP_0 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0, + IDLE_PAT_ACTN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN, + IDLE_PAT_ADDRESS_16 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16, + IDLE_PAT_ADDRESS_15 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15, + IDLE_PAT_ADDRESS_14 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14, + NTTM_MODE = EXPLR_MCBIST_CCS_MODEQ_NTTM_MODE, + NTTM_RW_DATA_DLY = EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY, + NTTM_RW_DATA_DLY_LEN = EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN, + IDLE_PAT_BANK_2 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2, + DDR_PARITY_ENABLE = EXPLR_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE, + IDLE_PAT_PARITY = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY, + + // CCS CNTL + CCS_START = EXPLR_MCBIST_CCS_CNTLQ_START, + CCS_STOP = EXPLR_MCBIST_CCS_CNTLQ_STOP, + + // CCS STATQ + CCS_IN_PROGRESS = EXPLR_MCBIST_CCS_STATQ_IP, + + // ARR0 + ARR0_DDR_ADDRESS_0_13 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, + ARR0_DDR_ADDRESS_0_13_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN, + ARR0_DDR_ADDRESS_0_9 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, // Useful for rd/wr cmds + ARR0_DDR_ADDRESS_0_9_LEN = 10, // CA bits are 9:0, total length of 10 + ARR0_DDR_ADDRESS_10 = 10, // ADR10 is the 10th bit from the left in Nimbus ARR0 + ARR0_DDR_ADDRESS_17 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17, + ARR0_DDR_BANK_GROUP_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1, + ARR0_DDR_RESETN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_RESETN, + ARR0_DDR_BANK_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1, + ARR0_DDR_BANK_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN, + ARR0_DDR_BANK_GROUP_0 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0, + ARR0_DDR_ACTN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ACTN, + ARR0_DDR_ADDRESS_16 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16, + ARR0_DDR_ADDRESS_15 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15, + ARR0_DDR_ADDRESS_14 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14, + ARR0_DDR_CKE = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE, + ARR0_DDR_CKE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN, + ARR0_DDR_CSN_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1, + ARR0_DDR_CSN_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN, + ARR0_DDR_CID_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1, + ARR0_DDR_CID_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN, + ARR0_DDR_CSN_2_3 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3, + ARR0_DDR_CSN_2_3_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN, + ARR0_DDR_CID_2 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_2, + ARR0_DDR_ODT = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT, + ARR0_DDR_ODT_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN, + ARR0_DDR_CAL_TYPE = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE, + ARR0_DDR_CAL_TYPE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN, + ARR0_DDR_PARITY = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_PARITY, + ARR0_DDR_BANK_2 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2, + ARR0_LOOP_BREAK_MODE = EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE, + ARR0_LOOP_BREAK_MODE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN, + + // ARR1 + ARR1_IDLES = EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES, + ARR1_IDLES_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES_LEN, + ARR1_REPEAT_CMD_CNT = EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, + ARR1_REPEAT_CMD_CNT_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN, + ARR1_READ_OR_WRITE_DATA = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA, + ARR1_READ_OR_WRITE_DATA_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN, + ARR1_READ_COMPARE_REQUIRED = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED, + ARR1_DDR_CAL_RANK = EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK, + ARR1_DDR_CAL_RANK_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN, + ARR1_DDR_CALIBRATION_ENABLE = EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE, + ARR1_END = EXPLR_MCBIST_CCS_INST_ARR1_00_END, + ARR1_GOTO_CMD = EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD, + ARR1_GOTO_CMD_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN, + + // CCS array constants + CCS_ARRAY_LEN = 32, + CCS_ARR0_START = EXPLR_MCBIST_CCS_INST_ARR0_00, + CCS_ARR1_START = EXPLR_MCBIST_CCS_INST_ARR1_00, + }; + + /// + /// @brief Enums for CCS return codes + /// + enum + { + // Success is defined as done-bit set, no others. + STAT_QUERY_SUCCESS = 0x4000000000000000, + + // Bit positions 3:5 + STAT_ERR_MASK = 0x1800000000000000, + STAT_READ_MISCOMPARE = 0x1000000000000000, + STAT_UE_SUE = 0x0800000000000000, + + // If the fail type isn't one of these, we're hung + STAT_HUNG = 0x0ull, + }; + + + // CSN Regular Settings + static constexpr std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] = + { + // CS0 L, CS1 H, CID0-> L => Rank 0 + { 0b01, 0b00 }, + + // CS0 L, CS1 H, CID0-> H => Rank 1 + { 0b01, 0b11 }, + + // CS0 H, CS1 L, CID0-> L => Rank 2 + { 0b10, 0b00 }, + + // CS0 H, CS1 L, CID0-> H => Rank 3 + { 0b10, 0b11 }, + }; + + + // CSN Setup for Dual Direct Mode + // For DIMM0 .first is the CSN_0_1 setting, .second is the CSN_2_3 setting. + // For DIMM1 .first is the CSN_2_3 setting, .second is the CSN_0_1 setting. + static constexpr std::pair<uint64_t, uint64_t> CS_ND[mss::MAX_RANK_PER_DIMM] = + { + // CS0 L CS1 H => CS2 => H CS3 => H Rank 0 + { 0b01, 0b11 }, + + // CS0 H CS1 L => CS2 => H CS3 => H Rank 1 + { 0b10, 0b11 }, + + // CS0 H CS1 H => CS2 => L CS3 => H Rank 2 + { 0b11, 0b01 }, + + // CS0 H CS1 H => CS2 => H CS3 => L Rank 3 + { 0b11, 0b10 }, + }; + + /// + /// @brief Gets the attribute for checking our rank configuration + /// @param[in] i_target the port target on which to operate + /// @param[out] o_ranks the rank data + /// @return SUCCESS iff the code executes successfully + /// + static fapi2::ReturnCode get_rank_config_attr(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) + { + return mss::attr::get_num_master_ranks_per_dimm(i_target, o_array); + } + + /// + /// @brief Gets the attribute for checking our rank configuration + /// @param[in] i_target the port target on which to operate + /// @param[out] o_ranks the rank data + /// @return The fully setup nimbus error + /// + static fapi2::EXP_CCS_HUNG_TRYING_TO_STOP setup_trying_to_stop_err(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target) + { + return fapi2::EXP_CCS_HUNG_TRYING_TO_STOP().set_MC_TARGET(i_target); + } + + // Lab values + static constexpr uint64_t LAB_MRS_CMD = 0x000008F000000000; +}; + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H index efbec9b09..cf990c94d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H @@ -102,9 +102,11 @@ class portTraits< mss::mc_type::EXPLORER > DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE, RCD_RECOVERY_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY, + RECR_ENABLE_UE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION, RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN, + DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, DSM0Q_WRDONE_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY, diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H index 7a56d4cc6..70830f58f 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H @@ -126,6 +126,13 @@ class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP> // All of the pattern registers are calculated off of this base static constexpr uint64_t PATTERN0_REG = EXPLR_MCBIST_MCBFD0Q; + static constexpr uint64_t PATTERN1_REG = EXPLR_MCBIST_MCBFD1Q; + static constexpr uint64_t PATTERN2_REG = EXPLR_MCBIST_MCBFD2Q; + static constexpr uint64_t PATTERN3_REG = EXPLR_MCBIST_MCBFD3Q; + static constexpr uint64_t PATTERN4_REG = EXPLR_MCBIST_MCBFD4Q; + static constexpr uint64_t PATTERN5_REG = EXPLR_MCBIST_MCBFD5Q; + static constexpr uint64_t PATTERN6_REG = EXPLR_MCBIST_MCBFD6Q; + static constexpr uint64_t PATTERN7_REG = EXPLR_MCBIST_MCBFD7Q; static constexpr uint64_t DATA_ROTATE_CNFG_REG = EXPLR_MCBIST_MCBDRCRQ; static constexpr uint64_t DATA_ROTATE_SEED_REG = EXPLR_MCBIST_MCBDRSRQ; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 4d7a7d4cc..0678d94af 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -122,6 +122,8 @@ enum sizes MAX_DIMM_PER_PORT = 2, MAX_RANK_PER_DIMM = 4, MAX_BITS_PER_PORT = 80, + MAX_RANKS_DIMM1 = 2, + MAX_MRANK_PER_PORT = MAX_DIMM_PER_PORT * MAX_RANK_PER_DIMM, }; /// diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H index 42648c785..d4bfd3387 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H @@ -42,9 +42,9 @@ namespace mss { -constexpr fapi2::TargetType DEFAULT_MEM_PORT_TARGET = fapi2::TARGET_TYPE_MEM_PORT; - constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::EXPLORER; +constexpr fapi2::TargetType DEFAULT_MC_TARGET = fapi2::TARGET_TYPE_OCMB_CHIP; +constexpr fapi2::TargetType DEFAULT_MEM_PORT_TARGET = fapi2::TARGET_TYPE_MEM_PORT; } // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml index 25ca0fbfc..c6a941e2d 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml @@ -216,4 +216,186 @@ </deconfigure> </hwpError> + <registerFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <scomRegister>EXPLR_MCBIST_CCS_MODEQ</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_STATQ</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_CNTLQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBMCATQ</scomRegister> + + <!-- Instructions --> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_00</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_01</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_02</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_03</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_04</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_05</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_06</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_07</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_08</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_09</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_10</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_11</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_12</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_13</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_14</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_15</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_16</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_17</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_18</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_19</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_20</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_21</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_22</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_23</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_24</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_25</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_26</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_27</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_28</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_29</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_30</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_31</scomRegister> + + <!-- Control array --> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_00</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_01</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_02</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_03</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_04</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_05</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_06</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_07</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_08</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_09</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_10</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_11</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_12</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_13</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_14</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_15</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_16</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_17</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_18</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_19</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_20</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_21</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_22</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_23</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_24</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_25</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_26</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_27</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_28</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_29</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_30</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_31</scomRegister> + + <!-- to get the CCS state machine hung state --> + <scomRegister>EXPLR_MCBIST_MBA_MCBERRPT0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MBA_MCBERRPT1Q</scomRegister> + </registerFfdc> + + <hwpError> + <rc>RC_MSS_EXP_CCS_READ_MISCOMPARE</rc> + <description> + CCS reports a read miscompare. + </description> + <ffdc>FAIL_TYPE</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>PORT_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>PORT_TARGET</target> + </deconfigure> + <gard> + <target>PORT_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_CCS_UE_SUE</rc> + <description> + CCS reports a UE or SUE in the CCS program array + Chould be an indicator of corruption in the CCS program + </description> + <ffdc>FAIL_TYPE</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_CCS_HUNG</rc> + <description> + Software reported that the machine is not seeing the CCS finish in the alloted time + </description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_CCS_HUNG_TRYING_TO_STOP</rc> + <description> + CCS failed to return from in-progress status while trying to stop a previous program + Software reported that CCS did not finish in alloted time after manually triggering stop + </description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + </hwpErrors> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C index f5a5ba066..d3725beee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C @@ -61,6 +61,30 @@ namespace ccs { /// +/// @brief Select the port(s) to be used by the CCS - EXPLORER specialization +/// @param[in] i_target the target to effect +/// @param[in] i_ports the buffer representing the ports +/// +template<> +fapi2::ReturnCode select_ports<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + uint64_t i_ports) +{ + typedef ccsTraits<mss::mc_type::NIMBUS> TT; + fapi2::buffer<uint64_t> l_data; + fapi2::buffer<uint64_t> l_ports; + + // Not handling multiple ports here, can't do that for CCS. BRS + FAPI_TRY( l_ports.setBit(i_ports) ); + + FAPI_TRY( mss::getScom(i_target, TT::MCB_CNTL_REG, l_data) ); + l_data.insert<TT::MCB_CNTL_PORT_SEL, TT::MCB_CNTL_PORT_SEL_LEN>(l_ports); + FAPI_TRY( mss::putScom(i_target, TT::MCB_CNTL_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Execute a set of CCS instructions - multiple ports - NIMBUS specialization /// @param[in] i_program the vector of instructions /// @param[in] i_ports the vector of ports diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H index 382fa63fd..c3b93cd5d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H @@ -59,6 +59,7 @@ class ccsTraits<mss::mc_type::NIMBUS> static constexpr uint64_t STATQ_REG = MCBIST_CCS_STATQ; static constexpr uint64_t PORTS_PER_MC_TARGET = mss::PORTS_PER_MCBIST; + static constexpr uint64_t CCS_MAX_DIMM_PER_PORT = mss::MAX_DIMM_PER_PORT; static constexpr uint64_t CCS_MAX_MRANK_PER_PORT = mss::MAX_MRANK_PER_PORT; static constexpr uint64_t CCS_MAX_RANK_PER_DIMM = mss::MAX_RANK_PER_DIMM; static constexpr uint64_t CCS_MAX_RANKS_DIMM1 = mss::MAX_RANKS_DIMM1; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H index 1eba1a35b..fcad0bf4f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H @@ -317,7 +317,7 @@ class commands // Check for a valid rank FAPI_ASSERT(mss::rank::is_rank_on_dimm(i_target, i_rank), fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). + set_PORT_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). set_RANK(i_rank). set_FUNCTION(mss::ffdc_function_codes::PDA_ADD_COMMAND), "%s does not have rank %lu", mss::c_str(i_target), i_rank); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H index 86270182e..130697bbb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H @@ -1033,7 +1033,7 @@ inline fapi2::ReturnCode set_rank_field( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(SET_RANK_FIELD), "%s Invalid rank (%d) in set_rank_field", mss::c_str(i_target), @@ -1101,7 +1101,7 @@ inline fapi2::ReturnCode get_rank_field( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_RANK_FIELD), "%s Invalid rank (%d) in get_ranks_in_pair", mss::c_str(i_target), @@ -1171,7 +1171,7 @@ inline fapi2::ReturnCode set_pair_valid( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(SET_PAIR_VALID), "%s Invalid rank (%d) in get_ranks_in_pair", mss::c_str(i_target), @@ -1243,7 +1243,7 @@ inline fapi2::ReturnCode get_pair_valid( const fapi2::Target<T> i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_PAIR_VALID), "%s Invalid rank (%d) passed into get get_pair_valid", mss::c_str(i_target), @@ -1350,7 +1350,7 @@ fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target, FAPI_ASSERT( l_ordinal < MAX_RANK_PER_DIMM, fapi2::MSS_INVALID_RANK() .set_RANK(l_ordinal) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_RANKS_IN_PAIR), "%s Invalid rank (%d) in set_ranks_in_pair", mss::c_str(i_target), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 40c6ac292..5aba2807e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -1304,7 +1304,7 @@ fapi2::ReturnCode override_odt_wr_config( const fapi2::Target<fapi2::TARGET_TYPE FAPI_ASSERT( i_rank < MAX_MRANK_PER_PORT, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(OVERRIDE_ODT_WR_CONFIG), "%s had invalid rank (0x%016lx) passed into override_odt_wr_config", mss::c_str(i_target), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 507f95f86..de647a577 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -4626,7 +4626,7 @@ fapi2::ReturnCode check_rp_and_dram( const fapi2::Target<fapi2::TARGET_TYPE_MCA> // Checks for i_rp in bounds FAPI_ASSERT(i_rp < MAX_RANK_PAIRS, fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(i_target). + set_PORT_TARGET(i_target). set_RANK(i_rp). set_FUNCTION(i_function), "%s rank pair is out of bounds %lu", mss::c_str(i_target), i_rp); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 7501a0884..a7e638093 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -660,14 +660,14 @@ fapi2::ReturnCode write_ctr::post_workaround( const fapi2::Target<fapi2::TARGET_ // If the rank vector is empty log an error FAPI_ASSERT(!l_ranks.empty(), fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(i_target). + set_PORT_TARGET(i_target). set_RANK(i_rp). set_FUNCTION(mss::ffdc_function_codes::WR_VREF_TRAINING_WORKAROUND), "%s rank pair is empty! %lu", mss::c_str(i_target), i_rp); FAPI_ASSERT(l_ranks[0] != NO_RANK, fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(i_target). + set_PORT_TARGET(i_target). set_RANK(NO_RANK). set_FUNCTION(mss::ffdc_function_codes::WR_VREF_TRAINING_WORKAROUND), "%s rank pair has no ranks %lu", mss::c_str(i_target), i_rp); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index c36dda47e..4cec1ad77 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -186,9 +186,6 @@ enum ffdc_function_codes // LR training function DWL_CALL_OUT = 130, MREP_CALL_OUT = 131, - - - CCS_INST_CONFIGURE_RANK = 132, }; // Static consts describing the bits used in the cal_step_enable attribute diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C index 9cc041ed6..de136357f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C @@ -463,7 +463,7 @@ fapi2::ReturnCode execute( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_tar // Kick off the CCS engine - per port. No broadcast mode for CCS (per Shelton 9/23/15) FAPI_INF("executing CCS array for port %d (%s)", mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port), mss::c_str(i_port)); - FAPI_TRY( mss::ccs::select_ports( i_target, mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port)), + FAPI_TRY( mss::ccs::select_ports<mss::mc_type::NIMBUS>( i_target, mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port)), "Error in ccs execute" ); FAPI_TRY( execute_inst_array(i_target, i_program, i_port), "Error in ccs execute" ); } diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index d7bb833cd..b177f8d18 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -658,20 +658,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_RANK</rc> - <description> - Invalid rank passed into function - </description> - <ffdc>FUNCTION</ffdc> - <ffdc>RANK</ffdc> - <ffdc>MCA_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> <rc>RC_MSS_INVALID_RANK_PAIR</rc> <description> Invalid rank pair passed into function diff --git a/src/import/generic/memory/lib/ccs/ccs.H b/src/import/generic/memory/lib/ccs/ccs.H index aafb0826e..f97c1f885 100644 --- a/src/import/generic/memory/lib/ccs/ccs.H +++ b/src/import/generic/memory/lib/ccs/ccs.H @@ -160,9 +160,9 @@ class instruction_t // First, check rank - we need to make sure that we have a valid rank FAPI_ASSERT(iv_rank < TT::CCS_MAX_MRANK_PER_PORT, fapi2::MSS_INVALID_RANK() - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_RANK(iv_rank) - .set_FUNCTION(ffdc_function_codes::CCS_INST_CONFIGURE_RANK), + .set_FUNCTION(generic_ffdc_codes::CCS_INST_CONFIGURE_RANK), "%s rank out of bounds rank%u", mss::c_str(i_target), iv_rank); // Now the fun happens and we can deal with the actual encoding @@ -217,9 +217,9 @@ class instruction_t // So, we pass always if we're DIMM0, or if our DIMM rank is less than the maximum number of DIMM's on rank 1 FAPI_ASSERT(l_dimm_rank < TT::CCS_MAX_RANKS_DIMM1 || l_is_dimm0, fapi2::MSS_INVALID_RANK() - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_RANK(iv_rank) - .set_FUNCTION(ffdc_function_codes::CCS_INST_CONFIGURE_RANK), + .set_FUNCTION(generic_ffdc_codes::CCS_INST_CONFIGURE_RANK), "%s rank out of bounds rank%u", mss::c_str(i_target), iv_rank); } @@ -255,7 +255,7 @@ inline fapi2::ReturnCode get_rank_config(const fapi2::Target<DEFAULT_MEM_PORT_TA constexpr uint8_t QUAD_RANK_ENABLE = 4; o_rank_config = rank_configuration::DUAL_DIRECT; - uint8_t l_num_master_ranks[MAX_DIMM_PER_PORT] = {}; + uint8_t l_num_master_ranks[TT::CCS_MAX_DIMM_PER_PORT] = {}; FAPI_TRY(TT::get_rank_config_attr(i_target, l_num_master_ranks)); // We only need to check DIMM0 @@ -913,27 +913,14 @@ inline instruction_t refresh_command( const uint64_t i_rank, const uint16_t i_id /// /// @brief Select the port(s) to be used by the CCS +/// @tparam MC the memory controller type which executes the CCS instruction /// @tparam T the target type of the chiplet which executes the CCS instruction /// @tparam TT the CCS traits of the chiplet which executes the CCS instruction /// @param[in] i_target the target to effect /// @param[in] i_ports the buffer representing the ports /// -template< fapi2::TargetType T, typename TT = ccsTraits<DEFAULT_MC_TYPE> > -inline fapi2::ReturnCode select_ports( const fapi2::Target<T>& i_target, uint64_t i_ports) -{ - fapi2::buffer<uint64_t> l_data; - fapi2::buffer<uint64_t> l_ports; - - // Not handling multiple ports here, can't do that for CCS. BRS - FAPI_TRY( l_ports.setBit(i_ports) ); - - FAPI_TRY( mss::getScom(i_target, TT::MCB_CNTL_REG, l_data) ); - l_data.insert<TT::MCB_CNTL_PORT_SEL, TT::MCB_CNTL_PORT_SEL_LEN>(l_ports); - FAPI_TRY( mss::putScom(i_target, TT::MCB_CNTL_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} +template< mss::mc_type MC, fapi2::TargetType T, typename TT = ccsTraits<MC> > +fapi2::ReturnCode select_ports( const fapi2::Target<T>& i_target, uint64_t i_ports); /// /// @brief User sets to a '1'b to tell the Hdw to stop CCS whenever failure occurs. When a @@ -1290,7 +1277,7 @@ fapi2::ReturnCode execute( const fapi2::Target<T>& i_target, FAPI_INF("executing CCS array for port %d (%s)", l_port_index, mss::c_str(p)); - FAPI_TRY( select_ports( i_target, l_port_index), "Error in ccs execute" ); + FAPI_TRY( select_ports<DEFAULT_MC_TYPE>( i_target, l_port_index), "Error in ccs execute" ); FAPI_TRY( execute_inst_array(i_target, i_program, p), "Error in ccs execute" ); } } diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 90c361e94..0599a01c7 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -177,6 +177,7 @@ enum generic_ffdc_codes SET_MRANKS = 0x102A, SET_HOST_TO_DDR_SPEED_RATIO = 0x102B, SET_ATTR_HOST_TO_DDR_SPEED_RATIO = 0x102C, + CCS_INST_CONFIGURE_RANK = 0x102D, SET_DIMM_RANKS_CNFG = 0x1039, DDIMM_RAWCARD_DECODE = 0x103a, INIT_RANK_INFO = 0x103B, diff --git a/src/import/generic/procedures/xml/error_info/generic_error.xml b/src/import/generic/procedures/xml/error_info/generic_error.xml index f09e3de8f..08a7ef84a 100644 --- a/src/import/generic/procedures/xml/error_info/generic_error.xml +++ b/src/import/generic/procedures/xml/error_info/generic_error.xml @@ -240,6 +240,20 @@ </hwpError> <hwpError> + <rc>RC_MSS_INVALID_RANK</rc> + <description> + Invalid rank passed into function + </description> + <ffdc>FUNCTION</ffdc> + <ffdc>RANK</ffdc> + <ffdc>PORT_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> <rc>RC_MSS_INVALID_TIMING_VALUE</rc> <description>Invalid value calculated for timing value based on MTB and FTB from SPD.</description> <ffdc>VALUE</ffdc> diff --git a/src/import/hwpf/fapi2/tools/parseErrorInfo.pl b/src/import/hwpf/fapi2/tools/parseErrorInfo.pl index c6044e5b8..782a5a38a 100755 --- a/src/import/hwpf/fapi2/tools/parseErrorInfo.pl +++ b/src/import/hwpf/fapi2/tools/parseErrorInfo.pl @@ -513,6 +513,7 @@ print CRFILE "#include <p9_quad_scom_addresses.H>\n"; print CRFILE "#include <p9_xbus_scom_addresses.H>\n"; print CRFILE "#include <cen_gen_scom_addresses.H>\n"; print CRFILE "#include <centaur_misc_constants.H>\n"; +print CRFILE "#include <explorer_scom_addresses.H>\n"; print CRFILE "namespace fapi2\n"; print CRFILE "{\n"; print CRFILE "void getAddressData(const fapi2::HwpFfdcId i_ffdcId,\n"; diff --git a/src/usr/errldisplay/makefile b/src/usr/errldisplay/makefile index b094bfc63..a2fe4c9e4 100644 --- a/src/usr/errldisplay/makefile +++ b/src/usr/errldisplay/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2013,2017 +# Contributors Listed Below - COPYRIGHT 2013,2019 # [+] Google Inc. # [+] International Business Machines Corp. # @@ -48,3 +48,4 @@ EXTRAINCDIR += ${GENDIR}/plugins/prdf/ EXTRAINCDIR += ${ROOTPATH}/src/usr/diag/prdf/plugins/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ diff --git a/src/usr/fapi2/fapi2.mk b/src/usr/fapi2/fapi2.mk index 5f0d84f07..44220ce07 100755 --- a/src/usr/fapi2/fapi2.mk +++ b/src/usr/fapi2/fapi2.mk @@ -59,6 +59,7 @@ EXTRAINCDIR += ${HWP_PATH_2}/hwp/memory/lib/shared/ EXTRAINCDIR += ${HWP_PATH_2}/hwp/memory/lib/utils/ EXTRAINCDIR += ${HWP_PATH_2}/vpd_accessors/ EXTRAINCDIR += ${ROOTPATH}/src/usr/scom/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/common/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/ include ${ROOTPATH}/src/build/mkrules/verbose.rules.mk @@ -134,7 +135,6 @@ FAPI2_ERROR_XML += $(wildcard \ FAPI2_ERROR_XML += $(wildcard \ $(ROOTPATH)/src/import/chips/ocmb/common/procedures/xml/error_info/*.xml) - # Attribute XML files. FAPI2_ATTR_XML += $(wildcard \ $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_info/*.xml) diff --git a/src/usr/fapi2/platCreateHwpErrParser.pl b/src/usr/fapi2/platCreateHwpErrParser.pl index 618459e30..e54f26a13 100755 --- a/src/usr/fapi2/platCreateHwpErrParser.pl +++ b/src/usr/fapi2/platCreateHwpErrParser.pl @@ -6,7 +6,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2018 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] Google Inc. # [+] International Business Machines Corp. # @@ -225,6 +225,7 @@ print EDISFILE "#include <p9_perv_scom_addresses.H>\n"; print EDISFILE "#include <p9_quad_scom_addresses.H>\n"; print EDISFILE "#include <p9_xbus_scom_addresses.H>\n"; print EDISFILE "#include <cen_gen_scom_addresses.H>\n"; +print EDISFILE "#include <explorer_scom_addresses.H>\n"; print EDISFILE "#include <centaur_misc_constants.H>\n"; print EDISFILE "namespace fapi2\n"; print EDISFILE "{\n\n"; diff --git a/src/usr/isteps/mss/makefile b/src/usr/isteps/mss/makefile index 854901790..aa5cf933a 100644 --- a/src/usr/isteps/mss/makefile +++ b/src/usr/isteps/mss/makefile @@ -85,6 +85,7 @@ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/fir/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/mcbist/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/phy/ MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/ecc/ +MSS_LIB += ${EXPLORER_PROCEDURES_PATH}/hwp/memory/lib/ccs/ MSS_LIB += ${GEMINI_PROCEDURES_PATH}/hwp/memory/ MSS_LIB += ${GEMINI_PROCEDURES_PATH}/hwp/memory/lib/ @@ -186,7 +187,6 @@ endef $(call BUILD_GENERATED) - # Generate pmic_accessors header file GENERATED = gen_pmic_accessors COMMAND = gen_accessors.pl @@ -208,7 +208,6 @@ endef $(call BUILD_GENERATED) - # Add common and generated parts to object list. MSS_PATH := $(PROCEDURES_PATH)/hwp/memory/lib |
