Updates the explorer draminit for 07MAY19 spec

Change-Id: Icda444adbb903ecce82ea99b5110430e951e1716
git-coreq:hostboot:Icda444adbb903ecce82ea99b5110430e951e1716
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77400
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77749
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 131 insertions, 21 deletions

diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C
index 79a5e0321..a18fa4ba1 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C
@@ -139,6 +139,8 @@ fapi2::ReturnCode putOCCfg(
 fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_input, std::vector<uint8_t>& o_data,
         uint32_t& o_crc)
 {
+    o_data.clear();
+    FAPI_TRY(forceCrctEndian(i_input.version_number, o_data));
     FAPI_TRY(forceCrctEndian(i_input.DimmType, o_data));
     FAPI_TRY(forceCrctEndian(i_input.CsPresent, o_data));
     FAPI_TRY(forceCrctEndian(i_input.DramDataWidth, o_data));
@@ -151,9 +153,11 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu
     FAPI_TRY(forceCrctEndian(i_input.SpdCLSupported, o_data));
     FAPI_TRY(forceCrctEndian(i_input.SpdtAAmin, o_data));
     FAPI_TRY(forceCrctEndian(i_input.Rank4Mode, o_data));
+    FAPI_TRY(forceCrctEndian(i_input.EncodedQuadCs, o_data));
     FAPI_TRY(forceCrctEndian(i_input.DDPCompatible, o_data));
     FAPI_TRY(forceCrctEndian(i_input.TSV8HSupport, o_data));
     FAPI_TRY(forceCrctEndian(i_input.MRAMSupport, o_data));
+    FAPI_TRY(forceCrctEndian(i_input.MDSSupport, o_data));
     FAPI_TRY(forceCrctEndian(i_input.NumPStates, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.Frequency, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.PhyOdtImpedance, MSDG_MAX_PSTATE, o_data));
@@ -180,7 +184,7 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu
     FAPI_TRY(forceCrctEndianArray(i_input.DramDic, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.DramWritePreamble, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.DramReadPreamble, MSDG_MAX_PSTATE, o_data));
-    FAPI_TRY(forceCrctEndian(i_input.PhyEqualization, o_data));
+    FAPI_TRY(forceCrctEndianArray(i_input.PhyEqualization, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.InitVrefDQ, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.InitPhyVref, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.OdtWrMapCs, MSDG_MAX_PSTATE, o_data));
@@ -191,10 +195,20 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu
     FAPI_TRY(forceCrctEndianArray(i_input.BistCAParityLatency, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.RcdDic, MSDG_MAX_PSTATE, o_data));
     FAPI_TRY(forceCrctEndianArray(i_input.RcdVoltageCtrl, MSDG_MAX_PSTATE, o_data));
-    FAPI_TRY(forceCrctEndian(i_input.RcdIBTCtrl, o_data));
-    FAPI_TRY(forceCrctEndian(i_input.RcdDBDic, o_data));
-    FAPI_TRY(forceCrctEndian(i_input.RcdSlewRate, o_data));
-    FAPI_TRY(forceCrctEndian(i_input.EmulationSupport, o_data));
+    FAPI_TRY(forceCrctEndianArray(i_input.RcdIBTCtrl, MSDG_MAX_PSTATE, o_data));
+    FAPI_TRY(forceCrctEndianArray(i_input.RcdDBDic, MSDG_MAX_PSTATE, o_data));
+    FAPI_TRY(forceCrctEndianArray(i_input.RcdSlewRate, MSDG_MAX_PSTATE, o_data));
+    FAPI_TRY(forceCrctEndian(i_input.DFIMRL_DDRCLK, o_data));
+
+    for(uint8_t l_pstate = 0; l_pstate < MSDG_MAX_PSTATE; ++l_pstate)
+    {
+        FAPI_TRY(forceCrctEndianArray(i_input.ATxDly_A[l_pstate], DRAMINIT_NUM_ADDR_DELAYS, o_data));
+    }
+
+    for(uint8_t l_pstate = 0; l_pstate < MSDG_MAX_PSTATE; ++l_pstate)
+    {
+        FAPI_TRY(forceCrctEndianArray(i_input.ATxDly_B[l_pstate], DRAMINIT_NUM_ADDR_DELAYS, o_data));
+    }
 
     o_crc = crc32_gen(o_data);
 
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
index 30683e5bb..c77c1c59a 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2018                             */
+/* Contributors Listed Below - COPYRIGHT 2018,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -77,6 +77,7 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
         FAPI_TRY(l_rc, "Unable to instantiate phy_params for target %s", mss::c_str(i_target));
 
         // Set the params by fetching them from the attributes
+        FAPI_TRY(l_set_phy_params.set_version_number(o_phy_params));
         FAPI_TRY(l_set_phy_params.setup_DimmType(o_phy_params));
         FAPI_TRY(l_set_phy_params.setup_CsPresent(o_phy_params));
         FAPI_TRY(l_set_phy_params.setup_DramDataWidth(o_phy_params));
@@ -89,9 +90,11 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
         FAPI_TRY(l_set_phy_params.set_SpdCLSupported(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_SpdtAAmin(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_Rank4Mode(o_phy_params));
+        FAPI_TRY(l_set_phy_params.set_EncodedQuadCs(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_DDPCompatible(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_TSV8HSupport(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_MRAMSupport(o_phy_params));
+        FAPI_TRY(l_set_phy_params.set_MDSSupport(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_NumPStates(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_Frequency(o_phy_params));
         FAPI_TRY(l_set_phy_params.set_PhyOdtImpedance(o_phy_params));
@@ -133,7 +136,10 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
         FAPI_TRY(l_set_phy_params.set_RcdDBDic(o_phy_params));
 
         FAPI_TRY(l_set_phy_params.set_RcdSlewRate(o_phy_params));
-        FAPI_TRY(l_set_phy_params.set_EmulationSupport(o_phy_params));
+
+        FAPI_TRY(l_set_phy_params.set_DFIMRL_DDRCLK(o_phy_params));
+        FAPI_TRY(l_set_phy_params.set_ATxDly_A(o_phy_params));
+        FAPI_TRY(l_set_phy_params.set_ATxDly_B(o_phy_params));
     }
 
     return fapi2::FAPI2_RC_SUCCESS;
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
index cee9491c5..ab24f989c 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
@@ -44,6 +44,7 @@
 #include <generic/memory/lib/utils/c_str.H>
 #include <generic/memory/lib/utils/find.H>
 #include <generic/memory/lib/utils/mss_buffer_utils.H>
+#include <stdio.h>
 
 namespace mss
 {
@@ -72,6 +73,15 @@ enum msdg_dram_data_width
 };
 
 ///
+/// @brief Defines CS encoding mode
+///
+enum msdg_cs_encode_mode
+{
+    MSDG_QUAD_ENCODE_MODE = 1,
+    MSDG_DUAL_DIRECT_MODE = 0,
+};
+
+///
 /// @brief defines the valid 3DS stack in Explorer
 ///
 enum msdg_height_3DS
@@ -149,6 +159,7 @@ struct phy_params_t
     ///
     /// Declare variables to be used
     ///
+    uint32_t iv_version_number;
     uint8_t iv_dimm_type[MAX_DIMM_PER_PORT];
     uint16_t iv_chip_select;
     uint8_t iv_dram_data_width[MAX_DIMM_PER_PORT];
@@ -161,9 +172,11 @@ struct phy_params_t
     uint32_t iv_spdcl_support;
     uint16_t iv_taa_min;
     uint8_t iv_rank4_mode[MAX_DIMM_PER_PORT];
+    uint16_t iv_encoded_quadcs;
     uint8_t iv_ddp_compatible[MAX_DIMM_PER_PORT];
     uint8_t iv_tsv8h[MAX_DIMM_PER_PORT];
     uint8_t iv_mram_support[MAX_DIMM_PER_PORT];
+    uint8_t iv_mdssupport;
     uint8_t iv_num_pstate[MAX_DIMM_PER_PORT];
     uint64_t iv_frequency;
     uint8_t iv_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
@@ -194,7 +207,9 @@ struct phy_params_t
     uint8_t iv_f0rc7x[MAX_DIMM_PER_PORT];
     uint8_t iv_f1rc00[MAX_DIMM_PER_PORT];
     uint16_t iv_rcd_slew_rate;
-    uint8_t iv_firmware_mode;
+    uint8_t iv_dfimrl_ddrclk;
+    uint8_t iv_atxdly_a[DRAMINIT_NUM_ADDR_DELAYS];
+    uint8_t iv_atxdly_b[DRAMINIT_NUM_ADDR_DELAYS];
 };
 
 ///
@@ -223,9 +238,10 @@ class phy_params
         /// @param[in,out] o_rc the fapi2 output
         ///
         phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
-                   fapi2::ReturnCode o_rc):
+                   fapi2::ReturnCode& o_rc):
             iv_target(i_target)
         {
+            uint8_t l_master_ranks[MAX_DIMM_PER_PORT] = {};
             // Fetch attributes and populate the member variables
             FAPI_TRY(mss::attr::get_dimm_type(i_target, iv_params.iv_dimm_type));
             FAPI_TRY(mss::attr::get_exp_cs_present(i_target, iv_params.iv_chip_select));
@@ -242,6 +258,7 @@ class phy_params
             FAPI_TRY(mss::attr::get_ddp_compatibility(i_target, iv_params.iv_ddp_compatible));
             FAPI_TRY(mss::attr::get_tsv_8h_support(i_target, iv_params.iv_tsv8h));
             FAPI_TRY(mss::attr::get_mram_support(i_target, iv_params.iv_mram_support));
+            FAPI_TRY(mss::attr::get_dram_mds(i_target, iv_params.iv_mdssupport));
             FAPI_TRY(mss::attr::get_pstates(i_target, iv_params.iv_num_pstate));
             FAPI_TRY(mss::attr::get_freq(i_target, iv_params.iv_frequency));
             FAPI_TRY(mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, iv_params.iv_odt_impedance));
@@ -272,7 +289,23 @@ class phy_params
             FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc7x(i_target, iv_params.iv_f0rc7x));
             FAPI_TRY(mss::attr::get_dimm_ddr4_f1rc00(i_target, iv_params.iv_f1rc00));
             FAPI_TRY(mss::attr::get_exp_rcd_slew_rate(i_target, iv_params.iv_rcd_slew_rate));
-            FAPI_TRY(mss::attr::get_exp_firmware_emulation_mode(i_target, iv_params.iv_firmware_mode));
+            FAPI_TRY(mss::attr::get_exp_dfimrl_clk(i_target, iv_params.iv_dfimrl_ddrclk));
+            FAPI_TRY(mss::attr::get_exp_atxdly_a(i_target, iv_params.iv_atxdly_a));
+            FAPI_TRY(mss::attr::get_exp_atxdly_b(i_target, iv_params.iv_atxdly_b));
+
+            // TK update this if/when Microchip responds
+            iv_params.iv_version_number = DRAMINIT_STRUCTURE_VERSION;
+
+            // We're in quad encoded mode IF
+            // 1) 4R per DIMM
+            // 2) we have an RDIMM
+            FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_master_ranks));
+            {
+                const bool l_has_rcd = iv_params.iv_dimm_type[0] == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM ||
+                                       iv_params.iv_dimm_type[0] == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM;
+                const bool l_4r = l_master_ranks[0] == fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R;
+                iv_params.iv_encoded_quadcs = (l_has_rcd && l_4r) ? MSDG_QUAD_ENCODE_MODE : MSDG_DUAL_DIRECT_MODE;
+            }
 
         fapi_try_exit:
             o_rc = fapi2::current_err;
@@ -309,6 +342,9 @@ class phy_params
                     io_phy_params.DimmType = MSDG_RDIMM;
                     break;
 
+                // TK this will need to be updated for the 4U explorer card
+                // For 1U/2U (what we're working on now), the DDIMM means an unregistered MC to DRAM interface
+                case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM:
                 case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM:
                     io_phy_params.DimmType = MSDG_UDIMM;
                     break;
@@ -317,10 +353,6 @@ class phy_params
                     io_phy_params.DimmType = MSDG_LRDIMM;
                     break;
 
-                case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM:
-                    io_phy_params.DimmType = MSDG_DDIMM;
-                    break;
-
                 default:
                     const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(iv_target);
                     FAPI_ASSERT(false,
@@ -761,7 +793,7 @@ class phy_params
         ///
         fapi2::ReturnCode set_PhyEqualization(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.PhyEqualization = iv_params.iv_phy_equalization[0][0];
+            io_phy_params.PhyEqualization[0] = iv_params.iv_phy_equalization[0][0];
             return fapi2::FAPI2_RC_SUCCESS;
         }
 
@@ -886,7 +918,7 @@ class phy_params
         ///
         fapi2::ReturnCode set_RcdIBTCtrl(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.RcdIBTCtrl = iv_params.iv_f0rc7x[0];
+            io_phy_params.RcdIBTCtrl[0] = iv_params.iv_f0rc7x[0];
             return fapi2::FAPI2_RC_SUCCESS;
         }
 
@@ -897,7 +929,7 @@ class phy_params
         ///
         fapi2::ReturnCode set_RcdDBDic(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.RcdDBDic = iv_params.iv_f1rc00[0];
+            io_phy_params.RcdDBDic[0] = iv_params.iv_f1rc00[0];
             return fapi2::FAPI2_RC_SUCCESS;
         }
 
@@ -908,18 +940,75 @@ class phy_params
         ///
         fapi2::ReturnCode set_RcdSlewRate(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.RcdSlewRate = iv_params.iv_rcd_slew_rate;
+            io_phy_params.RcdSlewRate[0] = iv_params.iv_rcd_slew_rate;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        // Version 2 updates
+
+        ///
+        /// @brief Get the value for parameter version_number
+        /// @param[in,out] io_phy_params the phy params data struct
+        /// @return FAPI2_RC_SUCCESS
+        ///
+        fapi2::ReturnCode set_version_number(user_input_msdg& io_phy_params) const
+        {
+            io_phy_params.version_number = iv_params.iv_version_number;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Get the value for parameter version_number
+        /// @param[in,out] io_phy_params the phy params data struct
+        /// @return FAPI2_RC_SUCCESS
+        ///
+        fapi2::ReturnCode set_EncodedQuadCs(user_input_msdg& io_phy_params) const
+        {
+            io_phy_params.EncodedQuadCs = iv_params.iv_encoded_quadcs;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Get the value for parameter MDSSupport
+        /// @param[in,out] io_phy_params the phy params data struct
+        /// @return FAPI2_RC_SUCCESS
+        ///
+        fapi2::ReturnCode set_MDSSupport(user_input_msdg& io_phy_params) const
+        {
+            io_phy_params.MDSSupport = iv_params.iv_mdssupport;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Get the value for parameter DFIMRL_DDRCLK
+        /// @param[in,out] io_phy_params the phy params data struct
+        /// @return FAPI2_RC_SUCCESS
+        ///
+        fapi2::ReturnCode set_DFIMRL_DDRCLK(user_input_msdg& io_phy_params) const
+        {
+            io_phy_params.DFIMRL_DDRCLK = iv_params.iv_dfimrl_ddrclk;
+            return fapi2::FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Get the value for parameter DFIMRL_DDRCLK
+        /// @param[in,out] io_phy_params the phy params data struct
+        /// @return FAPI2_RC_SUCCESS
+        ///
+        fapi2::ReturnCode set_ATxDly_A(user_input_msdg& io_phy_params) const
+        {
+            memcpy(&io_phy_params.ATxDly_A[0][0], &iv_params.iv_atxdly_a[0], DRAMINIT_NUM_ADDR_DELAYS);
             return fapi2::FAPI2_RC_SUCCESS;
         }
 
         ///
-        /// @brief Get the value for parameter EmulationSupport
+        /// @brief Get the value for parameter DFIMRL_DDRCLK
         /// @param[in,out] io_phy_params the phy params data struct
         /// @return FAPI2_RC_SUCCESS
         ///
-        fapi2::ReturnCode set_EmulationSupport(user_input_msdg& io_phy_params) const
+        fapi2::ReturnCode set_ATxDly_B(user_input_msdg& io_phy_params) const
         {
-            io_phy_params.EmulationSupport = iv_params.iv_firmware_mode;
+            memcpy(&io_phy_params.ATxDly_B[0][0], &iv_params.iv_atxdly_b[0], DRAMINIT_NUM_ADDR_DELAYS);
             return fapi2::FAPI2_RC_SUCCESS;
         }
 };
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
index c75014bdc..7be962792 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
@@ -82,6 +82,7 @@ void display_lane_results(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_t
     }
 
     // If we failed, display the information as INF
+    else
     {
         FAPI_INF("%s lane: %u FAILING R0:%u R1:%u R2:%u R3:%u",
                  mss::c_str(i_target), i_lane,