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authorStephen Glancy <sglancy@us.ibm.com>2019-05-14 16:41:07 -0400
committerDaniel M. Crowell <dcrowell@us.ibm.com>2019-06-04 08:29:42 -0500
commit2acc85787f4b9166e11a9e12ba244cbacb2f71ec (patch)
treea1c1bda969efae33c547b1630537329b1a7d152e
parent19394bc52406397f343dbcc1c2ffa4a8d65d959d (diff)
downloadtalos-hostboot-2acc85787f4b9166e11a9e12ba244cbacb2f71ec.tar.gz
talos-hostboot-2acc85787f4b9166e11a9e12ba244cbacb2f71ec.zip
Updates the explorer draminit for 07MAY19 spec
Change-Id: Icda444adbb903ecce82ea99b5110430e951e1716 git-coreq:hostboot:Icda444adbb903ecce82ea99b5110430e951e1716 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77400 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77749 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-rw-r--r--src/import/chips/ocmb/explorer/common/include/exp_data_structs.H55
-rw-r--r--src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C24
-rw-r--r--src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C10
-rw-r--r--src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H117
-rw-r--r--src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C1
-rw-r--r--src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C9
-rw-r--r--src/import/generic/memory/lib/mss_generic_attribute_getters.H20
-rw-r--r--src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml12
8 files changed, 215 insertions, 33 deletions
diff --git a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H
index 56f641637..bca66bed1 100644
--- a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H
+++ b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H
@@ -56,6 +56,10 @@ enum exp_struct_sizes
SENSOR_CACHE_PADDING_SIZE_0 = 3,
SENSOR_CACHE_PADDING_SIZE_1 = 15,
+ // Constants for draminit
+ DRAMINIT_NUM_ADDR_DELAYS = 8,
+ DRAMINIT_STRUCTURE_VERSION = 2,
+
// Training response constants
TIMING_RESPONSE_2D_ARRAY_SIZE = 16,
TRAINING_RESPONSE_NUM_RANKS = 4,
@@ -113,6 +117,8 @@ typedef struct
///
typedef struct user_input_msdg
{
+ uint32_t version_number;
+
// Choose the Dimm type from one of below:
// 0 = UDIMM
// 1 = RDIMM
@@ -187,6 +193,16 @@ typedef struct user_input_msdg
// 0 = Normal mode (2-rank);
uint16_t Rank4Mode;
+ // Operate PHY in Encoded QuadCs Mode (only valid for
+ // RDIMM/RLDIMM) (NOT Supported in Explorer) when enabled,
+ // each CA bus drives one RCD in Encoded QuadCs mode.
+ // {cid_a/b[0],csn_a/b[1:0]} are connected to {DC0,DCS1_n,DCS0_n}
+ // to select master ranks. cid_a/b[1] is connected to DC2 to
+ // select up to 2 logic ranks (2H 3DStack)
+ // 1 = Encoded QuadCs Mode
+ // 0 = Direct DualCs Mod
+ uint16_t EncodedQuadCs;
+
// Support 1rank 3DS Device in
// 1 = 1 rank 3DS in DDP board
// PHY are connected to c[0],c[1],c[2] of DRAM);
@@ -207,6 +223,12 @@ typedef struct user_input_msdg
// 0 = Normal DDR4 DRAM;
uint16_t MRAMSupport;
+
+ // 1 = Support MDS 8H DRAM (odt[1] is connected to c[2] of
+ // MDS DRAM);
+ // 0 = Normal Mode;
+ uint16_t MDSSupport;
+
// Number of p-states used
// Always set NumPStates to 1 for Explorer.
// For the fields with Pstate array, only need to fill [0] entry.
@@ -426,7 +448,7 @@ typedef struct user_input_msdg
// Disable Receiver DFE
// PhyEqualization[1] = 0: Enable Driver FFE; = 0:
// Disable Driver FFE
- uint16_t PhyEqualization;
+ uint16_t PhyEqualization[MSDG_MAX_PSTATE];
// Initial VrefDQ (MR6)
// InitVrefDQ[6] = VrefDQ training range (same as MR6[6])
@@ -528,14 +550,14 @@ typedef struct user_input_msdg
// RcdIBTCtrl[1:0] CA Input Bus Termination
// RcdIBTCtrl[3:2] DCS[3:0]_n Input Bus Termination // RcdIBTCtrl[5:4] DCKE Input Bus Termination
// RcdIBTCtrl[7:6] DODT Input Bus Termination
- uint16_t RcdIBTCtrl;
+ uint16_t RcdIBTCtrl[MSDG_MAX_PSTATE];
// RCD Data Buffer Interface Driver Characteristics (F1RC00)
// RcdDBDic[0] BCOM[3:0],BODT,BCKE, driver strength
// RcdDBDic[1] Reserved
// RcdDBDic[2] BCK_t/BCK_c driver strength
// RcdDBDic[3] Reserved
- uint16_t RcdDBDic;
+ uint16_t RcdDBDic[MSDG_MAX_PSTATE];
// RCD slew rate control (F1RC02,F1RC03,F1RC04,F1RC05)
// RcdSlewRate[1:0] slew rate control of address/command
@@ -545,12 +567,27 @@ typedef struct user_input_msdg
// RcdSlewRate[9:8] slew rate control of Y1_t/c, Y3_t/c
// RcdSlewRate[11:10] slew rate control of Y0_t/c, Y2_t/c
// RcdSlewRate[13:12] slew rate control of BCOM[3:0], BODT, BCKE // RcdSlewRate[15:14] slew rate control of BCK_t/c
- uint16_t RcdSlewRate;
-
- // Enable Special mode for Emulation Support
- // [0] = 0 Normal firmware mode
- // [0] = 1 Emulation firmware mode
- uint16_t EmulationSupport;
+ uint16_t RcdSlewRate[MSDG_MAX_PSTATE];
+
+ // DFIMRL_DDRCLK: Max Read Latency counted by DDR Clock.
+ // dfi_rddata is returned (14 + DFIMRL_DDRCLK) cycles after
+ // dfi_rddata_en is asserted.
+ uint16_t DFIMRL_DDRCLK;
+
+ //ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1]
+ //ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1]
+ //ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16]
+ //ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0]
+ //ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY
+ //ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0]
+ //ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10]
+ //ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14]
+ //7bit A-side AC Delay
+ //ATxDly_A[pstate][NumAnib]
+ uint8_t ATxDly_A[MSDG_MAX_PSTATE][DRAMINIT_NUM_ADDR_DELAYS];
+ //7bit B-side AC Delay
+ //ATxDly_B[pstate][NumAnib]
+ uint8_t ATxDly_B[MSDG_MAX_PSTATE][DRAMINIT_NUM_ADDR_DELAYS];
} user_input_msdg_t;
///
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C
index 79a5e0321..a18fa4ba1 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C
@@ -139,6 +139,8 @@ fapi2::ReturnCode putOCCfg(
fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_input, std::vector<uint8_t>& o_data,
uint32_t& o_crc)
{
+ o_data.clear();
+ FAPI_TRY(forceCrctEndian(i_input.version_number, o_data));
FAPI_TRY(forceCrctEndian(i_input.DimmType, o_data));
FAPI_TRY(forceCrctEndian(i_input.CsPresent, o_data));
FAPI_TRY(forceCrctEndian(i_input.DramDataWidth, o_data));
@@ -151,9 +153,11 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu
FAPI_TRY(forceCrctEndian(i_input.SpdCLSupported, o_data));
FAPI_TRY(forceCrctEndian(i_input.SpdtAAmin, o_data));
FAPI_TRY(forceCrctEndian(i_input.Rank4Mode, o_data));
+ FAPI_TRY(forceCrctEndian(i_input.EncodedQuadCs, o_data));
FAPI_TRY(forceCrctEndian(i_input.DDPCompatible, o_data));
FAPI_TRY(forceCrctEndian(i_input.TSV8HSupport, o_data));
FAPI_TRY(forceCrctEndian(i_input.MRAMSupport, o_data));
+ FAPI_TRY(forceCrctEndian(i_input.MDSSupport, o_data));
FAPI_TRY(forceCrctEndian(i_input.NumPStates, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.Frequency, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.PhyOdtImpedance, MSDG_MAX_PSTATE, o_data));
@@ -180,7 +184,7 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu
FAPI_TRY(forceCrctEndianArray(i_input.DramDic, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.DramWritePreamble, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.DramReadPreamble, MSDG_MAX_PSTATE, o_data));
- FAPI_TRY(forceCrctEndian(i_input.PhyEqualization, o_data));
+ FAPI_TRY(forceCrctEndianArray(i_input.PhyEqualization, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.InitVrefDQ, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.InitPhyVref, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.OdtWrMapCs, MSDG_MAX_PSTATE, o_data));
@@ -191,10 +195,20 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu
FAPI_TRY(forceCrctEndianArray(i_input.BistCAParityLatency, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.RcdDic, MSDG_MAX_PSTATE, o_data));
FAPI_TRY(forceCrctEndianArray(i_input.RcdVoltageCtrl, MSDG_MAX_PSTATE, o_data));
- FAPI_TRY(forceCrctEndian(i_input.RcdIBTCtrl, o_data));
- FAPI_TRY(forceCrctEndian(i_input.RcdDBDic, o_data));
- FAPI_TRY(forceCrctEndian(i_input.RcdSlewRate, o_data));
- FAPI_TRY(forceCrctEndian(i_input.EmulationSupport, o_data));
+ FAPI_TRY(forceCrctEndianArray(i_input.RcdIBTCtrl, MSDG_MAX_PSTATE, o_data));
+ FAPI_TRY(forceCrctEndianArray(i_input.RcdDBDic, MSDG_MAX_PSTATE, o_data));
+ FAPI_TRY(forceCrctEndianArray(i_input.RcdSlewRate, MSDG_MAX_PSTATE, o_data));
+ FAPI_TRY(forceCrctEndian(i_input.DFIMRL_DDRCLK, o_data));
+
+ for(uint8_t l_pstate = 0; l_pstate < MSDG_MAX_PSTATE; ++l_pstate)
+ {
+ FAPI_TRY(forceCrctEndianArray(i_input.ATxDly_A[l_pstate], DRAMINIT_NUM_ADDR_DELAYS, o_data));
+ }
+
+ for(uint8_t l_pstate = 0; l_pstate < MSDG_MAX_PSTATE; ++l_pstate)
+ {
+ FAPI_TRY(forceCrctEndianArray(i_input.ATxDly_B[l_pstate], DRAMINIT_NUM_ADDR_DELAYS, o_data));
+ }
o_crc = crc32_gen(o_data);
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
index 30683e5bb..c77c1c59a 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -77,6 +77,7 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
FAPI_TRY(l_rc, "Unable to instantiate phy_params for target %s", mss::c_str(i_target));
// Set the params by fetching them from the attributes
+ FAPI_TRY(l_set_phy_params.set_version_number(o_phy_params));
FAPI_TRY(l_set_phy_params.setup_DimmType(o_phy_params));
FAPI_TRY(l_set_phy_params.setup_CsPresent(o_phy_params));
FAPI_TRY(l_set_phy_params.setup_DramDataWidth(o_phy_params));
@@ -89,9 +90,11 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
FAPI_TRY(l_set_phy_params.set_SpdCLSupported(o_phy_params));
FAPI_TRY(l_set_phy_params.set_SpdtAAmin(o_phy_params));
FAPI_TRY(l_set_phy_params.set_Rank4Mode(o_phy_params));
+ FAPI_TRY(l_set_phy_params.set_EncodedQuadCs(o_phy_params));
FAPI_TRY(l_set_phy_params.set_DDPCompatible(o_phy_params));
FAPI_TRY(l_set_phy_params.set_TSV8HSupport(o_phy_params));
FAPI_TRY(l_set_phy_params.set_MRAMSupport(o_phy_params));
+ FAPI_TRY(l_set_phy_params.set_MDSSupport(o_phy_params));
FAPI_TRY(l_set_phy_params.set_NumPStates(o_phy_params));
FAPI_TRY(l_set_phy_params.set_Frequency(o_phy_params));
FAPI_TRY(l_set_phy_params.set_PhyOdtImpedance(o_phy_params));
@@ -133,7 +136,10 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C
FAPI_TRY(l_set_phy_params.set_RcdDBDic(o_phy_params));
FAPI_TRY(l_set_phy_params.set_RcdSlewRate(o_phy_params));
- FAPI_TRY(l_set_phy_params.set_EmulationSupport(o_phy_params));
+
+ FAPI_TRY(l_set_phy_params.set_DFIMRL_DDRCLK(o_phy_params));
+ FAPI_TRY(l_set_phy_params.set_ATxDly_A(o_phy_params));
+ FAPI_TRY(l_set_phy_params.set_ATxDly_B(o_phy_params));
}
return fapi2::FAPI2_RC_SUCCESS;
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
index cee9491c5..ab24f989c 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
@@ -44,6 +44,7 @@
#include <generic/memory/lib/utils/c_str.H>
#include <generic/memory/lib/utils/find.H>
#include <generic/memory/lib/utils/mss_buffer_utils.H>
+#include <stdio.h>
namespace mss
{
@@ -72,6 +73,15 @@ enum msdg_dram_data_width
};
///
+/// @brief Defines CS encoding mode
+///
+enum msdg_cs_encode_mode
+{
+ MSDG_QUAD_ENCODE_MODE = 1,
+ MSDG_DUAL_DIRECT_MODE = 0,
+};
+
+///
/// @brief defines the valid 3DS stack in Explorer
///
enum msdg_height_3DS
@@ -149,6 +159,7 @@ struct phy_params_t
///
/// Declare variables to be used
///
+ uint32_t iv_version_number;
uint8_t iv_dimm_type[MAX_DIMM_PER_PORT];
uint16_t iv_chip_select;
uint8_t iv_dram_data_width[MAX_DIMM_PER_PORT];
@@ -161,9 +172,11 @@ struct phy_params_t
uint32_t iv_spdcl_support;
uint16_t iv_taa_min;
uint8_t iv_rank4_mode[MAX_DIMM_PER_PORT];
+ uint16_t iv_encoded_quadcs;
uint8_t iv_ddp_compatible[MAX_DIMM_PER_PORT];
uint8_t iv_tsv8h[MAX_DIMM_PER_PORT];
uint8_t iv_mram_support[MAX_DIMM_PER_PORT];
+ uint8_t iv_mdssupport;
uint8_t iv_num_pstate[MAX_DIMM_PER_PORT];
uint64_t iv_frequency;
uint8_t iv_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
@@ -194,7 +207,9 @@ struct phy_params_t
uint8_t iv_f0rc7x[MAX_DIMM_PER_PORT];
uint8_t iv_f1rc00[MAX_DIMM_PER_PORT];
uint16_t iv_rcd_slew_rate;
- uint8_t iv_firmware_mode;
+ uint8_t iv_dfimrl_ddrclk;
+ uint8_t iv_atxdly_a[DRAMINIT_NUM_ADDR_DELAYS];
+ uint8_t iv_atxdly_b[DRAMINIT_NUM_ADDR_DELAYS];
};
///
@@ -223,9 +238,10 @@ class phy_params
/// @param[in,out] o_rc the fapi2 output
///
phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
- fapi2::ReturnCode o_rc):
+ fapi2::ReturnCode& o_rc):
iv_target(i_target)
{
+ uint8_t l_master_ranks[MAX_DIMM_PER_PORT] = {};
// Fetch attributes and populate the member variables
FAPI_TRY(mss::attr::get_dimm_type(i_target, iv_params.iv_dimm_type));
FAPI_TRY(mss::attr::get_exp_cs_present(i_target, iv_params.iv_chip_select));
@@ -242,6 +258,7 @@ class phy_params
FAPI_TRY(mss::attr::get_ddp_compatibility(i_target, iv_params.iv_ddp_compatible));
FAPI_TRY(mss::attr::get_tsv_8h_support(i_target, iv_params.iv_tsv8h));
FAPI_TRY(mss::attr::get_mram_support(i_target, iv_params.iv_mram_support));
+ FAPI_TRY(mss::attr::get_dram_mds(i_target, iv_params.iv_mdssupport));
FAPI_TRY(mss::attr::get_pstates(i_target, iv_params.iv_num_pstate));
FAPI_TRY(mss::attr::get_freq(i_target, iv_params.iv_frequency));
FAPI_TRY(mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, iv_params.iv_odt_impedance));
@@ -272,7 +289,23 @@ class phy_params
FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc7x(i_target, iv_params.iv_f0rc7x));
FAPI_TRY(mss::attr::get_dimm_ddr4_f1rc00(i_target, iv_params.iv_f1rc00));
FAPI_TRY(mss::attr::get_exp_rcd_slew_rate(i_target, iv_params.iv_rcd_slew_rate));
- FAPI_TRY(mss::attr::get_exp_firmware_emulation_mode(i_target, iv_params.iv_firmware_mode));
+ FAPI_TRY(mss::attr::get_exp_dfimrl_clk(i_target, iv_params.iv_dfimrl_ddrclk));
+ FAPI_TRY(mss::attr::get_exp_atxdly_a(i_target, iv_params.iv_atxdly_a));
+ FAPI_TRY(mss::attr::get_exp_atxdly_b(i_target, iv_params.iv_atxdly_b));
+
+ // TK update this if/when Microchip responds
+ iv_params.iv_version_number = DRAMINIT_STRUCTURE_VERSION;
+
+ // We're in quad encoded mode IF
+ // 1) 4R per DIMM
+ // 2) we have an RDIMM
+ FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_master_ranks));
+ {
+ const bool l_has_rcd = iv_params.iv_dimm_type[0] == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM ||
+ iv_params.iv_dimm_type[0] == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM;
+ const bool l_4r = l_master_ranks[0] == fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R;
+ iv_params.iv_encoded_quadcs = (l_has_rcd && l_4r) ? MSDG_QUAD_ENCODE_MODE : MSDG_DUAL_DIRECT_MODE;
+ }
fapi_try_exit:
o_rc = fapi2::current_err;
@@ -309,6 +342,9 @@ class phy_params
io_phy_params.DimmType = MSDG_RDIMM;
break;
+ // TK this will need to be updated for the 4U explorer card
+ // For 1U/2U (what we're working on now), the DDIMM means an unregistered MC to DRAM interface
+ case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM:
case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM:
io_phy_params.DimmType = MSDG_UDIMM;
break;
@@ -317,10 +353,6 @@ class phy_params
io_phy_params.DimmType = MSDG_LRDIMM;
break;
- case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM:
- io_phy_params.DimmType = MSDG_DDIMM;
- break;
-
default:
const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(iv_target);
FAPI_ASSERT(false,
@@ -761,7 +793,7 @@ class phy_params
///
fapi2::ReturnCode set_PhyEqualization(user_input_msdg& io_phy_params) const
{
- io_phy_params.PhyEqualization = iv_params.iv_phy_equalization[0][0];
+ io_phy_params.PhyEqualization[0] = iv_params.iv_phy_equalization[0][0];
return fapi2::FAPI2_RC_SUCCESS;
}
@@ -886,7 +918,7 @@ class phy_params
///
fapi2::ReturnCode set_RcdIBTCtrl(user_input_msdg& io_phy_params) const
{
- io_phy_params.RcdIBTCtrl = iv_params.iv_f0rc7x[0];
+ io_phy_params.RcdIBTCtrl[0] = iv_params.iv_f0rc7x[0];
return fapi2::FAPI2_RC_SUCCESS;
}
@@ -897,7 +929,7 @@ class phy_params
///
fapi2::ReturnCode set_RcdDBDic(user_input_msdg& io_phy_params) const
{
- io_phy_params.RcdDBDic = iv_params.iv_f1rc00[0];
+ io_phy_params.RcdDBDic[0] = iv_params.iv_f1rc00[0];
return fapi2::FAPI2_RC_SUCCESS;
}
@@ -908,18 +940,75 @@ class phy_params
///
fapi2::ReturnCode set_RcdSlewRate(user_input_msdg& io_phy_params) const
{
- io_phy_params.RcdSlewRate = iv_params.iv_rcd_slew_rate;
+ io_phy_params.RcdSlewRate[0] = iv_params.iv_rcd_slew_rate;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ // Version 2 updates
+
+ ///
+ /// @brief Get the value for parameter version_number
+ /// @param[in,out] io_phy_params the phy params data struct
+ /// @return FAPI2_RC_SUCCESS
+ ///
+ fapi2::ReturnCode set_version_number(user_input_msdg& io_phy_params) const
+ {
+ io_phy_params.version_number = iv_params.iv_version_number;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Get the value for parameter version_number
+ /// @param[in,out] io_phy_params the phy params data struct
+ /// @return FAPI2_RC_SUCCESS
+ ///
+ fapi2::ReturnCode set_EncodedQuadCs(user_input_msdg& io_phy_params) const
+ {
+ io_phy_params.EncodedQuadCs = iv_params.iv_encoded_quadcs;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Get the value for parameter MDSSupport
+ /// @param[in,out] io_phy_params the phy params data struct
+ /// @return FAPI2_RC_SUCCESS
+ ///
+ fapi2::ReturnCode set_MDSSupport(user_input_msdg& io_phy_params) const
+ {
+ io_phy_params.MDSSupport = iv_params.iv_mdssupport;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Get the value for parameter DFIMRL_DDRCLK
+ /// @param[in,out] io_phy_params the phy params data struct
+ /// @return FAPI2_RC_SUCCESS
+ ///
+ fapi2::ReturnCode set_DFIMRL_DDRCLK(user_input_msdg& io_phy_params) const
+ {
+ io_phy_params.DFIMRL_DDRCLK = iv_params.iv_dfimrl_ddrclk;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Get the value for parameter DFIMRL_DDRCLK
+ /// @param[in,out] io_phy_params the phy params data struct
+ /// @return FAPI2_RC_SUCCESS
+ ///
+ fapi2::ReturnCode set_ATxDly_A(user_input_msdg& io_phy_params) const
+ {
+ memcpy(&io_phy_params.ATxDly_A[0][0], &iv_params.iv_atxdly_a[0], DRAMINIT_NUM_ADDR_DELAYS);
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Get the value for parameter EmulationSupport
+ /// @brief Get the value for parameter DFIMRL_DDRCLK
/// @param[in,out] io_phy_params the phy params data struct
/// @return FAPI2_RC_SUCCESS
///
- fapi2::ReturnCode set_EmulationSupport(user_input_msdg& io_phy_params) const
+ fapi2::ReturnCode set_ATxDly_B(user_input_msdg& io_phy_params) const
{
- io_phy_params.EmulationSupport = iv_params.iv_firmware_mode;
+ memcpy(&io_phy_params.ATxDly_B[0][0], &iv_params.iv_atxdly_b[0], DRAMINIT_NUM_ADDR_DELAYS);
return fapi2::FAPI2_RC_SUCCESS;
}
};
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
index c75014bdc..7be962792 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C
@@ -82,6 +82,7 @@ void display_lane_results(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_t
}
// If we failed, display the information as INF
+ else
{
FAPI_INF("%s lane: %u FAILING R0:%u R1:%u R2:%u R3:%u",
mss::c_str(i_target), i_lane,
diff --git a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
index eb6eb8604..a81664989 100644
--- a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
+++ b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
@@ -32,8 +32,9 @@ using namespace fapi2;
constexpr uint64_t literal_1 = 1;
constexpr uint64_t literal_3 = 3;
constexpr uint64_t literal_0 = 0;
-constexpr uint64_t literal_9 = 9;
+constexpr uint64_t literal_11 = 11;
constexpr uint64_t literal_4 = 4;
+constexpr uint64_t literal_9 = 9;
constexpr uint64_t literal_14 = 14;
constexpr uint64_t literal_7 = 7;
constexpr uint64_t literal_2 = 2;
@@ -42,7 +43,6 @@ constexpr uint64_t literal_5 = 5;
constexpr uint64_t literal_266 = 266;
constexpr uint64_t literal_1866 = 1866;
constexpr uint64_t literal_2668 = 2668;
-constexpr uint64_t literal_11 = 11;
constexpr uint64_t literal_2934 = 2934;
constexpr uint64_t literal_12 = 12;
constexpr uint64_t literal_13 = 13;
@@ -105,6 +105,8 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
fapi2::ATTR_IS_SIMULATION_Type l_TGT2_ATTR_IS_SIMULATION;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT2, l_TGT2_ATTR_IS_SIMULATION));
uint64_t l_def_IS_MICROSEMI_SIM = (l_TGT2_ATTR_IS_SIMULATION == literal_1);
+ fapi2::ATTR_MEM_EXP_DFIMRL_CLK_Type l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK;
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EXP_DFIMRL_CLK, TGT1, l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK));
fapi2::ATTR_MEM_RDIMM_BUFFER_DELAY_Type l_TGT1_ATTR_MEM_RDIMM_BUFFER_DELAY;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_RDIMM_BUFFER_DELAY, TGT1, l_TGT1_ATTR_MEM_RDIMM_BUFFER_DELAY));
fapi2::ATTR_MEM_EFF_DIMM_TYPE_Type l_TGT1_ATTR_MEM_EFF_DIMM_TYPE;
@@ -237,7 +239,8 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
if (l_def_IS_MICROSEMI_SIM)
{
- l_scom_buffer.insert<36, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_9) + l_def_RDIMM_Add_latency) );
+ l_scom_buffer.insert<36, 6, 58, uint64_t>((((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_11) + l_def_RDIMM_Add_latency) +
+ l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK) );
}
else if (l_def_IS_IBM_SIM)
{
diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H
index f26d39723..97fa34867 100644
--- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H
+++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H
@@ -2553,6 +2553,26 @@ fapi_try_exit:
}
///
+/// @brief ATTR_MEM_EFF_DRAM_MDS getter
+/// @param[in] const ref to the TARGET_TYPE_MEM_PORT
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generate_mc_port_params
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note Controls if the given target has an MDS (managed DRAM solution)
+///
+inline fapi2::ReturnCode get_dram_mds(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value)
+{
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_MDS, i_target, o_value) );
+ return fapi2::current_err;
+
+fapi_try_exit:
+ FAPI_ERR("failed getting ATTR_MEM_EFF_DRAM_MDS: 0x%lx (target: %s)",
+ uint64_t(fapi2::current_err), mss::c_str(i_target));
+ return fapi2::current_err;
+}
+
+///
/// @brief ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM getter
/// @param[in] const ref to the TARGET_TYPE_DIMM
/// @param[out] uint8_t& reference to store the value
diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml
index 60cf77d35..8e7b12bbf 100644
--- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml
+++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml
@@ -752,6 +752,18 @@
</attribute>
<attribute>
+ <id>ATTR_MEM_EFF_DRAM_MDS</id>
+ <targetType>TARGET_TYPE_MEM_PORT</targetType>
+ <description>
+ Controls if the given target has an MDS (managed DRAM solution)
+ </description>
+ <initToZero></initToZero>
+ <valueType>uint8</valueType>
+ <writeable/>
+ <mssAccessorName>dram_mds</mssAccessorName>
+ </attribute>
+
+ <attribute>
<id>ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
<targetType>TARGET_TYPE_MEM_PORT</targetType>
<description>
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