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authorMark Pizzutillo <Mark.Pizzutillo@ibm.com>2019-04-15 16:08:22 -0400
committerChristian R. Geddes <crgeddes@us.ibm.com>2019-05-23 10:47:25 -0500
commit1dab92e705f6f8c893a09ff250eab1a762f7e88f (patch)
tree057239c62c8518640bad8c1a3ea306a84c108725 /src/import/chips/ocmb/common/include
parent5de4c5ec41bf05f8e3d735ded4cc864d017e6279 (diff)
downloadtalos-hostboot-1dab92e705f6f8c893a09ff250eab1a762f7e88f.tar.gz
talos-hostboot-1dab92e705f6f8c893a09ff250eab1a762f7e88f.zip
Add PMIC enable procedure code and UTs
Change-Id: Iac5cd8016efa705be6512b842e0e793eb3d4c5fa Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74639 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77132 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/ocmb/common/include')
-rw-r--r--src/import/chips/ocmb/common/include/pmic_regs.H130
-rw-r--r--src/import/chips/ocmb/common/include/pmic_regs_fld.H53
2 files changed, 183 insertions, 0 deletions
diff --git a/src/import/chips/ocmb/common/include/pmic_regs.H b/src/import/chips/ocmb/common/include/pmic_regs.H
index 4a6de40d4..f3010e727 100644
--- a/src/import/chips/ocmb/common/include/pmic_regs.H
+++ b/src/import/chips/ocmb/common/include/pmic_regs.H
@@ -22,3 +22,133 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
+
+///
+/// @file pmic_regs.H
+/// @brief PMIC Registers
+///
+// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com>
+// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB
+
+#ifndef __PMIC_REGS__
+#define __PMIC_REGS__
+
+#include <lib/utils/pmic_consts.H>
+
+///
+/// @brief Registers for PMIC devices
+/// @class pmicRegs
+/// @tparam P pmic_product
+///
+template<mss::pmic::product P>
+struct pmicRegs;
+
+///
+/// @brief JEDEC Common Registers
+/// @note These registers are not defined with any particular name other than RXX.
+/// Their purposes and bit-mappings are outlined in any of the JEDEC compliant PMIC specs.
+///
+template<>
+struct pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>
+{
+ static constexpr uint8_t BROADCAST = 0x0;
+ /* R00 - R03 RESERVED */
+ static constexpr uint8_t R04 = 0x04;
+ static constexpr uint8_t R05 = 0x05;
+ static constexpr uint8_t R06 = 0x06;
+ /* R07 RESERVED */
+ static constexpr uint8_t R08 = 0x08;
+ static constexpr uint8_t R09 = 0x09;
+ static constexpr uint8_t R0A = 0x0A;
+ static constexpr uint8_t R0B = 0x0B;
+ static constexpr uint8_t R0C = 0x0C;
+ static constexpr uint8_t R0D = 0x0D;
+ static constexpr uint8_t R0E = 0x0E;
+ static constexpr uint8_t R0F = 0x0F;
+ static constexpr uint8_t R10 = 0x10;
+ static constexpr uint8_t R11 = 0x11;
+ static constexpr uint8_t R12 = 0x12;
+ static constexpr uint8_t R13 = 0x13;
+ static constexpr uint8_t R14 = 0x14;
+ static constexpr uint8_t R15 = 0x15;
+ static constexpr uint8_t R16 = 0x16;
+ static constexpr uint8_t R17 = 0x17;
+ static constexpr uint8_t R18 = 0x18;
+ static constexpr uint8_t R19 = 0x19;
+ static constexpr uint8_t R1A = 0x1A;
+ static constexpr uint8_t R1B = 0x1B;
+ static constexpr uint8_t R1C = 0x1C;
+ static constexpr uint8_t R1D = 0x1D;
+ static constexpr uint8_t R1E = 0x1E;
+ static constexpr uint8_t R1F = 0x1F;
+ static constexpr uint8_t R20 = 0x20;
+ static constexpr uint8_t R21_SWA_VOLTAGE_SETTING = 0x21;
+ static constexpr uint8_t R22 = 0x22;
+ static constexpr uint8_t R23_SWB_VOLTAGE_SETTING = 0x23;
+ static constexpr uint8_t R24 = 0x24;
+ static constexpr uint8_t R25_SWC_VOLTAGE_SETTING = 0x25;
+ static constexpr uint8_t R26 = 0x26;
+ static constexpr uint8_t R27_SWD_VOLTAGE_SETTING = 0x27;
+ static constexpr uint8_t R28 = 0x28;
+ static constexpr uint8_t R29 = 0x29;
+ static constexpr uint8_t R2A = 0x2A;
+ static constexpr uint8_t R2B = 0x2B;
+ static constexpr uint8_t R2C = 0x2C;
+ static constexpr uint8_t R2D = 0x2D;
+ static constexpr uint8_t R2E = 0x2E;
+ static constexpr uint8_t R2F = 0x2F;
+ static constexpr uint8_t R30 = 0x30;
+ static constexpr uint8_t R31 = 0x31;
+ static constexpr uint8_t R32 = 0x32;
+ static constexpr uint8_t R33 = 0x33;
+ static constexpr uint8_t R34 = 0x34;
+ static constexpr uint8_t R35 = 0x35;
+ /* R36 RESERVED */
+ static constexpr uint8_t R37_PASSWORD_LOWER_BYTE_0 = 0x37;
+ static constexpr uint8_t R38_PASSWORD_UPPER_BYTE_1 = 0x38;
+ static constexpr uint8_t R39_COMMAND_CODES = 0x39;
+ static constexpr uint8_t R3A = 0x3A;
+ static constexpr uint8_t R3B = 0x3B;
+ static constexpr uint8_t R3C_VENDOR_ID_BYTE_0 = 0x3C;
+ static constexpr uint8_t R3D_VENDOR_ID_BYTE_1 = 0x3D;
+
+ /* ----- DIMM VENDOR REGION ----- */
+
+ /* R3E - R3F RESERVED */
+ static constexpr uint8_t R40_POWER_ON_SEQUENCE_CONFIG_1 = 0x40;
+ static constexpr uint8_t R41_POWER_ON_SEQUENCE_CONFIG_2 = 0x41;
+ static constexpr uint8_t R42_POWER_ON_SEQUENCE_CONFIG_3 = 0x42;
+ static constexpr uint8_t R43_POWER_ON_SEQUENCE_CONFIG_4 = 0x43;
+ /* R44 RESERVED */
+ static constexpr uint8_t R45_SWA_VOLTAGE_SETTING = 0x45;
+ static constexpr uint8_t R46 = 0x46;
+ static constexpr uint8_t R47_SWB_VOLTAGE_SETTING = 0x47;
+ static constexpr uint8_t R48 = 0x48;
+ static constexpr uint8_t R49_SWC_VOLTAGE_SETTING = 0x49;
+ static constexpr uint8_t R4A = 0x4A;
+ static constexpr uint8_t R4B_SWD_VOLTAGE_SETTING = 0x4B;
+ static constexpr uint8_t R4C = 0x4C;
+ static constexpr uint8_t R4D = 0x4D;
+ static constexpr uint8_t R4E = 0x4E;
+ static constexpr uint8_t R4F = 0x4F;
+ static constexpr uint8_t R50 = 0x50;
+ static constexpr uint8_t R51 = 0x51;
+ /* R52 - R57 RESERVED */
+ static constexpr uint8_t R58_POWER_OFF_SEQUENCE_CONFIG_1 = 0x58;
+ static constexpr uint8_t R59_POWER_OFF_SEQUENCE_CONFIG_2 = 0x59;
+ static constexpr uint8_t R5A_POWER_OFF_SEQUENCE_CONFIG_3 = 0x5A;
+ static constexpr uint8_t R5B_POWER_OFF_SEQUENCE_CONFIG_4 = 0x5B;
+ /* R5C RESERVED */
+ static constexpr uint8_t R5D = 0x5D;
+ static constexpr uint8_t R5E = 0x5E;
+ static constexpr uint8_t R5F_PRIMARY_INFERFACE_IO_TYPE = 0x5F;
+ /* R60 - R6C RESERVED */
+ static constexpr uint8_t R6D = 0x6D;
+ static constexpr uint8_t R6E = 0x6E;
+ /* R6F RESERVED */
+};
+
+#endif
diff --git a/src/import/chips/ocmb/common/include/pmic_regs_fld.H b/src/import/chips/ocmb/common/include/pmic_regs_fld.H
index 5531e0888..2eb348df9 100644
--- a/src/import/chips/ocmb/common/include/pmic_regs_fld.H
+++ b/src/import/chips/ocmb/common/include/pmic_regs_fld.H
@@ -22,3 +22,56 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
+
+///
+/// @file pmic_regs_fld.H
+/// @brief PMIC Register Fields
+///
+// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com>
+// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB
+
+#ifndef __PMIC_REGS_FLD__
+#define __PMIC_REGS_FLD__
+
+#include <lib/utils/pmic_consts.H>
+
+///
+/// @brief Register fields for PMIC devices
+/// @class pmicFields
+/// @tparam P pmic_product
+///
+template<mss::pmic::product P>
+struct pmicFields;
+
+///
+/// @brief Fields for JEDEC_COMPLIANT PMICs
+///
+template<>
+struct pmicFields<mss::pmic::product::JEDEC_COMPLIANT>
+{
+ static constexpr uint8_t R2F_SECURE_MODE = 0x02;
+ static constexpr uint8_t R32_VR_ENABLE = 0x07;
+ static constexpr uint8_t PMIC_DEVICE = 0x00;
+
+ static constexpr uint8_t SWA_SWB_PHASE_MODE_SELECT = 0x00;
+
+ static constexpr uint8_t SWA_VOLTAGE_RANGE = 0x05;
+ static constexpr uint8_t SWB_VOLTAGE_RANGE = 0x04;
+ static constexpr uint8_t SWC_VOLTAGE_RANGE = 0x03;
+ static constexpr uint8_t SWD_VOLTAGE_RANGE = 0x00;
+
+ static constexpr uint8_t SEQUENCE_ENABLE = 0x07;
+ static constexpr uint8_t SEQUENCE_SWA_ENABLE = 0x06;
+ static constexpr uint8_t SEQUENCE_SWB_ENABLE = 0x05;
+ static constexpr uint8_t SEQUENCE_SWC_ENABLE = 0x04;
+ static constexpr uint8_t SEQUENCE_SWD_ENABLE = 0x03;
+
+ static constexpr uint8_t VIN_BULK_INPUT_PWR_GOOD_STATUS = 0x07;
+
+ static constexpr uint8_t DELAY_FLD_LENGTH = 3;
+};
+
+#endif
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