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| author | Claus Michael Olsen <cmolsen@us.ibm.com> | 2018-01-04 21:24:06 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-02-07 17:34:26 -0500 |
| commit | 975d6f745c830cb54cff7a2cf751d57b44db83c0 (patch) | |
| tree | 205fe301e8f064fe93de033ce5df9bc7cc587d03 /src/import/chips/common | |
| parent | 29b02eface8422e47d7909f24377594b83bc9029 (diff) | |
| download | talos-hostboot-975d6f745c830cb54cff7a2cf751d57b44db83c0.tar.gz talos-hostboot-975d6f745c830cb54cff7a2cf751d57b44db83c0.zip | |
Moving DD specific ring coord from TOR to XIP (step 2)
Step 2 - Producing XIP coordinated DD packaging of the TOR
ring sections.
- Updated ring_apply to produce N number of DD specific .rings
ring sections and which is then assembled using the DD
container API.
Key_Cronus_Test=XIP_REGRESS
HW-ImageBuild-Prereq=42751
- 42751 must be fully merged in Cronus and HB before this
commit (51511) can be merged. This is to avoid a Coreq
situation.
CMVC-Prereq: 1043942
Change-Id: I45a73848f3e8683aae9dcc26fcdf282259c38fcc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51511
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51520
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/common')
| -rw-r--r-- | src/import/chips/common/utils/imageProcs/common_ringId.H | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H index a042d5d50..74edacb0f 100644 --- a/src/import/chips/common/utils/imageProcs/common_ringId.H +++ b/src/import/chips/common/utils/imageProcs/common_ringId.H @@ -49,6 +49,7 @@ typedef uint8_t PpeType_t; // Type for PpeType typedef uint8_t ChipType_t; // Type for ChipType enum typedef uint8_t RingType_t; // Type for RingType enum typedef uint8_t RingVariant_t; // Type for RingVariant enum +typedef uint8_t RingBlockType_t; // Type for RingBlockType enum, e.g. GET_SINGLE_RING typedef uint32_t TorCpltOffset_t; // Type for offset value to chiplet's CMN or INST section typedef uint8_t myBoolean_t; // false:0, true:1, undefined:UNDEFINED_BOOLEAN @@ -57,6 +58,7 @@ typedef uint8_t myBoolean_t; // false:0, true:1, undefined:UNDEFINED_BOOL #define INVALID_CHIPLET_TYPE (ChipletType_t)0xff #define UNDEFINED_PPE_TYPE (PpeType_t)0xff #define UNDEFINED_CHIP_TYPE (ChipType_t)0xff +#define UNDEFINED_RING_BLOCK_TYPE (RingBlockType_t)0xff; #define MAX_TOR_RING_OFFSET (uint16_t)(256*256-1) // Max val of uint16 #define MAX_RING_NAME_LENGTH (uint8_t)50 #define UNDEFINED_DD_LEVEL (uint8_t)0xff @@ -128,7 +130,8 @@ typedef uint16_t TorRingOffset_t; // Offset value to actual ring //#define TOR_VERSION 1 // Initial version. Large RS4 header. //#define TOR_VERSION 2 // Reduced RS4 header. //#define TOR_VERSION 3 // Added TOR magic header. -#define TOR_VERSION 4 // TOR API code restructuring. +//#define TOR_VERSION 4 // TOR API code restructuring. +#define TOR_VERSION 5 // Removed TOR-level DD handling. // TOR Magic values for top-level TOR ringSection and sub-ringSections enum TorMagicNum @@ -242,6 +245,16 @@ enum RingType ALLRING = 2 }; +enum RingBlockType +{ + GET_SINGLE_RING = 0x00, +#ifdef TORV3_SUPPORT + GET_DD_LEVEL_RINGS = 0x01, +#endif + GET_PPE_LEVEL_RINGS = 0x02, + PUT_SINGLE_RING = 0x03 +}; + typedef struct { // This is the chiplet-ID of the first instance of the Chiplet |
