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| author | Glenn Miles <milesg@ibm.com> | 2019-04-30 14:47:08 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-07 10:20:17 -0500 |
| commit | a2ee107c441a4aad0744897f3dbc0d883dbf6f4e (patch) | |
| tree | edf90d37fd6f904f8dd1e1dc3e3540ef9eae99c8 /src/build/citest/etc/simbuild | |
| parent | 6390bd34536aa14d814ab07390ef679a1aeff2b2 (diff) | |
| download | talos-hostboot-a2ee107c441a4aad0744897f3dbc0d883dbf6f4e.tar.gz talos-hostboot-a2ee107c441a4aad0744897f3dbc0d883dbf6f4e.zip | |
Update simbuild for axone simics bringup
The XML for the RAM1 register was not being parsed correctly
resulting in too few registers being allocated in
uchip_regs.chip not defining all of the registers. This
latest build adds those registers manually until the parser
can be fixed. This build also sets the POR values for the
RAM1 registers.
Also changes OCMB I2C addresses to 0x40
Change-Id: Icd2df80874200741d82fc152cb4b8bdbc75c5bed
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76764
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest/etc/simbuild')
| -rw-r--r-- | src/build/citest/etc/simbuild | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/build/citest/etc/simbuild b/src/build/citest/etc/simbuild index 9b0bb11dd..59bc920a4 100644 --- a/src/build/citest/etc/simbuild +++ b/src/build/citest/etc/simbuild @@ -1 +1 @@ -/gsa/ausgsa/projects/h/hostboot/simbuild/04_26_19_57d024_simics.tar.gz
\ No newline at end of file +/gsa/ausgsa/projects/h/hostboot/simbuild/05_01_19_a9c398_simics.tar.gz |
