Secureboot memory layout support.

    * Start kernel in 1/4 cache mode per Secureboot.
    * Copy Secureboot header for base image for later use.
    * Blind-purge bottom half of cache.
    * Add bottom of cache into memory maps for 1/2 cache mode.

RTC: 64762
Change-Id: I1b45f30a2d45c9709d4fd486cfe0ca2ce86b051c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3773
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/src/build/citest/etc/patches/p8_ex_l3purge.act b/src/build/citest/etc/patches/p8_ex_l3purge.act
new file mode 100644
index 000000000..3d540b662
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_ex_l3purge.act
@@ -0,0 +1,9 @@
+
+# Indicate purge complete whenever a purge operation is requested.
+CAUSE_EFFECT CHIPLETS ex{
+    LABEL=[L3 PURGE REGISTER]
+    WATCH=[REG(MYCHIPLET,0x0001080e)]
+
+    CAUSE: TARGET=[REG(MYCHIPLET,0x0001080e)] OP=[BIT,ON] BIT=[0]
+    EFFECT: TARGET=[REG(MYCHIPLET,0x0001080e)] OP=[BIT,OFF] BIT=[0]
+}