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| author | Patrick Williams <iawillia@us.ibm.com> | 2013-03-26 11:23:47 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-06-14 09:09:09 -0500 |
| commit | e89e72d2f8a2efe86acad95ed0769aa7a8fe64ae (patch) | |
| tree | 5541b72a698f58757ab2fe36b1a264fff6bcb3a2 /src/build | |
| parent | 92255af10842c672550a586d342c67ac1c7e11ca (diff) | |
| download | talos-hostboot-e89e72d2f8a2efe86acad95ed0769aa7a8fe64ae.tar.gz talos-hostboot-e89e72d2f8a2efe86acad95ed0769aa7a8fe64ae.zip | |
Secureboot memory layout support.
* Start kernel in 1/4 cache mode per Secureboot.
* Copy Secureboot header for base image for later use.
* Blind-purge bottom half of cache.
* Add bottom of cache into memory maps for 1/2 cache mode.
RTC: 64762
Change-Id: I1b45f30a2d45c9709d4fd486cfe0ca2ce86b051c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3773
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/build')
| -rw-r--r-- | src/build/citest/etc/patches/p8_ex_l3purge.act | 9 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/patchlist.txt | 7 | ||||
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 8 |
3 files changed, 22 insertions, 2 deletions
diff --git a/src/build/citest/etc/patches/p8_ex_l3purge.act b/src/build/citest/etc/patches/p8_ex_l3purge.act new file mode 100644 index 000000000..3d540b662 --- /dev/null +++ b/src/build/citest/etc/patches/p8_ex_l3purge.act @@ -0,0 +1,9 @@ + +# Indicate purge complete whenever a purge operation is requested. +CAUSE_EFFECT CHIPLETS ex{ + LABEL=[L3 PURGE REGISTER] + WATCH=[REG(MYCHIPLET,0x0001080e)] + + CAUSE: TARGET=[REG(MYCHIPLET,0x0001080e)] OP=[BIT,ON] BIT=[0] + EFFECT: TARGET=[REG(MYCHIPLET,0x0001080e)] OP=[BIT,OFF] BIT=[0] +} diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt index afccedee0..c605c55de 100644 --- a/src/build/citest/etc/patches/patchlist.txt +++ b/src/build/citest/etc/patches/patchlist.txt @@ -14,5 +14,8 @@ New version of proc_a_x_pll HW procedure requires additional actions src/build/citest/etc/patches/s1.act_proc_a_x_pll_patch - CoReq: N/A - - +Add action for L3 purge register. +-RTC: 67762 +-CMVC: 876083 +-Files: p8_ex_l3purge.act +-Coreq: None diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index d335f723b..54a80b8a5 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -32,3 +32,11 @@ #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $HOSTBOOTROOT/src/build/citest/etc/patches/my_patch_File +echo "+++ Updating actions for Blind Purge (CMVC 876083)" +mkdir -p $sb/simu/data/cec-chip +cp $BACKING_BUILD/src/simu/data/cec-chip/p8_ex.act $sb/simu/data/cec-chip +cp $BACKING_BUILD/src/simu/data/cec-chip/s1_ex.act $sb/simu/data/cec-chip +cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_ex_l3purge.act >> \ + $sb/simu/data/cec-chip/p8_ex.act +cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_ex_l3purge.act >> \ + $sb/simu/data/cec-chip/s1_ex.act |
