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author | crgeddes <crgeddes@us.ibm.com> | 2016-07-26 11:40:30 -0500 |
---|---|---|
committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-08-25 14:50:15 -0400 |
commit | b0bf18528f97ecef49ff27fd4715b2d2a50ad5ba (patch) | |
tree | c62489d62c413e523e72e3a5559d629165078c08 /src/build/buildpnor/defaultPnorLayout.xml | |
parent | 1400bea75a6bbd2083a8b39095470102479c8514 (diff) | |
download | talos-hostboot-b0bf18528f97ecef49ff27fd4715b2d2a50ad5ba.tar.gz talos-hostboot-b0bf18528f97ecef49ff27fd4715b2d2a50ad5ba.zip |
Update Bootloader to handle moving the TOC of PNOR around
Moved 1 of the PNOR TOCs from 0x8000 to TOP_OF_FLASH - 64KB.
Updated bootloader and pnor access code to handle new toc
location. Update the defaultPnorLayout to reflect these changes
Also added a FSP default pnor xml that will generate a 128 MB
image for FSP boxes to use.
RTC: 154286
Change-Id: I0253590299ff9714b0d5ab12a02ac9d653b115fa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27461
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/build/buildpnor/defaultPnorLayout.xml')
-rw-r--r-- | src/build/buildpnor/defaultPnorLayout.xml | 59 |
1 files changed, 29 insertions, 30 deletions
diff --git a/src/build/buildpnor/defaultPnorLayout.xml b/src/build/buildpnor/defaultPnorLayout.xml index ccc84fece..04c347ff1 100644 --- a/src/build/buildpnor/defaultPnorLayout.xml +++ b/src/build/buildpnor/defaultPnorLayout.xml @@ -25,6 +25,7 @@ <!-- Layout Description <metadata> Element -> Contains high-level information about the PNOR layout. + <chipSize> -> Size of the chip that the pnor image will reside on <imageSize> -> Size of PNOR image in bytes. <blockSize> -> size of erase blocks in bytes. <tocSize> -> size of each partition table @@ -65,21 +66,31 @@ Layout Description <pnor> <metadata> <imageSize>0x4000000</imageSize> + <chipSize>0x4000000</chipSize> <blockSize>0x1000</blockSize> <tocSize>0x8000</tocSize> <!--TODO: RTC 123734 - remove side offsets once hwsv implements new layout--> - <sideAOffset>0x0</sideAOffset> - <sideBOffset>0x8000</sideBOffset> - <arrangement>A-B-D</arrangement> + <sideAOffset>0x3FF0000</sideAOffset> + <sideBOffset>0x0</sideBOffset> + <arrangement>A-D-B</arrangement> <side> <id>B</id> </side> </metadata> <section> + <description>Hostboot Base (576K)</description> + <eyeCatch>HBB</eyeCatch> + <physicalOffset>0x8000</physicalOffset> + <physicalRegionSize>0x90000</physicalRegionSize> + <sha512Version/> + <side>sideless</side> + <ecc/> + </section> + <section> <description>Hostboot Error Logs (144K)</description> <eyeCatch>HBEL</eyeCatch> - <physicalOffset>0x10000</physicalOffset> + <physicalOffset>0x98000</physicalOffset> <physicalRegionSize>0x24000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -87,7 +98,7 @@ Layout Description <section> <description>Guard Data (20K)</description> <eyeCatch>GUARD</eyeCatch> - <physicalOffset>0x58000</physicalOffset> + <physicalOffset>0xBC000</physicalOffset> <physicalRegionSize>0x5000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -95,7 +106,7 @@ Layout Description <section> <description>Hostboot Data (1.125M)</description> <eyeCatch>HBD</eyeCatch> - <physicalOffset>0x5D000</physicalOffset> + <physicalOffset>0xC1000</physicalOffset> <physicalRegionSize>0x120000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -105,7 +116,7 @@ Layout Description <description>DIMM JEDEC (288K)</description> <eyeCatch>DJVPD</eyeCatch> <!--NOTE: MUST update standalone.simics if offset changes --> - <physicalOffset>0x17D000</physicalOffset> + <physicalOffset>0x1E1000</physicalOffset> <physicalRegionSize>0x48000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -114,7 +125,7 @@ Layout Description <description>Module VPD (576K)</description> <eyeCatch>MVPD</eyeCatch> <!--NOTE: MUST update standalone.simics if offset changes --> - <physicalOffset>0x1C5000</physicalOffset> + <physicalOffset>0x229000</physicalOffset> <physicalRegionSize>0x90000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -123,7 +134,7 @@ Layout Description <description>Centaur VPD (288K)</description> <eyeCatch>CVPD</eyeCatch> <!--NOTE: MUST update standalone.simics if offset changes --> - <physicalOffset>0x255000</physicalOffset> + <physicalOffset>0x2B9000</physicalOffset> <physicalRegionSize>0x48000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -131,7 +142,7 @@ Layout Description <section> <description>Hostboot Extended image (11MB w/o ECC)</description> <eyeCatch>HBI</eyeCatch> - <physicalOffset>0x29D000</physicalOffset> + <physicalOffset>0x301000</physicalOffset> <physicalRegionSize>0xC60000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -151,7 +162,7 @@ Layout Description <section> <description>SBE-IPL (Staging Area) (288K)</description> <eyeCatch>SBE</eyeCatch> - <physicalOffset>0xEFD000</physicalOffset> + <physicalOffset>0xF61000</physicalOffset> <physicalRegionSize>0x48000</physicalRegionSize> <sha512perEC/> <side>sideless</side> @@ -160,7 +171,7 @@ Layout Description <section> <description>HCODE Ref Image (1.125MB)</description> <eyeCatch>HCODE</eyeCatch> - <physicalOffset>0xF45000</physicalOffset> + <physicalOffset>0xFA9000</physicalOffset> <physicalRegionSize>0x120000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -169,7 +180,7 @@ Layout Description <section> <description>Hostboot Runtime Services for Sapphire (4.5MB)</description> <eyeCatch>HBRT</eyeCatch> - <physicalOffset>0x1065000</physicalOffset> + <physicalOffset>0x10C9000</physicalOffset> <physicalRegionSize>0x480000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -178,7 +189,7 @@ Layout Description <section> <description>Payload (21.375MB)</description> <eyeCatch>PAYLOAD</eyeCatch> - <physicalOffset>0x14E5000</physicalOffset> + <physicalOffset>0x1549000</physicalOffset> <physicalRegionSize>0x1560000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -186,7 +197,7 @@ Layout Description <section> <description>Special PNOR Test Space (36K)</description> <eyeCatch>TEST</eyeCatch> - <physicalOffset>0x2A45000</physicalOffset> + <physicalOffset>0x2AA9000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <testonly/> <side>sideless</side> @@ -195,7 +206,7 @@ Layout Description <section> <description>Special PNOR Test Space (36K)</description> <eyeCatch>TESTRO</eyeCatch> - <physicalOffset>0x2A4E000</physicalOffset> + <physicalOffset>0x2AB2000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <side>sideless</side> <testonly/> @@ -206,27 +217,15 @@ Layout Description <section> <description>Hostboot Bootloader (22.5K)</description> <eyeCatch>HBBL</eyeCatch> - <physicalOffset>0x2A57000</physicalOffset> + <physicalOffset>0x2ABB000</physicalOffset> <physicalRegionSize>0x6000</physicalRegionSize> <side>sideless</side> <ecc/> </section> <section> - <description>Hostboot Base (576K)</description> - <!--NOTE: MUST update standalone.simics if offset changes --> - <!--NOTE: HBB must be at pnorSize-0x99000 for a new proc - part to be bootable --> - <eyeCatch>HBB</eyeCatch> - <physicalOffset>0x3F67000</physicalOffset> - <physicalRegionSize>0x90000</physicalRegionSize> - <sha512Version/> - <side>sideless</side> - <ecc/> - </section> - <section> <description>Global Data (36K)</description> <eyeCatch>GLOBAL</eyeCatch> - <physicalOffset>0x3FF7000</physicalOffset> + <physicalOffset>0x2AC1000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <side>sideless</side> <ecc/> |