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| author | Dan Crowell <dcrowell@us.ibm.com> | 2017-10-01 16:09:56 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-29 12:03:50 -0400 |
| commit | 90eaed6f430c88eb0127ce47671bd80b21f35433 (patch) | |
| tree | 9bc4aaa5cfb416f0da69386fb595e92513e0d1b7 /src/bootloader | |
| parent | 284cebd97cf08d42ba2f4caa8779bf47494fcc20 (diff) | |
| download | talos-hostboot-90eaed6f430c88eb0127ce47671bd80b21f35433.tar.gz talos-hostboot-90eaed6f430c88eb0127ce47671bd80b21f35433.zip | |
Force checkstops for unhandled machine checks
Default MSR[ME]=0 during initial boot for bootloader and
hostboot kernel
Once the xscom address range has been mapped in, enable the
machine check handler to force a checkstop and set MSR[ME]=1
to allow regular machine check handling
CQ: SW401402
Change-Id: I104e39465e61b3b19d5c073e71271102711ae54f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47179
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/bootloader')
| -rw-r--r-- | src/bootloader/bl_start.S | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/bootloader/bl_start.S b/src/bootloader/bl_start.S index 0110c2401..0780575d6 100644 --- a/src/bootloader/bl_start.S +++ b/src/bootloader/bl_start.S @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2017 +# Contributors Listed Below - COPYRIGHT 2015,2018 # [+] Google Inc. # [+] International Business Machines Corp. # @@ -74,11 +74,10 @@ _start: ;// Set thread priority high. or 2,2,2 - ;// Clear MSR[TA] (bit 1) and enable MSR[ME] (bit 51). + ;// Clear MSR[TA] (bit 1) mfmsr r2 rldicl r2,r2,1,1 ;// Clear bit 1 - result [1-63,0] rotrdi r2,r2,1 ;// Rotate right 1 - result [0,63] - ori r2,r2,4096 ;// Set bit 51 ;// Set up SRR0 / SRR1 to enable new MSR. mtsrr1 r2 li r2, _start_postmsr@l |
