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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml $ -->
<!-- -->
<!-- IBM CONFIDENTIAL -->
<!-- -->
<!-- COPYRIGHT International Business Machines Corp. 2012,2013 -->
<!-- -->
<!-- p1 -->
<!-- -->
<!-- Object Code Only (OCO) source materials -->
<!-- Licensed Internal Code Source Materials -->
<!-- IBM HostBoot Licensed Internal Code -->
<!-- -->
<!-- The source code for this program is not published or otherwise -->
<!-- divested of its trade secrets, irrespective of what has been -->
<!-- deposited with the U.S. Copyright Office. -->
<!-- -->
<!-- Origin: 30 -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: p8_pmc_errors.xml,v 1.6 2013/08/02 19:15:41 stillgs Exp $ -->
<!-- Error definitions for proc_pmc_init procedure -->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_CODE_BAD_MODE</rc>
<description>Unknown mode passed to proc_pmc_init.</description>
<ffdc>MODE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCINIT_TIMEOUT</rc>
<description>time out in polling some register condition.</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_SPIVID_CONFIG_ERROR</rc>
<description>Master target does not have SPIVID ports enabled: check the configuration setup.</description>
<ffdc>MASTER_TARGET</ffdc>
<ffdc>ATTR_SPIVID_PORT_ENABLE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_FIR_ERROR</rc>
<description>Either both targets are masters or slaves in reset mode.</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR</rc>
<description>Error found in DCM installment..</description>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_MASTER_CONFIG_ERROR</rc>
<description>MasterPMC bit of Master PMC is not set.</description>
<ffdc>MASTERPMCMODE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_SLAVE_CONFIG_ERROR</rc>
<description>MasterPMC bit of Slave PMC is not set.</description>
<ffdc>SLAVEPMCMODE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR</rc>
<description>Master is enabled with interchip interface but slave is not.</description>
<ffdc>MASTERPMCMODE</ffdc>
<ffdc>SLAVEPMCMODE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROCPM_PMC_FW_MODE_ERROR</rc>
<description>Master is enabled with FW pstate mode but slave is not </description>
<ffdc>MASTERPMCMODE</ffdc>
<ffdc>SLAVEPMCMODE</ffdc>
</hwpError>
<!-- *********************************************************************** -->
</hwpErrors>
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