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| author | Dan Crowell <dcrowell@us.ibm.com> | 2016-09-06 09:56:35 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-28 18:54:58 -0400 |
| commit | 8bb29c96ea954622641c40de91394f1fe3f9272d (patch) | |
| tree | 8090d872d878035e32fc929fce4f89f4db996d86 | |
| parent | 4d0306e4803ef8cff2b275ccdf879c8ebc096826 (diff) | |
| download | talos-hostboot-8bb29c96ea954622641c40de91394f1fe3f9272d.tar.gz talos-hostboot-8bb29c96ea954622641c40de91394f1fe3f9272d.zip | |
Add new pci lane equalization attributes
Add PROC_PCIE_LANE_EQUALIZATION_GEN3
Add PROC_PCIE_LANE_EQUALIZATION_GEN4
Deprecate PROC_PCIE_LANE_EQUALIZATION
Change-Id: I3ed610d25e0df151c0ff3c8ee0b6bb380a57102a
RTC: 160416
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29264
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types.xml | 58 | ||||
| -rwxr-xr-x | src/usr/targeting/common/xmltohb/target_types.xml | 3 |
2 files changed, 58 insertions, 3 deletions
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index fe929fbd3..6db5cebed 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -16927,7 +16927,7 @@ Measured in GB</description> <readable/> </attribute> -<attribute> +<attribute><!-- Deprecated : @todo-Remove with RTC:160417 --> <id>PROC_PCIE_LANE_EQUALIZATION</id> <description>PCIE Lane Equalization values for each PHB Creator: MRW @@ -16956,7 +16956,7 @@ Measured in GB</description> <array>4,32</array> </simpleType> <persistency>non-volatile</persistency> - <readable/> + <readable/> </attribute> <attribute> @@ -31543,4 +31543,58 @@ Measured in GB</description> </hwpfToHbAttrMap> </attribute> +<attribute> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> + <description>PCIE Lane Equalization values for each PHB + Creator: MRW + Purpose: Holds settings which are loaded into the HW to optimize the + PCIE lane signal eye between the chips + PCIE Gen3 endpoints + Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ + value for each of its 16 lanes. Each value is a uint16 formatted as + follows: + Bit 0:3 - up_rx_hint (bit 0 reserved) + Bit 4:7 - up_tx_preset + Bit 8:11 - dn_rx_hint (bit 0 reserved) + Bit 12:15 - dn_tx_preset + </description> + <simpleType> + <uint16_t><default> + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777 + </default></uint16_t> + <array>16</array><!-- Lane --> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> + +<attribute> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> + <description>PCIE Lane Equalization values for each PHB + Creator: MRW + Purpose: Holds settings which are loaded into the HW to optimize the + PCIE lane signal eye between the chips + PCIE Gen4 endpoints + Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ + value for each of its 16 lanes. Each value is a uint16 formatted as + follows: + Bit 0:3 - up_rx_hint (bit 0 reserved) + Bit 4:7 - up_tx_preset + Bit 8:11 - dn_rx_hint (bit 0 reserved) + Bit 12:15 - dn_tx_preset + </description> + <simpleType> + <uint16_t><default> + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777 + </default></uint16_t> + <array>16</array><!-- Lane --> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 864b1412b..6eea3d855 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -2038,7 +2038,8 @@ <attribute><id>PROC_PCIE_BAR_BASE_ADDR</id></attribute> <attribute><id>PROC_PCIE_BAR_SIZE</id></attribute> <attribute><id>CDM_DOMAIN</id><default>IO</default></attribute> - + <attribute><id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id></attribute> + <attribute><id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id></attribute> </targetType> |
