Change PHY to use GPO, RLO, WLO from VPD

  Remove extra slew calibration files
  Update VBU VPD

CMVC-Prereq: 1005024
Change-Id: I5681135761a19bf9223a1e63ed5a2d47d0944dc8
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29227
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29228
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

17 files changed, 475 insertions, 697 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
index 88024e7a0..3939e7dc8 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
@@ -270,28 +270,50 @@ constexpr uint64_t twlmrd()
 }
 
 ///
-/// @brief Calculate TWLO_TWLOE
+/// @brief Mode Register Set command update delay
 /// @tparam T fapi2::TargetType of the target used to calculate cycles from ns
-/// @param[in] i_target the target used to get DIMM clocks
-/// @return uint64_t, TWLO_TWLOE in cycles
+/// @param[in] i_target the target used to get clocks
+/// @return max(24nCK,15ns) in clocks
 ///
 template< fapi2::TargetType T >
-inline uint64_t twlo_twloe(const fapi2::Target<T>& i_target)
+inline uint64_t tmod( const fapi2::Target<T>& i_target )
 {
-    return 12 + mss::ns_to_cycles(i_target, tWLO - tWLOE);
+    // Per DDR4 Full spec update (79-4A) - timing requirements
+    return mss::max_ck_ns( i_target, 24, 15 );
 }
 
 ///
-/// @brief Mode Register Set command update delay
+/// @brief Calculate TWLO_TWLOE
 /// @tparam T fapi2::TargetType of the target used to calculate cycles from ns
-/// @param[in] i_target the target used to get clocks
-/// @return max(24nCK,15ns) in clocks
+/// @param[in] i_target the target used to get DIMM clocks
+/// @return uint64_t, TWLO_TWLOE in cycles
 ///
 template< fapi2::TargetType T >
-inline uint64_t tmod( const fapi2::Target<T>& i_target )
+inline uint64_t twlo_twloe(const fapi2::Target<T>& i_target)
 {
-    // Per DDR4 Full spec update (79-4A) - timing requirements
-    return mss::max_ck_ns( i_target, 24, 15 );
+    // From mthe PHY databook:
+    // 12 + std::max((twldqsen - tmod), (twlo - twlow))
+    //    + longest DQS delay in clocks (rounded up) + longest DQ delay in clocks (rounded up)
+    // Magic numbers taken from talking with Anuwat (twloe) and reviewing the Centaur code (ldq/ldqs)
+    constexpr uint64_t l_dq_ck = 1;
+    constexpr uint64_t l_dqs_ck = 1;
+    uint8_t l_wlo_ck = 0;
+    uint64_t l_wloe_ck = mss::ns_to_cycles(i_target, 2);
+    uint64_t l_twlo_twloe = 0;
+
+    FAPI_TRY( mss::vpd_mr_dphy_wlo(i_target, l_wlo_ck) );
+
+    // TODO RTC:160356 This changes if wlo is signed, which it's not but I wonder if it should
+    // be ... (the PHY register is.) It changes because we need to round up to 0 if needed.
+    l_twlo_twloe = 12 + std::max( (twldqsen() + tmod(i_target)), (l_wlo_ck + l_wloe_ck) ) + l_dq_ck + l_dqs_ck;
+    FAPI_INF("twlo_twloe %d for %s", l_twlo_twloe, mss::c_str(i_target));
+    return l_twlo_twloe;
+
+fapi_try_exit:
+    // We're in deep horseradish if we can't get wlo
+    FAPI_ERR("failed to calculate twlo_twloe for %s", mss::c_str(i_target));
+    fapi2::Assert(false);
+    return 0;
 }
 
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index b3a7cdb02..685b43d58 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -10765,170 +10765,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_VPD_RLO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM
-/// associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C
-/// and 252 bits 4:7 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
-{
-    uint8_t l_value[2];
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_RLO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
-    o_value = l_value[mss::index(i_target)];
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_RLO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_RLO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D.1)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM
-/// associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C
-/// and 252 bits 4:7 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_rlo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
-{
-    uint8_t l_value[2];
-    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_RLO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
-    o_value = l_value[mss::index(l_mca)];
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_RLO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_RLO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[out] uint8_t* memory to store the value
-/// @note Generated by gen_accessors.pl generateParameters (E)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM
-/// associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C
-/// and 252 bits 4:7 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
-{
-    if (o_array == nullptr)
-    {
-        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
-        return fapi2::FAPI2_RC_INVALID_PARAMETER;
-    }
-
-    uint8_t l_value[2];
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_RLO, i_target, l_value) );
-    memcpy(o_array, &l_value, 2);
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_RLO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_WLO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM
-/// associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C
-/// and 252 bits 0:3 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
-{
-    uint8_t l_value[2];
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_WLO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
-    o_value = l_value[mss::index(i_target)];
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_WLO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_WLO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D.1)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM
-/// associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C
-/// and 252 bits 0:3 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_wlo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
-{
-    uint8_t l_value[2];
-    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_WLO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
-    o_value = l_value[mss::index(l_mca)];
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_WLO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_WLO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[out] uint8_t* memory to store the value
-/// @note Generated by gen_accessors.pl generateParameters (E)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM
-/// associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C
-/// and 252 bits 0:3 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
-{
-    if (o_array == nullptr)
-    {
-        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
-        return fapi2::FAPI2_RC_INVALID_PARAMETER;
-    }
-
-    uint8_t l_value[2];
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_WLO, i_target, l_value) );
-    memcpy(o_array, &l_value, 2);
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_WLO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
 /// @brief ATTR_EFF_DRAM_MODULE_BUS_WIDTH getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
@@ -16344,85 +16180,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_VPD_GPO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM
-/// associated with port A. Bytes 125 for port B, 189 for port C and 253 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_gpo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
-{
-    uint8_t l_value[2];
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_GPO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
-    o_value = l_value[mss::index(i_target)];
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_GPO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_GPO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D.1)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM
-/// associated with port A. Bytes 125 for port B, 189 for port C and 253 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_gpo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
-{
-    uint8_t l_value[2];
-    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_GPO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
-    o_value = l_value[mss::index(l_mca)];
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_GPO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_VPD_GPO getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[out] uint8_t* memory to store the value
-/// @note Generated by gen_accessors.pl generateParameters (E)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM
-/// associated with port A. Bytes 125 for port B, 189 for port C and 253 for port
-/// D
-///
-inline fapi2::ReturnCode vpd_gpo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
-{
-    if (o_array == nullptr)
-    {
-        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
-        return fapi2::FAPI2_RC_INVALID_PARAMETER;
-    }
-
-    uint8_t l_value[2];
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_VPD_GPO, i_target, l_value) );
-    memcpy(o_array, &l_value, 2);
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_VPD_GPO: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
 /// @brief ATTR_EFF_DRAM_TDQS getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
index c43c981e4..8bdad45ae 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C
@@ -65,6 +65,13 @@ const std::vector<uint64_t> adr32sTraits<fapi2::TARGET_TYPE_MCA>::DUTY_CYCLE_DIS
     MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1
 };
 
+// Definition of the ADR32S write clock static offset registers
+const std::vector<uint64_t> adr32sTraits<fapi2::TARGET_TYPE_MCA>::PR_STATIC_OFFSET_REG =
+{
+    MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0,
+    MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1,
+};
+
 namespace adr32s
 {
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H
index ae650302f..1e2ee1e8e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H
@@ -39,9 +39,10 @@
 #include <fapi2.H>
 #include <p9_mc_scom_addresses.H>
 #include <p9_mc_scom_addresses_fld.H>
-
+#include <lib/mss_attribute_accessors.H>
 #include <lib/shared/mss_const.H>
 #include <lib/utils/scom.H>
+#include <lib/utils/find.H>
 
 namespace mss
 {
@@ -82,6 +83,7 @@ class adr32sTraits<fapi2::TARGET_TYPE_MCA>
         static const std::vector<uint64_t> DLL_CNFG_REG;
         static const std::vector<uint64_t> OUTPUT_DRIVER_REG;
         static const std::vector<uint64_t> DUTY_CYCLE_DISTORTION_REG;
+        static const std::vector<uint64_t> PR_STATIC_OFFSET_REG;
 
         // This fellow is needed for the reset_dcd template, so he's more like a real trait.
         // Default starting place for duty cycle distortion algorithm
@@ -113,6 +115,9 @@ class adr32sTraits<fapi2::TARGET_TYPE_MCA>
             DCD_CONTROL_DLL_CORRECT_EN = MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN,
             DCD_CONTROL_DLL_ITER_A = MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A,
             DCD_CONTROL_DLL_COMPARE_OUT = MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_COMPARE_OUT,
+
+            TSYS_ADR = MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS,
+            TSYS_ADR_LEN = MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS_LEN,
         };
 
 };
@@ -341,7 +346,73 @@ fapi2::ReturnCode dcd_cal_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i
 ///
 fapi2::ReturnCode duty_cycle_distortion_calibration( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
 
-} // close namespace adr
+///
+/// @brief Read tsys_adr
+/// @tparam I ADR32S instance e.g., 0 or 1 for a 64 bit implementation of the PHY
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adr32sTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adr32sTraits<T> >
+inline fapi2::ReturnCode read_tsys_adr( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range");
+    FAPI_TRY( mss::getScom(i_target, TT::PR_STATIC_OFFSET_REG[I], o_data) );
+    FAPI_INF("tsys_adr adrs32%d: 0x%016lx", I, o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write tsys_adr
+/// @tparam I ADR32S instance e.g., 0 or 1 for a 64 bit implementation of the PHY
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adr32sTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = adr32sTraits<T> >
+inline fapi2::ReturnCode write_tsys_adr( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    static_assert( I < TT::ADR32S_COUNT, "adr32s instance out of range");
+    FAPI_INF("tsys_adr adr32s%d: 0x%016lx", I, i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::PR_STATIC_OFFSET_REG[I], i_data) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset tsys_adr
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to adr32sTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = adr32sTraits<T> >
+inline fapi2::ReturnCode reset_tsys_adr( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+    uint8_t l_tsys_adr = 0;
+
+    FAPI_TRY( mss::vpd_mr_tsys_adr(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target), l_tsys_adr) );
+    l_data.insertFromRight<TT::TSYS_ADR, TT::TSYS_ADR_LEN>(l_tsys_adr);
+
+    for (const auto r : TT::PR_STATIC_OFFSET_REG)
+    {
+        // TODO RTC:160358 Suspect duplicated scoms in ddr initfile
+        FAPI_INF("reset tsys_adr 0x%016lx: 0x%016lx", r, l_data);
+        FAPI_TRY( mss::putScom(i_target, r, l_data) );
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+} // close namespace adr32s
 
 } // close namespace mss
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 78dbc776e..d54ba3a28 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -550,93 +550,6 @@ fapi_try_exit:
 }
 
 ///
-/// @brief Setup the PC CONFIG0 register
-/// @tparam T the fapi2::TargetType
-/// @param[in] i_target the target (MCA or MBA?)
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template<>
-fapi2::ReturnCode set_pc_config0(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
-{
-    fapi2::buffer<uint64_t> l_data;
-    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) );
-
-    // Note: This needs to get the DRAM gen from an attribute. - 0x1 is DDR4 Note for Nimbus PHY
-    // this is ignored and hard-wired to DDR4, per John Bialas 10/15 BRS
-    // repurposed to pda_enable_override, so zero per John Bialas 4/16 JJM
-    l_data.insertFromRight<MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL, MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL_LEN>(0x0);
-
-    l_data.setBit<MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION>();
-    l_data.setBit<MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP>();
-
-    FAPI_INF("phy pc_config0 0x%0llx", l_data);
-    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
-/// @brief Setup the PC CONFIG1 register
-/// @tparam T the fapi2::TargetType
-/// @param[in] i_target <the target (MCA or MBA?)
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template<>
-fapi2::ReturnCode set_pc_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
-{
-    // Static table of PHY config values for MEMORY_TYPE.
-    // [EMPTY, RDIMM, CDIMM, or LRDIMM][EMPTY, DDR3 or DDR4]
-    static const uint64_t memory_type[4][3] =
-    {
-        { 0, 0,     0     },  // Empty, never really used.
-        { 0, 0b001, 0b101 },  // RDIMM
-        { 0, 0b000, 0b000 },  // CDIMM
-        { 0, 0b011, 0b111 },  // LRDIMM
-    };
-
-    fapi2::buffer<uint64_t> l_data;
-
-    uint8_t l_rlo = 0;
-    uint8_t l_wlo = 0;
-    uint8_t l_dram_gen[MAX_DIMM_PER_PORT]    = {0};
-    uint8_t l_dimm_type[MAX_DIMM_PER_PORT]   = {0};
-    uint8_t l_type_index = 0;
-    uint8_t l_gen_index = 0;
-
-    FAPI_TRY( mss::vpd_rlo(i_target, l_rlo) );
-    FAPI_TRY( mss::vpd_wlo(i_target, l_wlo) );
-    FAPI_TRY( mss::eff_dram_gen(i_target, &(l_dram_gen[0])) );
-    FAPI_TRY( mss::eff_dimm_type(i_target, &(l_dimm_type[0])) );
-
-    // There's no way to configure the PHY for more than one value. However, we don't know if there's
-    // a DIMM in one slot, the other or double drop. So we do a little gyration here to make sure
-    // we have one of the two values (and assume effective config caught a bad config
-    l_type_index = l_dimm_type[0] | l_dimm_type[1];
-    l_gen_index = l_dram_gen[0] | l_dram_gen[1];
-
-    // FOR NIMBUS PHY (as the protocol choice above is) BRS
-    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
-
-    l_data.insertFromRight<MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE,
-                           MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN>(memory_type[l_type_index][l_gen_index]);
-    l_data.insertFromRight<MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET,
-                           MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN>(l_rlo);
-    l_data.insertFromRight<MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET,
-                           MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN>(l_wlo);
-
-    // Model 31 changed the MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW bit to '0' for DDR4
-    // and '1' for 'extended 3ds.' We need to check an attribute here when we get to 3ds BRS
-    l_data.clearBit<MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW>();
-
-    FAPI_INF("phy pc_config1 0x%0llx", l_data);
-    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-///
 /// @brief Sets up the IO impedances (ADR DRV's and DP DRV's/RCV's) - MCA specialization
 /// @tparam T the fapi2::TargetType
 /// @param[in] i_target the target (MCA/MCBIST or MBA?)
@@ -674,10 +587,6 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
     {
         // The following registers must be configured to the correct operating environment:
 
-        // Undocumented, noted by Bialas
-        FAPI_TRY( mss::set_pc_config0(p) );
-        FAPI_TRY( mss::set_pc_config1(p) );
-
         // Section 5.2.1.3 PC Rank Pair 0 on page 177
         // Section 5.2.1.4 PC Rank Pair 1 on page 179
         FAPI_TRY( mss::set_rank_pairs(p) );
@@ -698,6 +607,9 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
         // Reset Read VREF according to ATTR_MSS_VPD_MT_VREF_MC_RD value
         FAPI_TRY( mss::dp16::reset_rd_vref(p) );
 
+        // PHY Control reset
+        FAPI_TRY( mss::pc::reset(p) );
+
         // Write Control reset
         FAPI_TRY( mss::wc::reset(p) );
 
@@ -713,6 +625,10 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
         // Shove the ADR delay values from VPD into the ADR delay registers
         FAPI_TRY( mss::adr::reset_delay(p) );
 
+        // Write tsys adr and tsys data
+        FAPI_TRY( mss::adr32s::reset_tsys_adr(p) );
+        FAPI_TRY( mss::dp16::reset_tsys_data(p) );
+
         //resets all of the IO impedances
         FAPI_TRY( mss::reset_io_impedances(p) );
     }
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index c604be0b1..4ff039e1b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -245,24 +245,6 @@ template<>
 fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
 
 ///
-/// @brief Setup the PC CONFIG0 register
-/// @tparam T the fapi2::TargetType
-/// @param[in] i_target the target (MCA or MBA?)
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T>
-fapi2::ReturnCode set_pc_config0(const fapi2::Target<T>& i_target);
-
-///
-/// @brief Setup the PC CONFIG1 register
-/// @tparam T the fapi2::TargetType
-/// @param[in] i_target the target (MCA or MBA?)
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T>
-fapi2::ReturnCode set_pc_config1(const fapi2::Target<T>& i_target);
-
-///
 /// @brief Return the DIMM target for the primary rank in the specificed rank pair
 /// @tparam T fapi2::TargetType of the port target
 /// @param[in] i_target the target
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index a7192efda..1f6fcfc7a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -243,6 +243,17 @@ const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::
     { MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4 },
 };
 
+// Definition of the DP16 Phase Rotator Static Offset registers
+// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
+const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::PR_STATIC_OFFSET_REG
+{
+    MCA_DDRPHY_DP16_WRCLK_PR_P0_0,
+    MCA_DDRPHY_DP16_WRCLK_PR_P0_1,
+    MCA_DDRPHY_DP16_WRCLK_PR_P0_2,
+    MCA_DDRPHY_DP16_WRCLK_PR_P0_3,
+    MCA_DDRPHY_DP16_WRCLK_PR_P0_4,
+};
+
 ///
 /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
 /// @tparam T fapi2 Target Type - derived
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 8a86932af..79050b6d6 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -42,6 +42,7 @@
 #include <p9_mc_scom_addresses_fld.H>
 
 #include <lib/utils/scom.H>
+#include <lib/utils/find.H>
 
 namespace mss
 {
@@ -148,6 +149,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
         static const std::vector< std::pair<uint64_t, uint64_t> > CTLE_CNTRL_REG;
         static const std::vector< std::pair<uint64_t, uint64_t> > RD_VREF_CNTRL_REG;
         static const std::vector< uint64_t > DATA_BIT_DIR1;
+        static const std::vector< uint64_t > PR_STATIC_OFFSET_REG;
         static const std::vector< uint64_t > IO_TX_FET_SLICE_REG;
         static const std::vector< uint64_t > IO_TX_PFET_TERM_REG;
 
@@ -157,6 +159,9 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
             FLUSH = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FLUSH,
             INIT_IO = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO,
 
+            TSYS_DATA = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS,
+            TSYS_DATA_LEN = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN,
+
             // Seriously PHY guys?
             AC_BOOST_WR_DOWN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC,
             AC_BOOST_WR_DOWN_LEN = MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN,
@@ -214,6 +219,75 @@ namespace dp16
 {
 
 ///
+/// @brief Read TSYS_DATA
+/// @tparam I DP16 instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode read_tsys_data( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
+
+    FAPI_TRY( mss::getScom(i_target, TT::PR_STATIC_OFFSET_REG[I], o_data) );
+    FAPI_INF("tsys_data dp16%d: 0x%016lx", I, o_data);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write TSYS_DATA
+/// @tparam I DP16 instance
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode write_tsys_data( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    static_assert( I < TT::DP_COUNT, "dp16 instance out of range");
+
+    FAPI_INF("tsys_data dp16%d: 0x%016lx", I, i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::PR_STATIC_OFFSET_REG[I], i_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset tsys_data
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode reset_tsys_data( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+    uint8_t l_tsys_data = 0;
+
+    FAPI_TRY( mss::vpd_mr_tsys_data(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target), l_tsys_data) );
+    l_data.insertFromRight<TT::TSYS_DATA, TT::TSYS_DATA_LEN>(l_tsys_data);
+
+    for (const auto r : TT::PR_STATIC_OFFSET_REG)
+    {
+        // TODO RTC:160358 Suspect duplicated scoms in ddr initfile
+        FAPI_INF("reset tsys_data 0x%016lx: 0x%016lx", r, l_data);
+        FAPI_TRY( mss::putScom(i_target, r, l_data) );
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Read DLL_CNTL
 /// @tparam I DP16 instance
 /// @tparam D DLL instance in the specified DP16
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
index d1642518c..26fec2e4f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
@@ -22,3 +22,111 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file phy_cntrl.C
+/// @brief Subroutines for the PHY PC registers
+///
+// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <lib/phy/phy_cntrl.H>
+#include <lib/utils/scom.H>
+#include <lib/utils/c_str.H>
+#include <lib/utils/index.H>
+
+#include <lib/mss_attribute_accessors.H>
+
+using fapi2::TARGET_TYPE_MCA;
+
+namespace mss
+{
+
+namespace pc
+{
+
+///
+/// @brief Reset the PC CONFIG0 register
+/// @param[in] i_target the target (MCA or MBA?)
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+template<>
+fapi2::ReturnCode reset_config0(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
+{
+    typedef pcTraits<TARGET_TYPE_MCA> TT;
+
+    fapi2::buffer<uint64_t> l_data;
+
+    l_data.setBit<TT::DDR4_CMD_SIG_REDUCTION>();
+    l_data.setBit<TT::DDR4_VLEVEL_BANK_GROUP>();
+
+    FAPI_TRY( write_config0(i_target, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset the PC CONFIG1 register
+/// @param[in] i_target <the target (MCA or MBA?)
+/// @return FAPI2_RC_SUCCESS if and only if ok
+///
+template<>
+fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
+{
+    typedef pcTraits<TARGET_TYPE_MCA> TT;
+
+    // Static table of PHY config values for MEMORY_TYPE.
+    // [EMPTY, RDIMM, CDIMM, or LRDIMM][EMPTY, DDR3 or DDR4]
+    constexpr uint64_t memory_type[4][3] =
+    {
+        { 0, 0,     0     },  // Empty, never really used.
+        { 0, 0b001, 0b101 },  // RDIMM
+        { 0, 0b000, 0b000 },  // CDIMM bits, UDIMM enum (placeholder, never used on Nimbus)
+        { 0, 0b011, 0b111 },  // LRDIMM
+    };
+
+    fapi2::buffer<uint64_t> l_data;
+
+    uint8_t l_rlo = 0;
+    uint8_t l_wlo = 0;
+    uint8_t l_dram_gen[MAX_DIMM_PER_PORT]    = {0};
+    uint8_t l_dimm_type[MAX_DIMM_PER_PORT]   = {0};
+    uint8_t l_type_index = 0;
+    uint8_t l_gen_index = 0;
+
+    FAPI_TRY( mss::vpd_mr_dphy_rlo(i_target, l_rlo) );
+    FAPI_TRY( mss::vpd_mr_dphy_wlo(i_target, l_wlo) );
+    FAPI_TRY( mss::eff_dram_gen(i_target, &(l_dram_gen[0])) );
+    FAPI_TRY( mss::eff_dimm_type(i_target, &(l_dimm_type[0])) );
+
+    // There's no way to configure the PHY for more than one value. However, we don't know if there's
+    // a DIMM in one slot, the other or double drop. So we do a little gyration here to make sure
+    // we have one of the two values (and assume effective config caught a bad config)
+    l_type_index = l_dimm_type[0] | l_dimm_type[1];
+    l_gen_index = l_dram_gen[0] | l_dram_gen[1];
+
+    // FOR NIMBUS PHY (as the protocol choice above is) BRS
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
+
+    l_data.insertFromRight<TT::MEMORY_TYPE, TT::MEMORY_TYPE_LEN>(memory_type[l_type_index][l_gen_index]);
+    l_data.insertFromRight<TT::READ_LATENCY_OFFSET, TT::READ_LATENCY_OFFSET_LEN>(l_rlo);
+    l_data.insertFromRight<TT::WRITE_LATENCY_OFFSET, TT::WRITE_LATENCY_OFFSET_LEN>(l_wlo);
+
+    // TODO RTC:160355 Need to check what mode to put this bit in if there are mixed 3DS/SDP DIMM
+    l_data.clearBit<TT::DDR4_LATENCY_SW>();
+
+    FAPI_TRY( write_config1(i_target, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+} // close namespace pc
+} // close namespace mss
+
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
index 3ed616af6..be44e095c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
@@ -38,6 +38,10 @@
 
 #include <fapi2.H>
 #include <p9_mc_scom_addresses.H>
+#include <p9_mc_scom_addresses_fld.H>
+
+#include <lib/shared/mss_const.H>
+#include <lib/utils/scom.H>
 
 namespace mss
 {
@@ -75,6 +79,8 @@ class pcTraits<fapi2::TARGET_TYPE_MCA>
         static const uint64_t PC_INIT_CAL_ERROR_REG = MCA_DDRPHY_PC_INIT_CAL_ERROR_P0;
         static const uint64_t PC_DLL_ZCAL_CAL_STATUS_REG = MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0;
         static const uint64_t PC_RESETS_REG = MCA_DDRPHY_PC_RESETS_P0;
+        static const uint64_t PC_CONFIG0_REG = MCA_DDRPHY_PC_CONFIG0_P0;
+        static const uint64_t PC_CONFIG1_REG = MCA_DDRPHY_PC_CONFIG1_P0;
 
         enum
         {
@@ -108,6 +114,35 @@ class pcTraits<fapi2::TARGET_TYPE_MCA>
             SYSCLK_RESET = MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET,
             PVT_OVERRIDE = MCA_DDRPHY_PC_RESETS_P0_PVT_OVERRIDE,
             ENABLE_ZCAL = MCA_DDRPHY_PC_RESETS_P0_ENABLE_ZCAL,
+
+            WRITE_LATENCY_OFFSET = MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET,
+            WRITE_LATENCY_OFFSET_LEN = MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN,
+            READ_LATENCY_OFFSET = MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET,
+            READ_LATENCY_OFFSET_LEN = MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN,
+            MEMCTL_CIC_FAST = MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CIC_FAST,
+            MEMCTL_CTRN_IGNORE = MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CTRN_IGNORE,
+            DISABLE_MEMCTL_CAL = MCA_DDRPHY_PC_CONFIG1_P0_DISABLE_MEMCTL_CAL,
+            MEMORY_TYPE = MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE,
+            MEMORY_TYPE_LEN = MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN,
+            DDR4_LATENCY_SW = MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW,
+            RETRAIN_PERCAL_SW = MCA_DDRPHY_PC_CONFIG1_P0_RETRAIN_PERCAL_SW,
+
+
+            // PC Config0 Protocol has been re-purposed for PDA enable.
+            // repurposed to pda_enable_override, so zero per John Bialas 4/16 JJM
+            PDA_ENABLE = MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL,
+            PDA_ENABLE_LEN = MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL_LEN,
+
+            DATA_MUX4_1MODE = MCA_DDRPHY_PC_CONFIG0_P0_DATA_MUX4_1MODE,
+            DDR4_CMD_SIG_REDUCTION = MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION,
+            SYSCLK_2X_MEMINTCLKO = MCA_DDRPHY_PC_CONFIG0_P0_SYSCLK_2X_MEMINTCLKO,
+            RANK_OVERRIDE = MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE,
+            RANK_OVERRIDE_VALUE = MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE,
+            RANK_OVERRIDE_VALUE_LEN = MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE_LEN,
+            LOW_LATENCY = MCA_DDRPHY_PC_CONFIG0_P0_LOW_LATENCY,
+            DDR4_IPW_LOOP_DIS = MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS,
+            DDR4_VLEVEL_BANK_GROUP = MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP,
+            VPROTH_PSEL_MODE = MCA_DDRPHY_PC_CONFIG0_P0_VPROTH_PSEL_MODE,
         };
 
 };
@@ -115,9 +150,104 @@ class pcTraits<fapi2::TARGET_TYPE_MCA>
 namespace pc
 {
 
+///
+/// @brief read PC_CONFIG1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = pcTraits<T> >
+inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::PC_CONFIG1_REG, o_data) );
+    FAPI_INF("pc_config1: 0x%016llx", o_data);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write PC_CONFIG1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = pcTraits<T> >
+inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target,
+                                        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_INF("pc_config1: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::PC_CONFIG1_REG, i_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset pc_config1
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = pcTraits<T> >
+fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target );
+
+///
+/// @brief read PC_CONFIG0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = pcTraits<T> >
+inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::PC_CONFIG0_REG, o_data) );
+    FAPI_INF("pc_config0: 0x%016llx", o_data);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write PC_CONFIG0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = pcTraits<T> >
+inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target,
+                                        const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_INF("pc_config0: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::PC_CONFIG0_REG, i_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset pc_config0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = pcTraits<T> >
+fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target );
 
 ///
 /// @brief read MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target the fapi2 target of the port
 /// @param[out] o_data the value of the register
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
@@ -127,12 +257,15 @@ inline fapi2::ReturnCode read_dll_zcal_status( const fapi2::Target<T>& i_target,
 {
     FAPI_TRY( mss::getScom(i_target, TT::PC_DLL_ZCAL_CAL_STATUS_REG, o_data) );
     FAPI_INF("pc_dll_zcal_status: 0x%016llx", o_data);
+
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
 /// @brief Get DP DLL Cal Status
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// Combine the processing of Good, Error and Error Fine into one functional interface
 /// @param[in] fapi2::buffer representing the status register to interrogate
 /// @return mss::states; YES == success, NO == fail, INVALID == still running
@@ -177,6 +310,8 @@ inline mss::states get_dll_cal_status( fapi2::buffer<uint64_t>& i_data )
 
 ///
 /// @brief Get ZCAL Cal Status
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] fapi2::buffer representing the status register to interrogate
 /// @return mss::states; YES == success, NO == fail
 ///
@@ -189,6 +324,8 @@ inline mss::states get_zcal_status( fapi2::buffer<uint64_t>& i_data )
 
 ///
 /// @brief read PC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target the fapi2 target of the port
 /// @param[out] o_data the value of the register
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
@@ -198,12 +335,15 @@ inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, f
 {
     FAPI_TRY( mss::getScom(i_target, TT::PC_ERROR_STATUS0_REG, o_data) );
     FAPI_INF("pc_error_status0: 0x%016llx", o_data);
+
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
 /// @brief Write PC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target the fapi2 target of the port
 /// @param[in] i_data the value of the register
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
@@ -214,12 +354,15 @@ inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target,
 {
     FAPI_INF("pc_error_status0: 0x%016llx", i_data);
     FAPI_TRY( mss::putScom(i_target, TT::PC_ERROR_STATUS0_REG, i_data) );
+
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
 /// @brief reset pc_error_status0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target fapi2 target of the port
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
 ///
@@ -234,6 +377,8 @@ fapi_try_exit:
 
 ///
 /// @brief read PC_INIT_CAL_ERROR
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target the fapi2 target of the port
 /// @param[out] o_data the value of the register
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
@@ -243,6 +388,7 @@ inline fapi2::ReturnCode read_init_cal_error( const fapi2::Target<T>& i_target,
 {
     FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_ERROR_REG, o_data) );
     FAPI_INF("pc_init_cal_error: 0x%016llx", o_data);
+
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -259,12 +405,15 @@ inline fapi2::ReturnCode write_init_cal_error( const fapi2::Target<T>& i_target,
 {
     FAPI_INF("pc_init_cal_error: 0x%016llx", i_data);
     FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_ERROR_REG, i_data) );
+
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
 /// @brief reset pc_init_cal_error
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target fapi2 target of the port
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
 ///
@@ -279,12 +428,16 @@ fapi_try_exit:
 
 ///
 /// @brief reset rc
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target fapi2 target of the port
 /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
 ///
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode reset( const fapi2::Target<T>& i_target )
 {
+    // Note that PC_CONFIG0 is statically configured in the initfile - we don't need to reset it.
+    FAPI_TRY( reset_config1(i_target) );
     FAPI_TRY( reset_error_status0(i_target) );
     FAPI_TRY( reset_init_cal_error(i_target) );
 
@@ -294,6 +447,8 @@ fapi_try_exit:
 
 ///
 /// @brief read PC_RESETS
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[in] i_target the fapi2 target of the port
 /// @param[out] o_data the value of the register
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
@@ -303,6 +458,7 @@ inline fapi2::ReturnCode read_resets( const fapi2::Target<T>& i_target, fapi2::b
 {
     FAPI_TRY( mss::getScom(i_target, TT::PC_RESETS_REG, o_data) );
     FAPI_INF("pc_resets: 0x%016llx", o_data);
+
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -318,12 +474,15 @@ inline fapi2::ReturnCode write_resets( const fapi2::Target<T>& i_target, const f
 {
     FAPI_INF("pc_resets: 0x%016llx", i_data);
     FAPI_TRY( mss::putScom(i_target, TT::PC_RESETS_REG, i_data) );
+
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
 /// @brief Set ENABLE_ZCAL in PC_RESETS
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
 /// @param[out] o_data the value of the register
 /// @param[in] i_state mss::HIGH or mss::LOW
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index 58e638ae7..b0fb65e72 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -324,11 +324,9 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
     fapi2::buffer<uint64_t> l_data;
     uint8_t l_gpo = 0;
 
-    FAPI_TRY( mss::vpd_gpo(i_target, l_gpo) );
+    FAPI_TRY( mss::vpd_mr_dphy_gpo(i_target, l_gpo) );
 
-    // 48:51, (ATTR_VPD_GPO[0]), any; # GLOBAL_PHY_OFFSET (GPO), based on attribute now
     l_data.insertFromRight<TT::GLOBAL_PHY_OFFSET, TT::GLOBAL_PHY_OFFSET_LEN>(l_gpo);
-
     l_data.setBit<TT::PERFORM_RDCLK_ALIGN>();
 
     FAPI_TRY( write_config0(i_target, l_data) );
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index 495ddcd05..af655539d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -98,10 +98,6 @@ enum times
     DELAY_100US             = 100000,   ///< general purpose 100 usec delay for HW mode
     DELAY_1MS               = 1000000,  ///< general purpose 1 ms delay for HW mode
 
-    // From the DDR4spec 2400 speed - need to be changed to read attributes. BRS
-    tWLO = 10,
-    tWLOE = 2,
-
     SEC_IN_HOUR             = 60 * 60,  ///< seconds in an hour, used for scrub times
     BG_SCRUB_IN_HOURS       = 12,
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.H b/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.H
deleted file mode 100644
index 87661158b..000000000
--- a/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.H
+++ /dev/null
@@ -1,150 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-///
-/// @file slew_cal.H
-/// @brief  Runs the slew calibration engine
-///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
-// *HWP Team: Memory
-// *HWP Level: 2
-// *HWP Consumed by: HB:FSP
-
-#ifndef _MSS_SLEW_CAL_H_
-#define _MSS_SLEW_CAL_H_
-
-#include <fapi2.H>
-
-namespace mss
-{
-
-// bits: 58:59 DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR0_SLEW_DONE_STATUS(0:1)
-enum slew_done_status
-{
-    SLEW_CAL_NOT_DONE = 0b00, ///< Not complete
-    SLEW_CAL_ERRORS   = 0b01, ///< Complete, but with errors - didn't reach alignment
-    SLEW_CAL_WARNING  = 0b10, ///< Complete, but with warnings - slew cntl is 0b0000
-    SLEW_CAL_SUCCESS  = 0b11, ///< OK
-};
-
-// Used for tagging slew rate information in the table. We use enums for tags rather than
-// strings for a few reasons, not the least of which it simplifies putting the tags into error logs.
-enum tags_t
-{
-    TAG_DATA = 0,
-    TAG_ADR = 1,
-
-    TAG_3VNS   = 3,
-    TAG_4VNS   = 4,
-    TAG_5VNS   = 5,
-    TAG_6VNS   = 6,
-    TAG_MAXVNS = 7,
-
-    TAG_15OHM = 15,
-    TAG_20OHM = 20,
-    TAG_24OHM = 24,
-    TAG_30OHM = 30,
-    TAG_34OHM = 34,
-    TAG_40OHM = 40,
-
-    TAG_1066MHZ = 1066,
-    TAG_1333MHZ = 1333,
-    TAG_1600MHZ = 1600,
-    TAG_1866MHZ = 1866,
-    TAG_2400MHZ = 2400,
-};
-
-///
-/// @brief find the attribute array index of a tag
-/// @param[in] i_type whether this is an adr or dq lookup
-/// @param[in] i_tag tags_t the tag to find the index of
-/// @return size_t the attribute array index
-///
-inline size_t index(const tags_t& i_type, const tags_t& i_tag)
-{
-    // Static table to map some tags to indexes.
-    // First are the indexes for DATA, second are the indexes for ADR
-    static const size_t map[2][41] =
-    {
-        // DATA
-        //  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20
-        {
-            0, 1, 0, 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-            // 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
-            0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 3
-        },
-
-        // ADR
-        //  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20
-        {
-            0, 1, 0, 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
-            // 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
-            0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3
-        }
-    };
-
-    fapi2::Assert((i_type == TAG_ADR) || (i_type == TAG_DATA));
-    fapi2::Assert(i_tag <= TAG_40OHM);
-    return map[i_type][i_tag];
-}
-
-
-typedef std::pair<tags_t, uint64_t> slew_rate_t;
-
-// Some types to help us keep track of the slew information
-///< slew(3)3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3
-typedef std::vector< slew_rate_t > slew_rates_t;
-
-///< imped(4)24ohms=0, 30ohms=1, 34ohms=2, 40ohms=3 for DQ/DQS
-///< imped(4)15ohms=0, 20ohms=1, 30ohms=2, 40ohms=3 for ADR driver
-typedef std::vector< std::pair<tags_t, slew_rates_t> > slew_per_imp_t;
-
-///< speed(4)1066=0, 1333=1, 1600=2, 1866=3
-typedef std::vector< std::pair<tags_t, slew_per_imp_t> > slew_table_t;
-
-///
-/// @brief Run the sle calibration engine
-/// @param[in] i_target the MCBIST
-/// @return FAPI2_RC_SUCCESS iff OK
-///
-fapi2::ReturnCode slew_cal(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target);
-
-///
-/// @brief Process FFDC for slew calibration
-/// @param[in] i_target MCA (port) target
-/// @param[in] -_where_am_i a vector of the steps which came before me
-/// @param[in] l_slew_rate the slew table to be operated on
-/// @param[in] i_status the calibration status
-/// @param[in] i_reg the register value
-/// @return A fapi2::ReturnCode, appropriate for the calibration status
-///
-fapi2::ReturnCode slew_cal_status(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
-                                  std::vector<tags_t>& i_where_am_i,
-                                  const uint64_t l_slew_rate,
-                                  const uint64_t i_status,
-                                  const fapi2::buffer<uint64_t>& i_reg);
-}
-#endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal_status.C b/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal_status.C
deleted file mode 100644
index b19813df8..000000000
--- a/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal_status.C
+++ /dev/null
@@ -1,116 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal_status.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-///
-/// @file slew_cal_status.C
-/// @brief Process the status from slew calibration. This is it's own function
-/// and file as it gets messey considering there are FFDC object per port ...
-///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
-// *HWP Team: Memory
-// *HWP Level: 2
-// *HWP Consumed by: FSP:HB
-
-#include <fapi2.H>
-
-#include <mss.H>
-#include <lib/termination/slew_cal.H>
-
-using fapi2::TARGET_TYPE_MCBIST;
-using fapi2::TARGET_TYPE_MCA;
-using fapi2::TARGET_TYPE_SYSTEM;
-
-using fapi2::TARGET_STATE_FUNCTIONAL;
-
-using fapi2::FAPI2_RC_SUCCESS;
-
-namespace mss
-{
-
-///
-/// @brief Process FFDC for slew calibration
-/// @param[in] MCA (port) target
-/// @param[in] a vector of the steps which came before me
-/// @param[in] the slew table to be operated on
-/// @param[in] the calibration status
-/// @param[in] the register value
-/// @return A fapi2::ReturnCode, appropriate for the calibration status
-///
-fapi2::ReturnCode slew_cal_status(const fapi2::Target<TARGET_TYPE_MCA>& i_target,
-                                  std::vector<tags_t>& i_where_am_i,
-                                  const uint64_t l_slew_rate,
-                                  const uint64_t i_status,
-                                  const fapi2::buffer<uint64_t>& i_reg)
-{
-    // Some short-hand for this subroutine
-    const char* l_type = i_where_am_i[0] == TAG_ADR ? "adr" : "data";
-    const uint64_t& l_speed = i_where_am_i[1];
-    const uint64_t& l_ohm = i_where_am_i[2];
-    const uint64_t& l_vns = i_where_am_i[3];
-
-    // Write up the message/error string once.
-    FAPI_INF("Slew calibration: %s slew %s, %lumhz %luohm %luV/ns: %d",
-             mss::c_str(i_target), l_type, l_speed, l_ohm, l_vns, l_slew_rate);
-
-    switch (i_status)
-    {
-        case SLEW_CAL_SUCCESS:
-            FAPI_DBG("Slew calibration success");
-            break;
-
-        case SLEW_CAL_WARNING:
-            FAPI_ERR("Slew calibration warning");
-            break;
-
-        case SLEW_CAL_NOT_DONE:
-            FAPI_ASSERT(false, fapi2::MSS_SLEW_CAL_TIMEOUT()
-                        .set_PORT(mss::pos(i_target))
-                        .set_DATA_ADR(i_where_am_i[0])
-                        .set_IMP(l_ohm)
-                        .set_SLEW(l_slew_rate)
-                        .set_STAT_REG(i_reg)
-                        .set_TARGET_IN_ERROR(i_target),
-                        "Slew calibration timeout");
-            break;
-
-        case SLEW_CAL_ERRORS:
-            FAPI_ASSERT(false, fapi2::MSS_SLEW_CAL_ERROR()
-                        .set_PORT(mss::pos(i_target))
-                        .set_DATA_ADR(i_where_am_i[0])
-                        .set_IMP(l_ohm)
-                        .set_SLEW(l_slew_rate)
-                        .set_STAT_REG(i_reg)
-                        .set_TARGET_IN_ERROR(i_target),
-                        "Slew calibration error");
-            break;
-    };
-
-    return fapi2::FAPI2_RC_SUCCESS;
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-}
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
index d60d4dde8..598a2a01d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
@@ -65,13 +65,13 @@ static constexpr uint8_t raw_mt[raw_mt_size] =
 constexpr auto raw_mr_size = 255;
 static constexpr uint8_t raw_mr[raw_mr_size] =
 {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x02, 0x02, 0x01, 0x01, 0x03, 0x08, 0x03, 0x06,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x01, 0x01, 0x01, 0x01, 0x03, 0x08, 0x03, 0x06,
     0x03, 0x09, 0x04, 0x04, 0x00, 0x01, 0x01, 0x00, 0x04, 0x02, 0x03, 0x00, 0x06, 0x0a, 0x02, 0x01,
     0x09, 0x09, 0x03, 0x01, 0x05, 0x07, 0x03, 0x05, 0x03, 0x03, 0x0a, 0x06, 0x08, 0x05, 0x09, 0x08,
     0x09, 0x07, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x67, 0x64, 0x66, 0x6b, 0x66, 0x66, 0x68, 0x6b,
     0x0b, 0x03, 0x0b, 0x0a, 0x09, 0x0d, 0x0a, 0x0b, 0x09, 0x04, 0x15, 0x14, 0x00, 0x00, 0x25, 0x22,
     0x00, 0x00, 0x1b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x00, 0x00, 0x14, 0x0e,
-    0x00, 0x00, 0x01, 0x21, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x01, 0x60, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index 41d193069..4a9f4fc84 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -201,21 +201,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
 
         // Hard-coded RIT protect attribute set (currently not taken account in eff_config)
         {
-            uint8_t l_vpd_rlo[mss::PORTS_PER_MCS] = {0x01, 0x01};
-            FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_VPD_RLO, i_target, l_vpd_rlo ) );
-        }
-
-        {
-            uint8_t l_vpd_wlo[mss::PORTS_PER_MCS] = {0x01, 0x01};
-            FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_VPD_WLO, i_target, l_vpd_wlo ) );
-        }
-
-        {
-            uint8_t l_vpd_glo[mss::PORTS_PER_MCS] = {0x05, 0x05};
-            FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_VPD_GPO, i_target, l_vpd_glo ) );
-        }
-
-        {
             uint32_t l_m_dram_clocks[mss::PORTS_PER_MCS] = {0x200, 0x200};
             FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_RUNTIME_MEM_M_DRAM_CLOCKS, i_target, l_m_dram_clocks ) );
         }
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 4c714e317..f4f4362f3 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -2184,34 +2184,6 @@
     </attribute>
 
     <attribute>
-        <id>ATTR_VPD_RLO</id>
-        <targetType>TARGET_TYPE_MCS</targetType>
-        <description>
-            This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A.
-            Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D
-        </description>
-        <initToZero></initToZero>
-        <valueType>uint8</valueType>
-        <array>2</array>
-        <mssAccessorName>vpd_rlo</mssAccessorName>
-        <writeable/>
-    </attribute>
-
-    <attribute>
-        <id>ATTR_VPD_WLO</id>
-        <targetType>TARGET_TYPE_MCS</targetType>
-        <description>
-            This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A.
-            Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D
-        </description>
-        <initToZero></initToZero>
-        <valueType>uint8</valueType>
-        <array>2</array>
-        <mssAccessorName>vpd_wlo</mssAccessorName>
-        <writeable/>
-    </attribute>
-
-    <attribute>
         <id>ATTR_EFF_DRAM_MODULE_BUS_WIDTH</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
@@ -2925,20 +2897,6 @@
     </attribute>
 
     <attribute>
-        <id>ATTR_VPD_GPO</id>
-        <targetType>TARGET_TYPE_MCS</targetType>
-        <description>
-          This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM
-          associated with port A.  Bytes 125 for port B, 189 for port C and 253 for port D
-        </description>
-        <initToZero></initToZero>
-        <valueType>uint8</valueType>
-        <array>2</array>
-        <writeable/>
-        <mssAccessorName>vpd_gpo</mssAccessorName>
-    </attribute>
-
-    <attribute>
         <id>ATTR_EFF_DRAM_TDQS</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>