path: root/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H

/* IBM_PROLOG_BEGIN_TAG                                                   */
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/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H $ */
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/* OpenPOWER HostBoot Project                                             */
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///
/// @file timing.H
/// @brief Determine effective config for mss settings
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: HB:FSP

#ifndef _MSS_TIMING_H_
#define _MSS_TIMING_H_

#include <cstdint>
#include <fapi2.H>
#include <lib/utils/find.H>
#include <lib/utils/conversions.H>
namespace mss
{

enum GUARD_BAND : uint16_t
{
    // Used for caclulating spd timing values - from JEDEC rounding algorithm
    // Correction factor is 1% (for DDR3) or 2.5% (for DDR4)
    // when doing integer math, we add-in the inverse correction factor
    // Formula used for derivation:
    // Guardband = 1000 * (1000* correction_factor) - 1
    INVERSE_DDR3_CORRECTION_FACTOR = 989,
    INVERSE_DDR4_CORRECTION_FACTOR = 974,
};

enum class refresh_rate : uint8_t
{
    REF1X = 1,
    REF2X = 2,
    REF4X = 4,
};

enum temp_mode : uint8_t
{
    NORMAL = 1,
    EXTENDED = 2,
};

///
/// @brief Calculates timing value
/// @param[in] i_timing_mtb timing value in MTB units
/// @param[in] i_mtb_multiplier SPD medium timebase
/// @param[in] i_timing_ftb fine offset of timing value
/// @param[in] i_ftb_multiplier SPD fine timebase
/// @return the timing value in picoseconds
///
inline int64_t calc_timing_from_timebase(const int64_t i_timing_mtb,
        const int64_t i_mtb_multiplier,
        const int64_t i_timing_ftb,
        const int64_t i_ftb_multiplier)
{
    // JEDEC algorithm
    const int64_t l_timing_val = i_timing_mtb * i_mtb_multiplier;
    const int64_t l_fine_offset = i_timing_ftb * i_ftb_multiplier;

    return l_timing_val + l_fine_offset;
}

///
/// @brief Returns clock cycles
/// @tparam T input
/// @tparam OT output
/// @param[in] timing_in_ps timing parameter in ps
/// @param[in] tck_in_ps  clock period in ps
/// @param[in] inverse_corr_factor inverse correction factor  (defined by JEDEC)
/// @param[out] o_value_nck the end calculation in nck
/// @return the clock cycles of timing parameter (provided in ps)
/// @note DDR4 SPD Contents Rounding Algorithm
/// @note Item 2220.46
///
template<typename T, typename OT>
inline fapi2::ReturnCode calc_nck(const T& i_timing_in_ps,
                                  const T& i_tck_in_ps,
                                  GUARD_BAND i_inverse_corr_factor,
                                  OT& o_val_nck)
{
    // Preliminary nCK calculation, scaled by 1000 per JDEC algorithm
    T l_temp_nck = (i_timing_in_ps * 1000) / (i_tck_in_ps == 0 ? 1 : i_tck_in_ps);
    l_temp_nck += i_inverse_corr_factor;
    l_temp_nck = l_temp_nck / 1000;

    //Check for overflow.
    o_val_nck = l_temp_nck;

    FAPI_ASSERT(o_val_nck == l_temp_nck,
                fapi2::MSS_INVALID_CAST_CALC_NCK().
                set_TIMING_PS(i_timing_in_ps).
                set_NCK_NS(i_tck_in_ps).
                set_CORRECTION_FACTOR(i_inverse_corr_factor),
                "Bad cast for calc_nck. Output is: %d, after cast is %d", l_temp_nck, l_temp_nck);
    return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Returns application clock period (tCK) based on dimm transfer rate
/// @tparam T the fapi2 target
/// @tparam OT output type
/// @param[in] i_target FAPI2 target
/// @param[out] o_tCK_in_ps application period in ps
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
template<fapi2::TargetType T, typename OT>
inline fapi2::ReturnCode clock_period(const fapi2::Target<T>& i_target,
                                      OT& o_tCK_in_ps)
{
    uint64_t l_dimm_transfer_rate = 0;
    FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_dimm_transfer_rate) );

    FAPI_TRY( freq_to_ps(l_dimm_transfer_rate, o_tCK_in_ps) );

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Calculates refresh interval time
/// @param[in] i_mode fine refresh rate mode
/// @param[in] i_temp_refresh_range temperature refresh range
/// @param[out] o_value timing val in ps
/// @return fapi2::ReturnCode
///
fapi2::ReturnCode calc_trefi( const refresh_rate i_mode,
                              const uint8_t i_temp_refresh_range,
                              int64_t& o_timing );

///
/// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank)
/// @param[in] i_mode fine refresh rate mode
/// @param[in] i_density SDRAM density
/// @param[out] o_trfc_in_ps timing val in ps
/// @return fapi2::FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode calc_trfc_dlr( const uint8_t i_refresh_mode,
                                 const uint8_t i_density,
                                 uint64_t& o_trfc_in_ps );

///
/// @brief DLL locking time
/// @tparam T the fapi2::TargetType of i_target
/// @tparam OT the type of the output location
/// @param[in] i_target a target for attributes
/// @param[out] o_value reference to space into which to store the output
/// @return fapi2::FAPI2_RC_SUCCESS iff okay
///
template< fapi2::TargetType T, typename OT = uint64_t >
inline fapi2::ReturnCode tdllk( const fapi2::Target<T>& i_target, OT& o_value )
{
    uint64_t l_freq = 0;

    // Calculate tDLLK from our MT/s. Magic numbers (in clocks) from the DDR4 spec
    FAPI_TRY( mss::freq(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq) );
    o_value = (l_freq < fapi2::ENUM_ATTR_MSS_FREQ_MT2133) ? 597 : 768;
    return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Mode Register Set Command Cycle Time
/// @return constexpr value of 8 clocks
///
constexpr uint64_t tmrd()
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return 8;
}

///
/// @brief Control word to control word delay
/// @return constexpr value of 16 clocks
///
constexpr uint64_t tmrd_l()
{
    // Per DDR4RCD02 Spec Rev 0.85
    return 16;
}

///
/// @brief Stabilization time
/// @return constexpr value of 5 us
///
constexpr uint64_t tstab()
{
    // Per DDR4RCD02 Spec Rev 0.85 CK_t stable
    return 5;
}

///
/// @brief Power-up and RESET calibration time
/// @return constexpr value of 1024 clocks
///
constexpr uint64_t tzqinit()
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return 1024;
}

///
/// @brief Normal operation Full calibration time
/// @return constexpr value of 512 clocks
///
constexpr uint64_t tzqoper()
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return 512;
}

///
/// @brief Normal operation Short calibration time
/// @return constexpr value of 128 clocks
///
constexpr uint64_t tzqcs()
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return 128;
}

///
/// @brief DQS_t/DQS_n delay after write leveling mode is programmed
/// @return constexpr value of 25 clocks
///
constexpr uint64_t twldqsen()
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return 25;
}

///
/// @brief First DQS_t/DQS_n rising edge after write leveling mode is programmed
/// @return constexpr value of 40 clocks
///
constexpr uint64_t twlmrd()
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return 40;
}

///
/// @brief Mode Register Set command update delay
/// @tparam T fapi2::TargetType of the target used to calculate cycles from ns
/// @param[in] i_target the target used to get clocks
/// @return max(24nCK,15ns) in clocks
///
template< fapi2::TargetType T >
inline uint64_t tmod( const fapi2::Target<T>& i_target )
{
    // Per DDR4 Full spec update (79-4A) - timing requirements
    return mss::max_ck_ns( i_target, 24, 15 );
}

///
/// @brief Calculate TWLO_TWLOE
/// @tparam T fapi2::TargetType of the target used to calculate cycles from ns
/// @param[in] i_target the target used to get DIMM clocks
/// @return uint64_t, TWLO_TWLOE in cycles
///
template< fapi2::TargetType T >
inline uint64_t twlo_twloe(const fapi2::Target<T>& i_target)
{
    // From mthe PHY databook:
    // 12 + std::max((twldqsen - tmod), (twlo - twlow))
    //    + longest DQS delay in clocks (rounded up) + longest DQ delay in clocks (rounded up)
    // Magic numbers taken from talking with Anuwat (twloe) and reviewing the Centaur code (ldq/ldqs)
    constexpr uint64_t l_dq_ck = 1;
    constexpr uint64_t l_dqs_ck = 1;
    uint8_t l_wlo_ck = 0;
    uint64_t l_wloe_ck = mss::ns_to_cycles(i_target, 2);
    uint64_t l_twlo_twloe = 0;

    FAPI_TRY( mss::vpd_mr_dphy_wlo(i_target, l_wlo_ck) );

    // TODO RTC:160356 This changes if wlo is signed, which it's not but I wonder if it should
    // be ... (the PHY register is.) It changes because we need to round up to 0 if needed.
    l_twlo_twloe = 12 + std::max( (twldqsen() + tmod(i_target)), (l_wlo_ck + l_wloe_ck) ) + l_dq_ck + l_dqs_ck;
    FAPI_INF("twlo_twloe %d for %s", l_twlo_twloe, mss::c_str(i_target));
    return l_twlo_twloe;

fapi_try_exit:
    // We're in deep horseradish if we can't get wlo
    FAPI_ERR("failed to calculate twlo_twloe for %s", mss::c_str(i_target));
    fapi2::Assert(false);
    return 0;
}

///
/// @brief Refresh cycle time
/// @param[in] i_target the DIMM target used to get clocks (needed to know the stack type)
/// @param[out] o_trfc the trfc *in clocks*
/// @return FAPI2_RC_SUCCESS iff ok
///
inline fapi2::ReturnCode trfc( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint16_t& o_trfc )
{
    // Pull down the 3DS attribute. If we have a stack we need to use
    // tRFC_DLR if not we pull down TRFC and use that.
    uint8_t l_stack = 0;

    FAPI_TRY( mss::eff_prim_stack_type(i_target, l_stack) );

    if (l_stack == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_3DS)
    {
        uint8_t l_value = 0;
        FAPI_TRY( mss::eff_dram_trfc_dlr(i_target, l_value) );
        o_trfc = l_value;
    }
    else
    {
        FAPI_TRY( mss::eff_dram_trfc(i_target, o_trfc) );
    }

    return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Direct ODT turn on Latency
/// @param[in] i_target the DIMM target used to get attributes
/// @param[out] o_dodt *in clocks*
/// @return FAPI2_RC_SUCCESS iff ok
///
inline fapi2::ReturnCode dodt_on( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_dodt )
{
    // CWL + AL + PL - 2.0 per DDR4 Full spec update(79-4B)

    uint8_t l_ca_parity_latency = 0;
    uint8_t l_al = 0;
    uint8_t l_cwl = 0;

    FAPI_TRY( mss::eff_ca_parity_latency(i_target, l_ca_parity_latency) );
    FAPI_TRY( mss::eff_dram_al(i_target, l_al) );
    FAPI_TRY( mss::eff_dram_cwl(i_target, l_cwl) );

    o_dodt = l_cwl + l_al + l_ca_parity_latency - 2;
    return fapi2::FAPI2_RC_SUCCESS;

fapi_try_exit:
    return fapi2::current_err;
}

///
/// @brief Direct ODT turn off Latency
/// @param[in] i_target the DIMM target used to get attributes
/// @param[out] o_dodt *in clocks*
/// @return FAPI2_RC_SUCCESS iff ok
///
inline fapi2::ReturnCode dodt_off( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_dodt )
{
    // Same for all frequencies of DDR4; DDR4 Full spec update(79-4B)
    return dodt_on(i_target, o_dodt);
}

// TK RODTon - The use would be for the ODT in the PHY, but the max RODT is equal to or less than
// the max DODTon/off so it would really never be used anyway there anyway. We can implement it if
// we find another need for it.

} // mss
#endif