p9_xip_customize.C: Update Level1 API

Change-Id: I23d4e3dcfb6fb46b1f85669992b81972d08cd264
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24750
Tested-by: Jenkins Server
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25886
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 78 insertions, 35 deletions

diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
index fac10b272..419c31d58 100644
--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
@@ -29,37 +29,37 @@
 
 fapi2::ReturnCode writeMboxRegs (
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target,
-    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_system_target,
-    void* io_image)
+    void* i_image)
 {
     FAPI_DBG ("writeMboxRegs Entering...");
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
 
-    MBOX_ATTR_WRITE (ATTR_I2C_BUS_DIV_REF,         i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_FUNCTIONAL_EQ_EC_VALID,  i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_EQ_GARD,                 i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_EC_GARD,                 i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_I2C_BUS_DIV_REF_VALID,   i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_FW_MODE_FLAGS_VALID,     i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_ISTEP_MODE,              i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_SBE_RUNTIME_MODE,        i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_IS_MPIPL,                i_system_target, io_image);
-    MBOX_ATTR_WRITE (ATTR_IS_SP_MODE,              i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_SBE_FFDC_ENABLE,         i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_SBE_INTERNAL_FFDC_ENABLE, i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_BOOT_FREQUENCY_VALID,    i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_NEST_PLL_BUCKET,         i_system_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_BOOT_FREQ_MULT,          i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_HWP_CONTROL_FLAGS_VALID, i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_SYSTEM_IPL_PHASE,        i_system_target, io_image);
-    MBOX_ATTR_WRITE (ATTR_SYS_FORCE_ALL_CORES,     i_system_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_RISK_LEVEL,              i_system_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_DISABLE_HBBL_VECTORS,    i_system_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_CHIP_SELECTION_VALID,    i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_CHIP_SELECTION,          i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_NODE_POS,                i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_CHIP_POS,                i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_SCRATCH6_VALID,          i_proc_target,   io_image);
-    MBOX_ATTR_WRITE (ATTR_SCRATCH7_VALID,          i_proc_target,   io_image);
+    MBOX_ATTR_WRITE (ATTR_I2C_BUS_DIV_REF,         i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_FUNCTIONAL_EQ_EC_VALID,  i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_EQ_GARD,                 i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_EC_GARD,                 i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_I2C_BUS_DIV_REF_VALID,   i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_FW_MODE_FLAGS_VALID,     i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_ISTEP_MODE,              i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_SBE_RUNTIME_MODE,        i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_IS_MPIPL,                FAPI_SYSTEM,     i_image);
+    MBOX_ATTR_WRITE (ATTR_IS_SP_MODE,              i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_SBE_FFDC_ENABLE,         i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_SBE_INTERNAL_FFDC_ENABLE, i_proc_target,  i_image);
+    MBOX_ATTR_WRITE (ATTR_BOOT_FREQUENCY_VALID,    i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_NEST_PLL_BUCKET,         FAPI_SYSTEM,     i_image);
+    MBOX_ATTR_WRITE (ATTR_BOOT_FREQ_MULT,          i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_HWP_CONTROL_FLAGS_VALID, i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_SYSTEM_IPL_PHASE,        FAPI_SYSTEM,     i_image);
+    MBOX_ATTR_WRITE (ATTR_SYS_FORCE_ALL_CORES,     FAPI_SYSTEM,     i_image);
+    MBOX_ATTR_WRITE (ATTR_RISK_LEVEL,              FAPI_SYSTEM,     i_image);
+    MBOX_ATTR_WRITE (ATTR_DISABLE_HBBL_VECTORS,    FAPI_SYSTEM,     i_image);
+    MBOX_ATTR_WRITE (ATTR_CHIP_SELECTION_VALID,    i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_CHIP_SELECTION,          i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_NODE_POS,                i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_CHIP_POS,                i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_SCRATCH6_VALID,          i_proc_target,   i_image);
+    MBOX_ATTR_WRITE (ATTR_SCRATCH7_VALID,          i_proc_target,   i_image);
 
 fapi_try_exit:
     FAPI_DBG ("writeMboxRegs Exiting...");
@@ -68,15 +68,31 @@ fapi_try_exit:
 
 fapi2::ReturnCode p9_xip_customize (
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target,
-    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_system_target,
-    void* io_image)
+    void*     i_image,
+    uint32_t& io_imageSize,
+    uint8_t   i_sysPhase,
+    void*     i_vpdUncompressedRings,
+    uint32_t  i_vpdRingsSize,
+    void*     i_overlaysUncompressedRings,
+    uint32_t  i_overlayRingsSize)
 {
     FAPI_DBG ("Entering p9_xip_customize...");
+    auto l_rc = 0;
 
-    FAPI_TRY(writeMboxRegs(i_proc_target, i_system_target, io_image),
+    FAPI_TRY(writeMboxRegs(i_proc_target, i_image),
              "p9_xip_customize: error writing mbox regs in SBE image rc=0x%.8x",
              (uint64_t)fapi2::current_err);
 
+    l_rc = p9_xip_image_size (i_image, &io_imageSize);
+
+    if (l_rc)
+    {
+        FAPI_ERR ("Error getting size of the input image");
+        fapi2::current_err = l_rc;
+        goto fapi_try_exit;
+    }
+
+    FAPI_DBG("Input Image Size is: %d", io_imageSize);
 
 fapi_try_exit:
     FAPI_DBG("Exiting p9_xip_customize");
diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H
index 0653ac1bb..9b8994927 100644
--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H
+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H
@@ -23,15 +23,42 @@
 
 typedef fapi2::ReturnCode (*p9_xip_customize_FP_t) (
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target,
-    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_system_target,
-    void* io_image);
+    void*     i_image,
+    uint32_t& io_imageSize,
+    uint8_t   i_sysPhase,
+    void*     i_vpdUncompressedRings,
+    uint32_t  i_vpdRingsSize,
+    void*     i_overlaysUncompressedRings,
+    uint32_t  i_overlayRingsSize);
 
 extern "C"
 {
+/// @brief p9_xip_customize used to customize the SBE/SEEPROM image with
+///        mailbox attributes and vpd rings
+/// @param[in] i_proc_target            => P9 proc chip target
+/// @param[in] i_image                  => Pointer to the in-memory SBE/SEEPROM image
+/// @param[in/out] io_imageSize         => Size of the sbe/seeprom image
+/// @param[in] i_sysPhase               => 0: SBE_IPL, 1: HB IPL
+/// @param[in] i_vpdUncompressedRings   => Pointer to in-memory buffer that can
+///                                        be used to keep uncompressed rings in
+/// @param[in] i_vpdRingsSize           => Size of the vpd rings buffer
+/// @param[in] i_overlaysUncompressedRings => Pointer to in-memory buffer for
+///                                           uncompressed overlay rings
+/// @param[in] i_overlayRingsSize       => Size of the overlay ring buffer
+//
+/// @note: the content of the image pointers will be changed upon return
+///
+/// @return FAPI_RC_SUCCESS if the customization was successful
+///
     fapi2::ReturnCode p9_xip_customize (
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target,
-        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_system_target,
-        void* io_image);
+        void*     i_image,
+        uint32_t& io_imageSize,
+        uint8_t   i_sysPhase,
+        void*     i_vpdUncompressedRings,
+        uint32_t  i_vpdRingsSize,
+        void*     i_overlaysUncompressedRings,
+        uint32_t  i_overlayRingsSize);
 
 }
 #endif