PM: Generation of summarized version of STOP Recovery FFDC.

A summary of STOP recovery FFDC is created after generation of
complete FFDC. It is stored at the end of FFDC section. It is
intended for copying to an error log created during second
phase of STOP Recovery. Commit also incorporates some changes
to support creation of PM Display from STOP Recovery FFDC.

Key_Cronus_Test=PM_REGRESS

CQ: SW416531
Change-Id: Ieb0bceeb141cc80b18f63b01e881e5ad3b50263d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50414
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

1 files changed, 74 insertions, 12 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index df71bacc..4e025dcc 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -572,6 +572,8 @@ HCD_CONST(FFDC_CPPM_MAGIC_NUM,        (0x4350504d)) //"CPPM"
 HCD_CONST(FFDC_QPPM_MAGIC_NUM,        (0x5150504d)) //"QPPM"
 HCD_CONST(FFDC_QUAD_MAGIC_NUM,        (0x51554144)) //"QUAD"
 HCD_CONST(FFDC_FIR_MAGIC_NUM,         (0x46495200)) //"FIR"
+HCD_CONST(FFDC_SUMM_MAGIC_NUM,        (0x53554d4d)) //"SUMM"
+HCD_CONST(FFDC_REG_NOT_FOUND,         (0x212d2d21)) //"!--!"
 
 // PM FFDC Region Layout Sizes
 HCD_CONST(FFDC_SCOM_REG_ID_VAL_SIZE,    12)
@@ -579,8 +581,8 @@ HCD_CONST(FFDC_SCOM_REG_ID_VAL_SIZE,    12)
 // PPE FFDC Section
 // section common to SGPE and PGPE FFDC
 
-// 27 CME internal regs, 10 CME regs, 1 buffer/pad
-HCD_CONST(FFDC_PPE_INTL_REGISTERS_MAX,  38)
+//31 CME internal regs, 10 CME regs, 1 buffer/pad
+HCD_CONST(FFDC_PPE_INTL_REGISTERS_MAX,  42)
 
 HCD_CONST(FFDC_PPE_HDR_SIZE ,           0x18)
 HCD_CONST(FFDC_PPE_SCORE_BOARD_SIZE,    0x200)
@@ -601,8 +603,9 @@ HCD_CONST(FFDC_PPE_BLOCK_SIZE,          (FFDC_PPE_HDR_SIZE +
           FFDC_PPE_TRACES_SIZE ))
 
 // FIR FFDC Section
-HCD_CONST(FFDC_PM_CME_FIR_REGISTERS_MAX, 1)
-HCD_CONST(FFDC_PM_FIR_REGISTERS_MAX,     2)
+// Includes FIR, its Mask and action registers
+HCD_CONST(FFDC_PM_CME_FIR_REGISTERS_MAX, 4)
+HCD_CONST(FFDC_PM_FIR_REGISTERS_MAX,     5)
 
 HCD_CONST(FFDC_FIR_HDR_SIZE ,           0x10)
 HCD_CONST(FFDC_CME_FIR_REGISTERS_SIZE,  (FFDC_PM_CME_FIR_REGISTERS_MAX*
@@ -617,14 +620,14 @@ HCD_CONST(FFDC_FIR_REGION_SIZE,         (FFDC_FIR_HDR_SIZE +
 HCD_CONST(FFDC_PPM_HDR_SIZE,            0x10)
 
 // Core PPM
-HCD_CONST(FFDC_CPPM_REGISTERS_MAX,      28)
+HCD_CONST(FFDC_CPPM_REGISTERS_MAX,      29)
 HCD_CONST(FFDC_CPPM_REGISTERS_SIZE,     (FFDC_CPPM_REGISTERS_MAX*
           FFDC_SCOM_REG_ID_VAL_SIZE))
 HCD_CONST(FFDC_CPPM_REGION_SIZE,        (FFDC_PPM_HDR_SIZE +
           FFDC_CPPM_REGISTERS_SIZE))
 
 // Quad PPM
-HCD_CONST(FFDC_QPPM_REGISTERS_MAX,      28) // 1 extra for pad
+HCD_CONST(FFDC_QPPM_REGISTERS_MAX,      62) // 1 extra for pad
 HCD_CONST(FFDC_QPPM_REGISTERS_SIZE,     (FFDC_QPPM_REGISTERS_MAX*
           FFDC_SCOM_REG_ID_VAL_SIZE))
 HCD_CONST(FFDC_QPPM_REGION_SIZE,        (FFDC_PPM_HDR_SIZE +
@@ -643,7 +646,7 @@ HCD_CONST(FFDC_SGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
 HCD_CONST(FFDC_PGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
 
 // OCC FFDC Section
-HCD_CONST(FFDC_OCC_REGISTERS_MAX,       202) // 1 extra for pad
+HCD_CONST(FFDC_OCC_REGISTERS_MAX,       230) // 1 extra for pad
 
 HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x20)
 HCD_CONST(FFDC_TRACE_ERR_SIZE,          (8 * ONE_KB))
@@ -665,21 +668,80 @@ HCD_CONST(FFDC_OCC_REGION_SIZE,         (FFDC_OCC_REGION_HDR_SIZE +
           FFDC_SHARED_SRAM_SIZE +
           FFDC_OCC_REGS_SIZE))
 
+
+//FFDC Summary Section
+
+HCD_CONST(FFDC_SUMMARY_SUB_SEC_VALID,   1 )  // FFDC sub-sec valid mark
+HCD_CONST(FFDC_SUMMARY_SUB_SEC_INVALID, 0 )  // FFDC sub-sec in-valid mark
+HCD_CONST(FFDC_SUMMARY_PPE_REG,         6 )  // 5 + 1 extra for pad
+HCD_CONST(FFDC_SUMMARY_CPPM_REG,        3 )  // 2  + 1 extra for pad
+HCD_CONST(FFDC_SUMMARY_QPPM_REG,        4 )  // 3  + 1 extra for pad
+HCD_CONST(FFDC_SUMMARY_PPE_REG_SIZE,    4 )
+HCD_CONST(FFDC_SUMMARY_SCOM_REG_SIZE,   8 )
+HCD_CONST(FFDC_SUMMARY_MAGIC_WORD_SIZE,   4 )
+HCD_CONST(FFDC_SUMMARY_SEC_HDR_SIZE,      4 )
+HCD_CONST(FFDC_SUMMARY_SYS_CNGF_REG,      5 ) // CCSR, QSSR, OCCFLAG1 OCCFLAG2 + 1 pad
+HCD_CONST(FFDC_SUMMARY_SYS_STATE_REG,     19 ) // 12 CME LFIR + OCC LFIR, PBAFIR + 4 OCC Reg + 1 Pad
+HCD_CONST(FFDC_SUMMARY_DASH_BOARD_BLOCK,  12 )
+HCD_CONST(FFDC_SUMMARY_DASH_BOARD_SUMM_SIZE,  (14 * FFDC_SUMMARY_DASH_BOARD_BLOCK ) ) // 12 CMEs + 1 SGPE + 1 PGPE
+HCD_CONST(FFDC_SUMMARY_SIZE_SYS_CONFIG,
+          (FFDC_SUMMARY_SYS_CNGF_REG* FFDC_SUMMARY_SCOM_REG_SIZE) )
+
+HCD_CONST(FFDC_SUMMARY_SIZE_SYS_STATE,
+          (FFDC_SUMMARY_SYS_STATE_REG* FFDC_SUMMARY_SCOM_REG_SIZE)  +
+          ( FFDC_SUMMARY_SEC_HDR_SIZE ) )
+
+HCD_CONST(FFDC_SUMMARY_OCC_PBA_FIR_SIZE, (2 * FFDC_SUMMARY_SCOM_REG_SIZE) )
+HCD_CONST(FFDC_SUMMARY_XIR_OFFSET,
+          (FFDC_SUMMARY_SEC_HDR_SIZE + FFDC_SUMMARY_SCOM_REG_SIZE) )
+
+HCD_CONST(FFDC_SUMMARY_SIZE_SGPE,
+          ( FFDC_SUMMARY_PPE_REG* FFDC_SUMMARY_PPE_REG_SIZE ) +
+          FFDC_SUMMARY_SEC_HDR_SIZE )
+
+HCD_CONST(FFDC_SUMMARY_SIZE_PGPE,
+          ( FFDC_SUMMARY_PPE_REG* FFDC_SUMMARY_PPE_REG_SIZE ) +
+          FFDC_SUMMARY_SEC_HDR_SIZE )
+
+HCD_CONST(FFDC_SUMMARY_SIZE_CME,
+          ( FFDC_SUMMARY_PPE_REG* FFDC_SUMMARY_PPE_REG_SIZE ) +
+          FFDC_SUMMARY_SEC_HDR_SIZE )    //PPE XIRS, and Pad
+
+HCD_CONST(FFDC_SUMMARY_SIZE_CPPM_REG,
+          ( FFDC_SUMMARY_CPPM_REG* FFDC_SUMMARY_SCOM_REG_SIZE ) +
+          FFDC_SUMMARY_SEC_HDR_SIZE )
+
+HCD_CONST(FFDC_SUMMARY_SIZE_QPPM_REG,
+          ( FFDC_SUMMARY_QPPM_REG* FFDC_SUMMARY_SCOM_REG_SIZE ) +
+          FFDC_SUMMARY_SEC_HDR_SIZE )
+
+HCD_CONST(FFDC_SUMMARY_MAJ_NUM,     1 )
+HCD_CONST(FFDC_SUMMARY_MIN_NUM,     0 )
+
+HCD_CONST(FFDC_SUMMARY_SIZE,      ( FFDC_SUMMARY_MAGIC_WORD_SIZE + FFDC_SUMMARY_SIZE_SYS_STATE +
+                                    FFDC_SUMMARY_SIZE_SGPE +
+                                    FFDC_SUMMARY_SIZE_PGPE +
+                                    (FFDC_SUMMARY_SIZE_CME* MAX_CMES_PER_CHIP ) +
+                                    (FFDC_SUMMARY_SIZE_CPPM_REG* MAX_CORES_PER_CHIP ) +
+                                    (FFDC_SUMMARY_SIZE_QPPM_REG* MAX_QUADS_PER_CHIP) +
+                                    FFDC_SUMMARY_DASH_BOARD_SUMM_SIZE ) )
+
 // Overall PM FFDC Section
 HCD_CONST(FFDC_PM_HEADER_SIZE,          0x38)
-HCD_CONST(FFDC_PM_REGION_SIZE,          (FFDC_PM_HEADER_SIZE +
+HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET,
+          (FFDC_REGION_QPMR_BASE_OFFSET + QPMR_HOMER_OFFSET))
+
+HCD_CONST(FFDC_PM_REGION_SIZE,          ( FFDC_PM_HEADER_SIZE +
           FFDC_FIR_REGION_SIZE +
-          (FFDC_QUAD_REGION_SIZE * 6) +
+          (FFDC_QUAD_REGION_SIZE* MAX_QUADS_PER_CHIP) +
           FFDC_SGPE_REGION_SIZE +
           FFDC_PGPE_REGION_SIZE +
-          FFDC_OCC_REGION_SIZE))
+          FFDC_OCC_REGION_SIZE ) + FFDC_SUMMARY_SIZE )
 
 HCD_CONST(DOPTRACE_OFFSET,
           (PPMR_HOMER_OFFSET + 64 * ONE_KB))
 HCD_CONST(DOPTRACE_LEN, 64 * ONE_KB)
 
 HCD_CONST(HOMER_OPTRACE_FFDC_OFFSET, (FFDC_REGION_QPMR_BASE_OFFSET + ONE_MB + FFDC_PM_REGION_SIZE))
-HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET,
-          (FFDC_REGION_QPMR_BASE_OFFSET + QPMR_HOMER_OFFSET))
 
 #endif /* __HCD_MEMMAP_BASE_H__ */