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authorMichael Floyd <mfloyd@us.ibm.com>2018-02-09 16:50:43 -0600
committerhostboot <hostboot@us.ibm.com>2018-03-22 14:07:29 -0500
commita521e07279224c2196ecdd4060e7fd057455c168 (patch)
tree5a5afdb1c06f45d8d76bce648cc4b5e7f3a85892 /import
parent01ab477e989bc6476a5727b3ef18ff8bf6ffe70a (diff)
downloadtalos-hcode-a521e07279224c2196ecdd4060e7fd057455c168.tar.gz
talos-hcode-a521e07279224c2196ecdd4060e7fd057455c168.zip
CME Size Reduction Fixes
-- sibling no longer clears g_eimr_override bit7 -- misplaced paren with invert mask for IRQ_VEC_STOP_C0_UPPER -- fixed comment and removed redundant code in pstate start for Enabling PMCR interrupts -- removed bad trace message in sibling during registration -- removed unneeded scom_data init to 0 -- removed annoying \n in cme pstate trace messages Key_Cronus_Test=PM_REGRESS Change-Id: If8d7e5bd322786bc9d9824ae4bb1aea6bcd6f322 Original-Change-Id: I651c7eac42c1cde65f6480304a7f66249c7e3e36 CQ: SW415503 RTC: 178789 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53794 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import')
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c11
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c6
2 files changed, 8 insertions, 9 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 9f926dce..d84b6896 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -63,7 +63,7 @@ void p9_cme_pstate_intercme_msg_handler(void)
void p9_cme_pstate_sibling_lock_and_intercme_protocol(uint32_t process_intercme_in0)
{
- PK_TRACE("SIBL: Enter\n");
+ PK_TRACE("SIBL: Enter");
uint32_t msg;
intercme_msg_recv(&msg, IMT_LOCK_SIBLING);
@@ -85,7 +85,7 @@ void p9_cme_pstate_sibling_lock_and_intercme_protocol(uint32_t process_intercme_
p9_cme_pstate_process_db0_sibling();
}
- PK_TRACE("SIBL: Enter\n");
+ PK_TRACE("SIBL: Enter");
}
void p9_cme_pstate_process_db0_sibling()
@@ -97,7 +97,7 @@ void p9_cme_pstate_process_db0_sibling()
//writes same value for both cores
CME_GETSCOM(CPPM_CMEDB0, G_cme_pstate_record.firstGoodCoreMask, dbData.value);
- PK_TRACE("INTER0: Enter\n");
+ PK_TRACE("INTER0: Enter");
dbQuadInfo = (dbData.value >> (in32(CME_LCL_SRTCH0) &
(BITS32(CME_SCRATCH_LOCAL_PSTATE_IDX_START, CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH)
@@ -113,9 +113,8 @@ void p9_cme_pstate_process_db0_sibling()
p9_cme_pstate_pmsr_updt();
- //Clear any pending PMCR interrupts
- g_eimr_override |= BITS64(34, 2);
- g_eimr_override &= ~(uint64_t)(G_cme_record.core_enabled << 28);
+ // Enable PMCR updates for good cores
+ g_eimr_override &= ~(uint64_t)(G_cme_record.core_enabled << SHIFT64(35));
//Clear Core GPMMR RESET_STATE_INDICATOR bit to show pstates have started
CME_PUTSCOM(PPM_GPMMR_CLR, G_cme_record.core_enabled, BIT64(15));
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
index fda77451..d414ef46 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
@@ -67,7 +67,7 @@ void cme_pstate_pmcr_action()
if (core & cm)
{
request = in64(CME_LCL_PMCRS0 + ((cm & 1) << 5)) & PMCR_LOWERPS_MASK;
- PK_TRACE_INF("PMCR: Fwd Core[%d] Pstate Request = 0x%02x\n", cm, (uint32_t)(request >> PMCR_PSTATE_SHIFT_AMOUNT));
+ PK_TRACE_INF("PMCR: Fwd Core[%d] Pstate Request = 0x%02x", cm, (uint32_t)(request >> PMCR_PSTATE_SHIFT_AMOUNT));
// Note that LowerPS coincidentally is in the correct place for the PIG payload
@@ -93,7 +93,7 @@ void p9_cme_pstate_pmcr_handler(void)
//
void p9_cme_init_done()
{
- PK_TRACE_INF("CME INIT DONE: Enter\n");
+ PK_TRACE_INF("CME INIT DONE: Enter");
uint32_t msg;
// Synchronization between QM and Sibling
@@ -118,5 +118,5 @@ void p9_cme_init_done()
// @todo RTC173279 rename this flag to CME_FLAGS_BOOT_DONE
out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PMCR_READY));
- PK_TRACE_INF("CME INIT DONE: Exit\n");
+ PK_TRACE_INF("CME INIT DONE: Exit");
}
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