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| author | Brian Silver <bsilver@us.ibm.com> | 2016-01-19 08:25:33 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 15:56:46 -0500 |
| commit | 0dc0322d8abafbfb9152970ce7a86f13ea65b5f9 (patch) | |
| tree | c9fca4bd5f15a5eeedd1a4d06195ac60868fb4b5 /import/chips | |
| parent | 20ac6113a49c9fbf44c536e9ad6ad5840719c63e (diff) | |
| download | talos-hcode-0dc0322d8abafbfb9152970ce7a86f13ea65b5f9.tar.gz talos-hcode-0dc0322d8abafbfb9152970ce7a86f13ea65b5f9.zip | |
Changes related to model 31, attr changes for sim latencies
Fix bug in ODT write config, using read config values
Turn off WL RTT Swap
Change VBU attribute file to include all sim cal steps
Change-Id: I75aa17dcc46cecd120cdcd1847ea7e28b82c4dc8
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23418
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Andre A. Marin <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips')
| -rw-r--r-- | import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index 2e05ef87..8685b816 100644 --- a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -53,4 +53,9 @@ REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC , 9 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , 0 ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WL_SWAP_ENABLE_P0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + 0 ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WR_CTL_SWAP_ENABLE_P0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + 0 ); + #endif |
