From 0dc0322d8abafbfb9152970ce7a86f13ea65b5f9 Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Tue, 19 Jan 2016 08:25:33 -0600 Subject: Changes related to model 31, attr changes for sim latencies Fix bug in ODT write config, using read config values Turn off WL RTT Swap Change VBU attribute file to include all sim cal steps Change-Id: I75aa17dcc46cecd120cdcd1847ea7e28b82c4dc8 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23418 Tested-by: Jenkins Server Reviewed-by: Craig C. Hamilton Reviewed-by: Andre A. Marin Reviewed-by: Jennifer A. Stofer --- import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'import/chips') diff --git a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index 2e05ef87..8685b816 100644 --- a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -53,4 +53,9 @@ REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC , 9 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , 0 ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WL_SWAP_ENABLE_P0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + 0 ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WR_CTL_SWAP_ENABLE_P0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + 0 ); + #endif -- cgit v1.2.1