STOP: CME/SGPE Hcode size reduction via global use of literals

Key_Cronus_Test=PM_REGRESS

Change-Id: I6ea9e7a29ad3a12b89eb59a4a557e9d96ef8e276
Original-Change-Id: Ic9ec56beff42f052e88bde98e90e01d44ac43e4f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58542
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

2 files changed, 48 insertions, 15 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 9cb875b0..d4ef5dff 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -71,6 +71,39 @@ extern "C" {
 #endif
 
 
+extern uint32_t G_OCB_CCSR;
+extern uint32_t G_OCB_QCSR;
+extern uint32_t G_OCB_QSSR;
+extern uint32_t G_OCB_QSSR_CLR;
+extern uint32_t G_OCB_QSSR_OR;
+extern uint32_t G_OCB_OCCFLG;
+extern uint32_t G_OCB_OCCFLG_CLR;
+extern uint32_t G_OCB_OCCFLG_OR;
+extern uint32_t G_OCB_OCCFLG2;
+extern uint32_t G_OCB_OCCS2;
+extern uint32_t G_OCB_OISR0_CLR;
+extern uint32_t G_OCB_OISR1;
+extern uint32_t G_OCB_OISR1_CLR;
+extern uint32_t G_OCB_OIMR0_CLR;
+extern uint32_t G_OCB_OIMR0_OR;
+extern uint32_t G_OCB_OIMR1_CLR;
+extern uint32_t G_OCB_OIMR1_OR;
+extern uint32_t G_OCB_OPIT0PRA;
+extern uint32_t G_OCB_OPIT2PRA;
+extern uint32_t G_OCB_OPIT3PRA;
+extern uint32_t G_OCB_OPIT6PRB;
+extern uint32_t G_OCB_OPIT0PRA_CLR;
+extern uint32_t G_OCB_OPIT1PRA_CLR;
+extern uint32_t G_OCB_OPIT2PRA_CLR;
+extern uint32_t G_OCB_OPIT3PRA_CLR;
+extern uint32_t G_OCB_OPIT4PRA_CLR;
+extern uint32_t G_OCB_OPIT5PRA_CLR;
+extern uint32_t G_OCB_OPIT6PRB_CLR;
+extern uint32_t G_OCB_OPIT7PRB_CLR;
+extern uint32_t G_OCB_OCCLFIR_AND;
+extern uint32_t G_GPE_GPE3TSEL;
+
+
 #define DEBUG_TRACE_CONTROL         0x100107D0
 #define L3TRA_TRACE_TRCTRL_CONFIG   0x10010402
 #define L3TRA_TRACE_TRDATA_CONFIG_0 0x10010403
@@ -181,7 +214,7 @@ extern "C" {
 
 
 #define PK_OPTIONAL_DEBUG_HALT(panic_code) \
-    if (in32(OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);}
+    if (in32(G_OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);}
 
 
 #define SGPE_STOP_QUAD_ERROR_HANDLER(quad_error, panic_code) \
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 1659055f..2c92bdb4 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -69,7 +69,7 @@ p9_sgpe_stop_entry()
     MARK_TAG(BEGINSCOPE_STOP_ENTRY, 0)
     //================================
 
-    if( in32(OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ))
+    if( in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ))
     {
         PK_TRACE_ERR("SGPE STOP ENTRY ERROR INJECT TRAP");
         PK_PANIC(SGPE_STOP_ENTRY_TRAP_INJECT);
@@ -154,7 +154,7 @@ p9_sgpe_stop_entry()
                 G_sgpe_stop_record.group.quad[VECTOR_ENTRY] |= BIT32(qloop);
 
                 ocb_qssr_t qssr = {0};
-                qssr.value      = in32(OCB_QSSR);
+                qssr.value      = in32(G_OCB_QSSR);
 
                 // check qssr for already stopped ex
                 G_sgpe_stop_record.group.ex01[qloop] =
@@ -420,7 +420,7 @@ p9_sgpe_stop_entry()
         }
 
         PK_TRACE("Update QSSR: stop_entry_ongoing");
-        out32(OCB_QSSR_OR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_OR, BIT32(qloop + 20));
 
         //====================================================
         MARK_TAG(SE_STOP_L2_CLKS, ((ex << 6) | (32 >> qloop)))
@@ -555,8 +555,8 @@ p9_sgpe_stop_entry()
         }
 
         PK_TRACE("Update QSSR: l2_stopped, drop stop_entry_ongoing");
-        out32(OCB_QSSR_CLR, BIT32(qloop + 20));
-        out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1)));
+        out32(G_OCB_QSSR_CLR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1)));
 
         PK_TRACE_DBG("SE.8C: L2 Clock Sync Dropped");
 
@@ -643,7 +643,7 @@ p9_sgpe_stop_entry()
         GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value);
 
         PK_TRACE("Update QSSR: stop_entry_ongoing");
-        out32(OCB_QSSR_OR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_OR, BIT32(qloop + 20));
 
         PK_TRACE_INF("SE.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex);
 
@@ -721,14 +721,14 @@ p9_sgpe_stop_entry()
 
 #if !SKIP_L3_PURGE_ABORT
 
-            if ((in32(OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) &&
+            if ((in32(G_OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) &&
                 // Skip L3 Purge Abort check if in Block Wakeup mode
                 (!(G_sgpe_stop_record.group.quad[VECTOR_BLOCKX] & BIT32(qloop))))
             {
                 PK_TRACE("Abort: interrupt detected");
 
-                if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) ||
-                    (in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4)))
+                if ((in32(G_OCB_OPIT2PRA) & BITS32((qloop << 2), 4)) ||
+                    (in32(G_OCB_OPIT3PRA) & BITS32((qloop << 2), 4)))
                 {
                     PK_TRACE("Abort: core interrupt detected");
 
@@ -746,7 +746,7 @@ p9_sgpe_stop_entry()
                     }
                 }
 
-                if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) &&
+                if ((in32(G_OCB_OPIT6PRB) & BIT32(qloop)) &&
                     (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT))
                 {
                     PK_TRACE_DBG("Abort: quad wakeup detected");
@@ -913,7 +913,7 @@ p9_sgpe_stop_entry()
         //   4. optionally finishes the entry (if not done above)
 
         if ((!ipc_quad_entry) &&
-            (in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+            (in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
             G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
             G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) // entry into STOP11
         {
@@ -1323,10 +1323,10 @@ p9_sgpe_stop_entry()
         GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value);
 
         PK_TRACE("Update QSSR: quad_stopped");
-        out32(OCB_QSSR_OR, BIT32(qloop + 14));
+        out32(G_OCB_QSSR_OR, BIT32(qloop + 14));
 
         PK_TRACE("Update QSSR: drop stop_entry_ongoing");
-        out32(OCB_QSSR_CLR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_CLR, BIT32(qloop + 20));
 
         G_sgpe_stop_record.state[qloop].act_state_q   = STOP_LEVEL_11;
         G_sgpe_stop_record.group.quad[VECTOR_ACTIVE] &= ~BIT32(qloop);
@@ -1343,7 +1343,7 @@ p9_sgpe_stop_entry()
 
 #if !SKIP_IPC
 
-    if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+    if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
         G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
         G_sgpe_stop_record.group.quad[VECTOR_ENTRY])
     {