STOP: CME/SGPE Hcode size reduction via global use of literals

Key_Cronus_Test=PM_REGRESS

Change-Id: I6ea9e7a29ad3a12b89eb59a4a557e9d96ef8e276
Original-Change-Id: Ic9ec56beff42f052e88bde98e90e01d44ac43e4f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58542
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

3 files changed, 87 insertions, 51 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 2b331fff..cb9c82d7 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -270,9 +270,9 @@ p9_cme_stop_entry()
     // pm_active is edge trigger because its level can be phantom
     // due to common-core constantly gives pm_active when core is stopped,
     // reading from EINR for raw signal, ignore EISR if EINR signal is gone
-    core     = (in32(CME_LCL_EISR) & BITS32(20, 2));
-    core_raw = (in32(CME_LCL_EINR) & BITS32(20, 2));
-    out32(CME_LCL_EISR_CLR, core);
+    core     = (in32(G_CME_LCL_EISR) & BITS32(20, 2));
+    core_raw = (in32(G_CME_LCL_EINR) & BITS32(20, 2));
+    out32(G_CME_LCL_EISR_CLR, core);
     core     = (core & core_raw) >> SHIFT32(21);
 
     // filter with partial good and running core mask
@@ -295,7 +295,7 @@ p9_cme_stop_entry()
     //       not implemented in DD1
     // bit1 is Recoverable Error
     // bit2 is Special Attention
-    if (((core & CME_MASK_C0) && (in32(CME_LCL_SISR)    & BITS32(13, 2))) ||
+    if (((core & CME_MASK_C0) && (in32(G_CME_LCL_SISR)    & BITS32(13, 2))) ||
         ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(61, 2))))
     {
         PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return");
@@ -435,10 +435,10 @@ p9_cme_stop_entry()
 #endif
 
             PK_TRACE("Request PCB mux via SICR[10/11]");
-            out32(CME_LCL_SICR_OR, core << SHIFT32(11));
+            out32(G_CME_LCL_SICR_OR, core << SHIFT32(11));
 
             // Poll Infinitely for PCB Mux Grant
-            while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core);
+            while((core & (in32(G_CME_LCL_SISR) >> SHIFT32(11))) != core);
 
             PK_TRACE("PCB Mux Granted on Core[%d]", core);
 
@@ -464,8 +464,8 @@ p9_cme_stop_entry()
                 // Note: Only Stop1 requires pulsing entry ack to pc,
                 //       thus this is NDD1 only as well.
                 PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]");
-                out32(CME_LCL_SICR_OR,  core_stop1 << SHIFT32(1));
-                out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1));
+                out32(G_CME_LCL_SICR_OR,  core_stop1 << SHIFT32(1));
+                out32(G_CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1));
 
                 if (core & CME_MASK_C0)
                 {
@@ -572,16 +572,16 @@ p9_cme_stop_entry()
             wrteei(0);
 
             PK_TRACE("HW407385: Assert block interrupt to PC via SICR[2/3]");
-            out32(CME_LCL_SICR_OR, core << SHIFT32(3));
+            out32(G_CME_LCL_SICR_OR, core << SHIFT32(3));
 
             PK_TRACE("HW407385: Waking up the core(pm_exit=1) via SICR[4/5]");
-            out32(CME_LCL_SICR_OR, core << SHIFT32(5));
+            out32(G_CME_LCL_SICR_OR, core << SHIFT32(5));
 
             CME_PM_EXIT_DELAY
 
             PK_TRACE("HW407385: Polling for core wakeup(pm_active=0) via EINR[20/21]");
 
-            while((in32(CME_LCL_EINR)) & (core << SHIFT32(21)));
+            while((in32(G_CME_LCL_EINR)) & (core << SHIFT32(21)));
 
             wrteei(1);
 
@@ -866,11 +866,11 @@ p9_cme_stop_entry()
             //=============================
 
             PK_TRACE("Assert halt STOP override disable via LMCR[14/15]");
-            out32(CME_LCL_LMCR_OR, (core << SHIFT32(15)));
+            out32(G_CME_LCL_LMCR_OR, (core << SHIFT32(15)));
 
 #if SPWU_AUTO
             PK_TRACE("Assert auto special wakeup disable via LMCR[12/13]");
-            out32(CME_LCL_LMCR_OR, (core << SHIFT32(13)));
+            out32(G_CME_LCL_LMCR_OR, (core << SHIFT32(13)));
 #endif
 
 
@@ -880,13 +880,13 @@ p9_cme_stop_entry()
 #endif
 
             PK_TRACE("Assert core-L2 + core-CC quiesces via SICR[6/7,8/9]");
-            out32(CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9)));
+            out32(G_CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9)));
 
             PK_TRACE("Poll for L2 interface quiesced via SISR[30/31]");
 
             do
             {
-                lclr_data = in32(CME_LCL_SISR);
+                lclr_data = in32(G_CME_LCL_SISR);
             }
             while((lclr_data & core) != core);
 
@@ -953,17 +953,17 @@ p9_cme_stop_entry()
             wrteei(0);
 
             PK_TRACE("HW407385: Drop pm_exit via SICR[4/5]");
-            out32(CME_LCL_SICR_CLR, core << SHIFT32(5));
+            out32(G_CME_LCL_SICR_CLR, core << SHIFT32(5));
 
             PK_TRACE("HW407385: Polling for core to stop(pm_active=1) via EINR[20/21]");
 
-            while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21)));
+            while((~(in32(G_CME_LCL_EINR))) & (core << SHIFT32(21)));
 
             PK_TRACE("HW407385: Clear pm_active status via EISR[20/21]");
-            out32(CME_LCL_EISR_CLR, core << SHIFT32(21));
+            out32(G_CME_LCL_EISR_CLR, core << SHIFT32(21));
 
             PK_TRACE("HW407385: Drop block interrupt to PC via SICR[2/3]");
-            out32(CME_LCL_SICR_CLR, core << SHIFT32(3));
+            out32(G_CME_LCL_SICR_CLR, core << SHIFT32(3));
 
             wrteei(1);
 
@@ -1201,13 +1201,13 @@ p9_cme_stop_entry()
                 break;
             }
 
-            core_catchup = (in32(CME_LCL_EISR) & BITS32(20, 2)) >> SHIFT32(21);
+            core_catchup = (in32(G_CME_LCL_EISR) & BITS32(20, 2)) >> SHIFT32(21);
             core_catchup = core_catchup & G_cme_record.core_enabled &
                            G_cme_stop_record.core_running;
 
             if (core_catchup)
             {
-                out32(CME_LCL_EISR_CLR, core_catchup << SHIFT32(21));
+                out32(G_CME_LCL_EISR_CLR, core_catchup << SHIFT32(21));
                 origin_core  = core;
                 origin_level = target_level;
                 core = core_catchup;
@@ -1240,13 +1240,14 @@ p9_cme_stop_entry()
             //===========================
 
 #if !SKIP_ABORT
+
             core_wakeup = core & (~G_cme_stop_record.core_blockwu);
-            out32(CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) |
+            out32(G_CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) |
                   (core_wakeup << SHIFT32(15)) |
                   (core_wakeup << SHIFT32(17)));
             sync();
             wrteei(0);
-            out32(CME_LCL_EIMR_OR, BITS32(10, 12));
+            out32(G_CME_LCL_EIMR_OR, BITS32(10, 12));
             wrteei(1);
 
 #endif
@@ -1292,7 +1293,7 @@ p9_cme_stop_entry()
             // bit2 is Special Attention
             // bit3 is Core Checkstop
 
-            if ((core & CME_MASK_C0) && (in32(CME_LCL_SISR) & BITS32(12, 4)))
+            if ((core & CME_MASK_C0) && (in32(G_CME_LCL_SISR) & BITS32(12, 4)))
             {
                 PK_TRACE_INF("WARNING: Core0 Xstop/Attn/Recov Present, Abort Entry");
                 core -= CME_MASK_C0;
@@ -1324,7 +1325,7 @@ p9_cme_stop_entry()
 
 #if !STOP_PRIME
 
-            if(in32(CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE))
+            if(in32(G_CME_LCL_FLAGS) & BIT32(CME_FLAGS_VDM_OPERABLE))
             {
                 PK_TRACE_DBG("Clear Poweron bit in VDMCR");
                 CME_PUTSCOM(PPM_VDMCR_CLR, core, BIT64(0));
@@ -1416,14 +1417,16 @@ p9_cme_stop_entry()
             //===========================
 
 #if !SKIP_ABORT
+
             core_wakeup = core & (~G_cme_stop_record.core_blockwu);
-            out32(CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) |
+            out32(G_CME_LCL_EIMR_CLR, (core_wakeup << SHIFT32(13)) |
                   (core_wakeup << SHIFT32(15)) |
                   (core_wakeup << SHIFT32(17)));
             sync();
             wrteei(0);
-            out32(CME_LCL_EIMR_OR, BITS32(10, 12));
+            out32(G_CME_LCL_EIMR_OR, BITS32(10, 12));
             wrteei(1);
+
 #endif
 
             //===================
@@ -1475,8 +1478,8 @@ p9_cme_stop_entry()
                 // insert tlbie quiesce before ncu purge to avoid window condition
                 // of ncu traffic still happening when purging starts
                 // Note: chtm purge and drop tlbie quiesce will be done in SGPE
-                out32(CME_LCL_SICR_OR, BIT32(18) | BIT32(21));
-                out32(CME_LCL_SICR_OR, BIT32(22));
+                out32(G_CME_LCL_SICR_OR, BIT32(18) | BIT32(21));
+                out32(G_CME_LCL_SICR_OR, BIT32(22));
 
                 PK_TRACE("Poll for purged done via EISR[22,23]");
 
@@ -1486,15 +1489,15 @@ p9_cme_stop_entry()
 #if !SKIP_L2_PURGE_ABORT
 
                     if (!core_aborted &&
-                        (in32(CME_LCL_EINR) & BITS32(12, 6)))
+                        (in32(G_CME_LCL_EINR) & BITS32(12, 6)))
                     {
-                        if (in32(CME_LCL_EINR) &
+                        if (in32(G_CME_LCL_EINR) &
                             (((core & CME_MASK_C0) ? BIT32(12) : 0) | BIT32(14) | BIT32(16)))
                         {
                             core_aborted |= CME_MASK_C0;
                         }
 
-                        if (in32(CME_LCL_EINR) &
+                        if (in32(G_CME_LCL_EINR) &
                             (((core & CME_MASK_C1) ? BIT32(13) : 0) | BIT32(15) | BIT32(17)))
                         {
                             core_aborted |= CME_MASK_C1;
@@ -1507,17 +1510,17 @@ p9_cme_stop_entry()
                             //=======================================
 
                             PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted);
-                            out32(CME_LCL_SICR_OR, BIT32(19) | BIT32(23));
+                            out32(G_CME_LCL_SICR_OR, BIT32(19) | BIT32(23));
                         }
                     }
 
 #endif
 
                 }
-                while((in32(CME_LCL_EISR) & BITS32(22, 2)) != BITS32(22, 2));
+                while((in32(G_CME_LCL_EISR) & BITS32(22, 2)) != BITS32(22, 2));
 
                 PK_TRACE("Drop L2+NCU purges and their possible aborts via SICR[18,19,22,23]");
-                out32(CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2)));
+                out32(G_CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2)));
 
                 PK_TRACE_DBG("SE.5A: L2 and NCU Purged");
 
@@ -1630,7 +1633,7 @@ p9_cme_stop_entry()
             sync();
 
             PK_TRACE("Clear special/regular wakeup after wakeup_notify = 1 since it is edge triggered");
-            out32(CME_LCL_EISR_CLR, (core << SHIFT32(15)) | (core << SHIFT32(17)));
+            out32(G_CME_LCL_EISR_CLR, (core << SHIFT32(15)) | (core << SHIFT32(17)));
 
             PK_TRACE_INF("SE.5B: Core[%d] Handed off to SGPE", core);
 
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 9cb875b0..d4ef5dff 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -71,6 +71,39 @@ extern "C" {
 #endif
 
 
+extern uint32_t G_OCB_CCSR;
+extern uint32_t G_OCB_QCSR;
+extern uint32_t G_OCB_QSSR;
+extern uint32_t G_OCB_QSSR_CLR;
+extern uint32_t G_OCB_QSSR_OR;
+extern uint32_t G_OCB_OCCFLG;
+extern uint32_t G_OCB_OCCFLG_CLR;
+extern uint32_t G_OCB_OCCFLG_OR;
+extern uint32_t G_OCB_OCCFLG2;
+extern uint32_t G_OCB_OCCS2;
+extern uint32_t G_OCB_OISR0_CLR;
+extern uint32_t G_OCB_OISR1;
+extern uint32_t G_OCB_OISR1_CLR;
+extern uint32_t G_OCB_OIMR0_CLR;
+extern uint32_t G_OCB_OIMR0_OR;
+extern uint32_t G_OCB_OIMR1_CLR;
+extern uint32_t G_OCB_OIMR1_OR;
+extern uint32_t G_OCB_OPIT0PRA;
+extern uint32_t G_OCB_OPIT2PRA;
+extern uint32_t G_OCB_OPIT3PRA;
+extern uint32_t G_OCB_OPIT6PRB;
+extern uint32_t G_OCB_OPIT0PRA_CLR;
+extern uint32_t G_OCB_OPIT1PRA_CLR;
+extern uint32_t G_OCB_OPIT2PRA_CLR;
+extern uint32_t G_OCB_OPIT3PRA_CLR;
+extern uint32_t G_OCB_OPIT4PRA_CLR;
+extern uint32_t G_OCB_OPIT5PRA_CLR;
+extern uint32_t G_OCB_OPIT6PRB_CLR;
+extern uint32_t G_OCB_OPIT7PRB_CLR;
+extern uint32_t G_OCB_OCCLFIR_AND;
+extern uint32_t G_GPE_GPE3TSEL;
+
+
 #define DEBUG_TRACE_CONTROL         0x100107D0
 #define L3TRA_TRACE_TRCTRL_CONFIG   0x10010402
 #define L3TRA_TRACE_TRDATA_CONFIG_0 0x10010403
@@ -181,7 +214,7 @@ extern "C" {
 
 
 #define PK_OPTIONAL_DEBUG_HALT(panic_code) \
-    if (in32(OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);}
+    if (in32(G_OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) {PK_PANIC(panic_code);}
 
 
 #define SGPE_STOP_QUAD_ERROR_HANDLER(quad_error, panic_code) \
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 1659055f..2c92bdb4 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -69,7 +69,7 @@ p9_sgpe_stop_entry()
     MARK_TAG(BEGINSCOPE_STOP_ENTRY, 0)
     //================================
 
-    if( in32(OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ))
+    if( in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ))
     {
         PK_TRACE_ERR("SGPE STOP ENTRY ERROR INJECT TRAP");
         PK_PANIC(SGPE_STOP_ENTRY_TRAP_INJECT);
@@ -154,7 +154,7 @@ p9_sgpe_stop_entry()
                 G_sgpe_stop_record.group.quad[VECTOR_ENTRY] |= BIT32(qloop);
 
                 ocb_qssr_t qssr = {0};
-                qssr.value      = in32(OCB_QSSR);
+                qssr.value      = in32(G_OCB_QSSR);
 
                 // check qssr for already stopped ex
                 G_sgpe_stop_record.group.ex01[qloop] =
@@ -420,7 +420,7 @@ p9_sgpe_stop_entry()
         }
 
         PK_TRACE("Update QSSR: stop_entry_ongoing");
-        out32(OCB_QSSR_OR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_OR, BIT32(qloop + 20));
 
         //====================================================
         MARK_TAG(SE_STOP_L2_CLKS, ((ex << 6) | (32 >> qloop)))
@@ -555,8 +555,8 @@ p9_sgpe_stop_entry()
         }
 
         PK_TRACE("Update QSSR: l2_stopped, drop stop_entry_ongoing");
-        out32(OCB_QSSR_CLR, BIT32(qloop + 20));
-        out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1)));
+        out32(G_OCB_QSSR_CLR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1)));
 
         PK_TRACE_DBG("SE.8C: L2 Clock Sync Dropped");
 
@@ -643,7 +643,7 @@ p9_sgpe_stop_entry()
         GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value);
 
         PK_TRACE("Update QSSR: stop_entry_ongoing");
-        out32(OCB_QSSR_OR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_OR, BIT32(qloop + 20));
 
         PK_TRACE_INF("SE.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex);
 
@@ -721,14 +721,14 @@ p9_sgpe_stop_entry()
 
 #if !SKIP_L3_PURGE_ABORT
 
-            if ((in32(OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) &&
+            if ((in32(G_OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) &&
                 // Skip L3 Purge Abort check if in Block Wakeup mode
                 (!(G_sgpe_stop_record.group.quad[VECTOR_BLOCKX] & BIT32(qloop))))
             {
                 PK_TRACE("Abort: interrupt detected");
 
-                if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) ||
-                    (in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4)))
+                if ((in32(G_OCB_OPIT2PRA) & BITS32((qloop << 2), 4)) ||
+                    (in32(G_OCB_OPIT3PRA) & BITS32((qloop << 2), 4)))
                 {
                     PK_TRACE("Abort: core interrupt detected");
 
@@ -746,7 +746,7 @@ p9_sgpe_stop_entry()
                     }
                 }
 
-                if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) &&
+                if ((in32(G_OCB_OPIT6PRB) & BIT32(qloop)) &&
                     (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT))
                 {
                     PK_TRACE_DBG("Abort: quad wakeup detected");
@@ -913,7 +913,7 @@ p9_sgpe_stop_entry()
         //   4. optionally finishes the entry (if not done above)
 
         if ((!ipc_quad_entry) &&
-            (in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+            (in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
             G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
             G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) // entry into STOP11
         {
@@ -1323,10 +1323,10 @@ p9_sgpe_stop_entry()
         GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value);
 
         PK_TRACE("Update QSSR: quad_stopped");
-        out32(OCB_QSSR_OR, BIT32(qloop + 14));
+        out32(G_OCB_QSSR_OR, BIT32(qloop + 14));
 
         PK_TRACE("Update QSSR: drop stop_entry_ongoing");
-        out32(OCB_QSSR_CLR, BIT32(qloop + 20));
+        out32(G_OCB_QSSR_CLR, BIT32(qloop + 20));
 
         G_sgpe_stop_record.state[qloop].act_state_q   = STOP_LEVEL_11;
         G_sgpe_stop_record.group.quad[VECTOR_ACTIVE] &= ~BIT32(qloop);
@@ -1343,7 +1343,7 @@ p9_sgpe_stop_entry()
 
 #if !SKIP_IPC
 
-    if ((in32(OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
+    if ((in32(G_OCB_OCCS2) & BIT32(PGPE_ACTIVE)) &&
         G_sgpe_stop_record.wof.update_pgpe != IPC_SGPE_PGPE_UPDATE_PGPE_HALTED &&
         G_sgpe_stop_record.group.quad[VECTOR_ENTRY])
     {