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| author | Rahul Batra <rbatra@us.ibm.com> | 2017-08-24 16:44:00 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 19:10:32 -0500 |
| commit | 46ac80391d6fd81a7219c5fd9d6b79ff07ffd2bb (patch) | |
| tree | c1a47675e577d0b0146c0c8c6006ad010c6a942b /import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c | |
| parent | 387b1772caa4f272b812b355862ce8e8ca6caa57 (diff) | |
| download | talos-hcode-46ac80391d6fd81a7219c5fd9d6b79ff07ffd2bb.tar.gz talos-hcode-46ac80391d6fd81a7219c5fd9d6b79ff07ffd2bb.zip | |
PSTATE/STOP: Pstate-Stop interaction fixes
Change-Id: Ifbbecdffc7a18382217b3c0a691912f311407336
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45138
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c')
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c index a000563b..4d41a679 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c @@ -244,15 +244,19 @@ void p9_pgpe_irq_handler_pcb_type4(void* arg, PkIrqId irq) p9_pgpe_pstate_do_auction(); p9_pgpe_pstate_apply_clips(); - //Write CME_SCRATCH register + //Write CME_SCRATCH and PMSR0/1 registers if (qcsr.fields.ex_config & (0x800 >> (q << 1))) { + //CME_Scratch GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value); value |= ((uint64_t)(MAX_QUADS - 1 - q) << 3) << 32; + value |= BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value); - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(2)); + + //PMSR0/1 value = ((uint64_t)G_pgpe_pstate_record.psClipMax[q] << SHIFT64(23)) | ((uint64_t)G_pgpe_pstate_record.psClipMin[q] << SHIFT64(31)); + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(2)); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_PMSRS0, q, 0), value); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_PMSRS1, q, 0), value); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 0), BIT64(2)); @@ -260,9 +264,13 @@ void p9_pgpe_irq_handler_pcb_type4(void* arg, PkIrqId irq) if (qcsr.fields.ex_config & (0x400 >> (q << 1))) { + //CME_Scratch GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value); value |= ((uint64_t)(MAX_QUADS - 1 - q) << 3) << 32; + value |= BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value); + + //PMSR0/1 value = ((uint64_t)G_pgpe_pstate_record.psClipMax[q] << SHIFT64(23)) | ((uint64_t)G_pgpe_pstate_record.psClipMin[q] << SHIFT64(31)); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(2)); |
