PSTATE/STOP: Pstate-Stop interaction fixes

Change-Id: Ifbbecdffc7a18382217b3c0a691912f311407336
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45138
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

6 files changed, 89 insertions, 49 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
index 928b1db2..a18b2d20 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
+++ b/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
@@ -217,6 +217,7 @@ enum PM_CME_FLAGS_DEFS
 //
 enum PM_CME_SCRATCH_DEFS
 {
+    CME_SCRATCH_DB0_PROCESSING_ENABLE        = 25,
     CME_SCRATCH_LOCAL_PSTATE_IDX_START       = 26,
     CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH      = 6
 };
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 3467d98b..fdfd0e90 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -105,8 +105,6 @@ void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
         p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
 
         //Clear any pending PMCR interrupts
-        out32_sh(CME_LCL_EISR_CLR, G_cme_record.core_enabled << 28);
-        out32_sh(CME_LCL_EIMR_CLR, G_cme_record.core_enabled << 28);//Enable PMCR0/1
         g_eimr_override |= BITS64(34, 2);
         g_eimr_override &= ~(uint64_t)(G_cme_record.core_enabled << 28);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
index 4c8f0b9a..483e572f 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
@@ -375,54 +375,57 @@ inline void p9_cme_pstate_process_db0()
 
     PK_TRACE_INF("DB_TH: DB0 0x%x\n"dbData.value);
 
-    //Process DB0
-    //Start Pstates and Pstates NOT enabled
-    if(G_dbData.fields.cme_message_number0 == MSGID_DB0_START_PSTATE_BROADCAST &&
-       !(G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED)))
+    if (in32(CME_LCL_SRTCH0) & BIT32(CME_SCRATCH_DB0_PROCESSING_ENABLE))
     {
-        p9_cme_pstate_db0_start();
-    }
-    //Global Actual Broadcast and Pstates enabled
-    else if(G_dbData.fields.cme_message_number0 == MSGID_DB0_GLOBAL_ACTUAL_BROADCAST)
-    {
-        //Process Global Bcast only if Pstates are enabled.
-        //Otherwise, ignore. The reason is PGPE multicasts Global Bcast, and doorbell0
-        //can be written while this CME is powered-off. For Pstate Start and Stop
-        //PGPE only unicasts.
-        if (G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED))
+        //Process DB0
+        //Start Pstates and Pstates NOT enabled
+        if(G_dbData.fields.cme_message_number0 == MSGID_DB0_START_PSTATE_BROADCAST &&
+           !(G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED)))
         {
-            p9_cme_pstate_db0_glb_bcast();
+            p9_cme_pstate_db0_start();
         }
-    }
-    //Stop Pstates and Pstates enabled
-    else if(G_dbData.fields.cme_message_number0 == MSGID_DB0_STOP_PSTATE_BROADCAST &&
-            (G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED)))
-    {
-        p9_cme_pstate_db0_suspend();
-    }
-    //Pmin or Pmax Update
-    else if(G_dbData.fields.cme_message_number0 == MSGID_DB0_CLIP_BROADCAST &&
-            (G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED)))
-    {
-        p9_cme_pstate_db0_clip_bcast();
-    }
-    //Otherwise, send an ERR ACK to PGPE and Halt
-    else
-    {
-        ppmPigData.value = 0;
-        ppmPigData.fields.req_intr_type = 4;
-        ppmPigData.fields.req_intr_payload = MSGID_PCB_TYPE4_ACK_ERROR;
-        send_pig_packet(ppmPigData.value, G_cme_pstate_record.cmeMaskGoodCore);
-        PK_TRACE_INF("DB_TH: Bad DB0=0x%x Pstate=0x%x", G_dbData.fields.cme_message_number0, G_cme_flags);
-
-        if(G_dbData.fields.cme_message_number0 < MSGID_DB0_VALID_START ||
-           G_dbData.fields.cme_message_number0 > MSGID_DB0_VALID_END)
+        //Global Actual Broadcast and Pstates enabled
+        else if(G_dbData.fields.cme_message_number0 == MSGID_DB0_GLOBAL_ACTUAL_BROADCAST)
+        {
+            //Process Global Bcast only if Pstates are enabled.
+            //Otherwise, ignore. The reason is PGPE multicasts Global Bcast, and doorbell0
+            //can be written while this CME is powered-off. For Pstate Start and Stop
+            //PGPE only unicasts.
+            if (G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED))
+            {
+                p9_cme_pstate_db0_glb_bcast();
+            }
+        }
+        //Stop Pstates and Pstates enabled
+        else if(G_dbData.fields.cme_message_number0 == MSGID_DB0_STOP_PSTATE_BROADCAST &&
+                (G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED)))
+        {
+            p9_cme_pstate_db0_suspend();
+        }
+        //Pmin or Pmax Update
+        else if(G_dbData.fields.cme_message_number0 == MSGID_DB0_CLIP_BROADCAST &&
+                (G_cme_flags & BIT32(CME_FLAGS_PSTATES_ENABLED)))
         {
-            PK_PANIC(CME_PSTATE_UNEXPECTED_DB0_MSGID);
+            p9_cme_pstate_db0_clip_bcast();
         }
+        //Otherwise, send an ERR ACK to PGPE and Halt
         else
         {
-            PK_PANIC(CME_PSTATE_INVALID_DB0_MSGID);
+            ppmPigData.value = 0;
+            ppmPigData.fields.req_intr_type = 4;
+            ppmPigData.fields.req_intr_payload = MSGID_PCB_TYPE4_ACK_ERROR;
+            send_pig_packet(ppmPigData.value, G_cme_pstate_record.cmeMaskGoodCore);
+            PK_TRACE_INF("DB_TH: Bad DB0=0x%x Pstate=0x%x", G_dbData.fields.cme_message_number0, G_cme_flags);
+
+            if(G_dbData.fields.cme_message_number0 < MSGID_DB0_VALID_START ||
+               G_dbData.fields.cme_message_number0 > MSGID_DB0_VALID_END)
+            {
+                PK_PANIC(CME_PSTATE_UNEXPECTED_DB0_MSGID);
+            }
+            else
+            {
+                PK_PANIC(CME_PSTATE_INVALID_DB0_MSGID);
+            }
         }
     }
 
@@ -478,12 +481,9 @@ inline void p9_cme_pstate_db0_start()
     send_pig_packet(ppmPigData.value, G_cme_pstate_record.cmeMaskGoodCore);
 
     //Clear Pending PMCR interrupts and Enable PMCR Interrupts (for good cores)
-    out32_sh(CME_LCL_EISR_CLR, G_cme_record.core_enabled << 28 );
-    out32_sh(CME_LCL_EIMR_CLR, G_cme_record.core_enabled << 28 );
     g_eimr_override |= BITS64(34, 2);
     g_eimr_override &= ~(uint64_t)(G_cme_record.core_enabled << 28);
 
-
     //Clear Core GPMMR RESET_STATE_INDICATOR bit to show pstates have started
     CME_PUTSCOM(PPM_GPMMR_CLR, G_cme_record.core_enabled, BIT64(15));
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
index 2ed81f30..ed42780c 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
@@ -64,6 +64,7 @@ enum PGPE_DEFINES
 {
     QUAD0_MASK        = 0x80,
     CORE0_MASK        = 0x80000000,
+    QUAD0_ALL_CORES_MASK = 0xF0000000
 };
 
 enum PSTATE_START_SOURCE
@@ -78,6 +79,9 @@ enum PSTATE_START_SOURCE
 #define QUAD_MASK(quad) \
     (QUAD0_MASK >> quad)
 
+#define QUAD_ALL_CORES_MASK(quad) \
+    (QUAD0_ALL_CORES_MASK >> (quad<<2))
+
 #define FIRST_CORE_FROM_QUAD(quad) \
     ((quad) << 2)
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
index a000563b..4d41a679 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
@@ -244,15 +244,19 @@ void p9_pgpe_irq_handler_pcb_type4(void* arg, PkIrqId irq)
                 p9_pgpe_pstate_do_auction();
                 p9_pgpe_pstate_apply_clips();
 
-                //Write CME_SCRATCH register
+                //Write CME_SCRATCH and PMSR0/1 registers
                 if (qcsr.fields.ex_config &  (0x800 >> (q << 1)))
                 {
+                    //CME_Scratch
                     GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value);
                     value |= ((uint64_t)(MAX_QUADS - 1 - q) << 3) << 32;
+                    value |= BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE);
                     GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value);
-                    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(2));
+
+                    //PMSR0/1
                     value = ((uint64_t)G_pgpe_pstate_record.psClipMax[q] << SHIFT64(23)) | ((uint64_t)G_pgpe_pstate_record.psClipMin[q] <<
                             SHIFT64(31));
+                    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(2));
                     GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_PMSRS0, q, 0), value);
                     GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_PMSRS1, q, 0), value);
                     GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 0), BIT64(2));
@@ -260,9 +264,13 @@ void p9_pgpe_irq_handler_pcb_type4(void* arg, PkIrqId irq)
 
                 if (qcsr.fields.ex_config &  (0x400 >> (q << 1)))
                 {
+                    //CME_Scratch
                     GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value);
                     value |= ((uint64_t)(MAX_QUADS - 1 - q) << 3) << 32;
+                    value |= BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE);
                     GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value);
+
+                    //PMSR0/1
                     value = ((uint64_t)G_pgpe_pstate_record.psClipMax[q] << SHIFT64(23)) | ((uint64_t)G_pgpe_pstate_record.psClipMin[q] <<
                             SHIFT64(31));
                     GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(2));
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 1b3d294c..a0697f55 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -617,9 +617,13 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
 
             if (qcsr.fields.ex_config &  (0x800 >> (q << 1)))
             {
+                //CME Scratch0
                 GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value);
                 value |= (uint64_t)((MAX_QUADS - 1 - q) << 3) << 32;
+                value |= BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE);
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value);
+
+                //PMSR0/1
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(2));
                 value = 0;
                 value |= (pmin << SHIFT64(23));
@@ -631,9 +635,13 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
 
             if (qcsr.fields.ex_config &  (0x400 >> (q << 1)))
             {
+                //CME Scratch0
                 GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value);
                 value |= (uint64_t)((MAX_QUADS - 1 - q) << 3) << 32;
+                value |= BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE);
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value);
+
+                //PMSR0/1
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(2));
                 value = 0;
                 value |= (pmin << SHIFT64(23));
@@ -870,6 +878,9 @@ void p9_pgpe_pstate_process_quad_entry_notify(uint32_t quadsRequested)
     uint32_t q;
     qppm_dpll_freq_t dpllFreq;
     dpllFreq.value = 0;
+    ocb_qcsr_t qcsr;
+    qcsr.value = in32(OCB_QCSR);
+    uint64_t value;
 
     G_pgpe_pstate_record.activeQuads &= ~quadsRequested;
 
@@ -880,7 +891,25 @@ void p9_pgpe_pstate_process_quad_entry_notify(uint32_t quadsRequested)
         if (quadsRequested & QUAD_MASK(q))
         {
             GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, q), BIT64(26)); //Open DPLL for SCOMs
-            G_pgpe_pstate_record.activeCores &= ~(0xF >> (q << 2));
+
+            G_pgpe_pstate_record.activeCores &= ~(QUAD_ALL_CORES_MASK(q));
+            out32(OCB_OPIT4PRA_CLR, QUAD_ALL_CORES_MASK(q)); //Clear any pending PCB_Type4
+
+            //CME_Scratch0[DB0_PROCESSING_ENABLE]=0
+            if (qcsr.fields.ex_config &  (0x800 >> (q << 1)))
+            {
+                GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value);
+                value &= ~BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE);
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 0), value);
+            }
+
+            if (qcsr.fields.ex_config &  (0x400 >> (q << 1)))
+            {
+                GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value);
+                value &= ~BIT64(CME_SCRATCH_DB0_PROCESSING_ENABLE);
+                GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0, q, 1), value);
+            }
+
 
             if (G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE)
             {