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author | Rahul Batra <rbatra@us.ibm.com> | 2018-10-30 17:25:33 -0500 |
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committer | hostboot <hostboot@us.ibm.com> | 2018-12-11 10:41:04 -0600 |
commit | 9bc92eb0e16930a501eab0eb2db3e1aaba3c0465 (patch) | |
tree | 92782841230b6884f1260a5f8ca8cc42d85a538d /import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c | |
parent | bb0509e82ee86fe801911fb6563df7e317ed1592 (diff) | |
download | talos-hcode-9bc92eb0e16930a501eab0eb2db3e1aaba3c0465.tar.gz talos-hcode-9bc92eb0e16930a501eab0eb2db3e1aaba3c0465.zip |
PM: Fix default aux task
Key_Cronus_Test=PM_REGRESS
Change-Id: Icdfe0f0f30402257637ef4cf851653ec151675bf
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68199
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c')
-rw-r--r-- | import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c index 65fa03ee..708b1c4a 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c @@ -29,6 +29,7 @@ #include "p9_pgpe_header.h" #include <p9_hcd_memmap_occ_sram.H> #include "p9_pgpe_optrace.h" +#include "occhw_shared_data.h" #define AUX_TASK 14 #define GPE2TSEL 0xC0020000 @@ -97,6 +98,12 @@ void p9_pgpe_fit_init() if(aux_period) //multiply by attribute if nonzero { + //If auxilary task is enabled, then fills up the fields in OCC Complex Shared SRAM + //NOte: PGPE ends up writing gpe3 area, but this is because in future aux task will + //move to GPE3. So, to have continuity for aux task interface, we are writing + //it through GPE2 for now. + OSD_PTR->occ_comp_shr_data.gpe3_data.aux_region_start = OCC_SRAM_AUX_TASK_ADDR; + OSD_PTR->occ_comp_shr_data.gpe3_data.aux_region_length = PGPE_AUX_TASK_SIZE; G_aux_task_count_threshold *= aux_period; } |