PM: Fix default aux task

    Key_Cronus_Test=PM_REGRESS

Change-Id: Icdfe0f0f30402257637ef4cf851653ec151675bf
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68199
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

3 files changed, 17 insertions, 26 deletions

diff --git a/import/chips/p9/common/pmlib/occlib/occhw_shared_data.h b/import/chips/p9/common/pmlib/occlib/occhw_shared_data.h
index 817a55ef..f781f25a 100644
--- a/import/chips/p9/common/pmlib/occlib/occhw_shared_data.h
+++ b/import/chips/p9/common/pmlib/occlib/occhw_shared_data.h
@@ -75,7 +75,9 @@ typedef struct gpe3_occ_sram_region_data
     uint32_t gpe3_sram_region_start; //GPE3 sram region starting address
     uint32_t gpe3_image_header_addr;
     uint32_t gpe3_debug_header_addr;
-    uint8_t  reserved[52];
+    uint8_t  reserved[44];
+    uint32_t aux_region_start;
+    uint32_t aux_region_length;
 } gpe3_occ_sram_region_data_t;
 
 //OCC Complex Shared Data.
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/boot/p9_pgpe_aux_task.c b/import/chips/p9/procedures/ppe_closed/pgpe/boot/p9_pgpe_aux_task.c
index 8a1fac76..298f9cd3 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/boot/p9_pgpe_aux_task.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/boot/p9_pgpe_aux_task.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2017                                                         */
+/* COPYRIGHT 2017,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -30,33 +30,15 @@
 #include "pk.h"
 #include "ppe42.h"
 
-#define BUFFER_BASE         (0xFFF2B800 - 0x100)
-#define IDX                 (BUFFER_BASE - 4)
-#define SRAM_MAX             0xFFF2B7FC
-#define QUAD_PS_CURR_ADDR_0  0xFFF2025C
-#define QUAD_PS_CURR_ADDR_1 (QUAD_PS_CURR_ADDR_0 + 0x4)
 
-uint32_t buffer_address;
+#define BUFFER_SIZE 32
+uint8_t buffer[BUFFER_SIZE];
 void aux_task()
 {
-    if(buffer_address < BUFFER_BASE)//handles initialization
+    uint32_t i;
+
+    for (i = 0; i < BUFFER_SIZE; i++)
     {
-        buffer_address = BUFFER_BASE;
+        buffer[i] = i;
     }
-
-    /* get pstates */
-    uint32_t data;
-    uint32_t temp;
-
-    temp = in32(QUAD_PS_CURR_ADDR_0);
-    data = (temp << 16);
-    temp = in32(QUAD_PS_CURR_ADDR_1);
-    data |= (temp >> 16);
-
-    /* write pstates */
-    out32(buffer_address, data);
-    buffer_address = (buffer_address == SRAM_MAX) ? BUFFER_BASE : (buffer_address + 0x4);
-    out32(buffer_address, ((temp & 0xFFFF) << 16));
-    buffer_address = (buffer_address == SRAM_MAX) ? BUFFER_BASE : (buffer_address + 0x4);
-    out32(IDX, buffer_address);
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index 65fa03ee..708b1c4a 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -29,6 +29,7 @@
 #include "p9_pgpe_header.h"
 #include <p9_hcd_memmap_occ_sram.H>
 #include "p9_pgpe_optrace.h"
+#include "occhw_shared_data.h"
 
 #define AUX_TASK 14
 #define GPE2TSEL 0xC0020000
@@ -97,6 +98,12 @@ void p9_pgpe_fit_init()
 
     if(aux_period) //multiply by attribute if nonzero
     {
+        //If auxilary task is enabled, then fills up the fields in OCC Complex Shared SRAM
+        //NOte: PGPE ends up writing gpe3 area, but this is because in future aux task will
+        //move to GPE3. So, to have continuity for aux task interface, we are writing
+        //it through GPE2 for now.
+        OSD_PTR->occ_comp_shr_data.gpe3_data.aux_region_start = OCC_SRAM_AUX_TASK_ADDR;
+        OSD_PTR->occ_comp_shr_data.gpe3_data.aux_region_length =  PGPE_AUX_TASK_SIZE;
         G_aux_task_count_threshold *= aux_period;
     }