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author | Yue Du <daviddu@us.ibm.com> | 2017-07-10 23:25:45 -0500 |
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committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 18:27:45 -0500 |
commit | 163b4a1ffb4f12707a8a2dbbc909d5ef737bddac (patch) | |
tree | 4373376b3b92846725825939b8a83792c1b8785e /import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c | |
parent | a0488da1959604566126c97327649d60a13260df (diff) | |
download | talos-hcode-163b4a1ffb4f12707a8a2dbbc909d5ef737bddac.tar.gz talos-hcode-163b4a1ffb4f12707a8a2dbbc909d5ef737bddac.zip |
STOP: Fix block Entry and Exit
Change-Id: Ia825ed504f3ce156d0f46f18963690b528401361
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42966
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c')
-rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index c11bcb94..b387d73d 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -295,15 +295,16 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockwu |= CME_MASK_BC; g_eimr_override |= IRQ_VEC_WAKE_C0 | IRQ_VEC_WAKE_C1; +#if HW386841_NDD1_DSL_STOP1_FIX + // Set AUTO_STOP1_DISABLE out32(CME_LCL_LMCR_OR, BIT32(18)); +#endif + // Set PM_BLOCK_INTERRUPTS out32(CME_LCL_SICR_OR, BITS32(2, 2)); - // Clear PM_EXIT - out32(CME_LCL_SICR_CLR, BITS32(4, 2)); - // Block Exit Enabled out32(CME_LCL_FLAGS_OR, BITS32(8, 2)); } @@ -314,8 +315,12 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockey |= CME_MASK_BC; g_eimr_override |= IRQ_VEC_STOP_C0 | IRQ_VEC_STOP_C1; - // Clear PM_ENTRY_ACK - out32(CME_LCL_SICR_CLR, BITS32(0, 2)); +#if HW386841_NDD1_DSL_STOP1_FIX + + // Set AUTO_STOP1_DISABLE + out32(CME_LCL_LMCR_OR, BIT32(18)); + +#endif // Block Entry Enabled out32(CME_LCL_FLAGS_OR, BITS32(10, 2)); @@ -333,9 +338,13 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockwu &= ~CME_MASK_BC; g_eimr_override &= ~(IRQ_VEC_WAKE_C0 | IRQ_VEC_WAKE_C1); +#if HW386841_NDD1_DSL_STOP1_FIX + // Clear AUTO_STOP1_DISABLE out32(CME_LCL_LMCR_CLR, BIT32(18)); +#endif + // Clear PM_BLOCK_INTERRUPTS out32(CME_LCL_SICR_CLR, BITS32(2, 2)); @@ -349,6 +358,13 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockey &= ~CME_MASK_BC; g_eimr_override &= ~(IRQ_VEC_STOP_C0 | IRQ_VEC_STOP_C1); +#if HW386841_NDD1_DSL_STOP1_FIX + + // Clear AUTO_STOP1_DISABLE + out32(CME_LCL_LMCR_CLR, BIT32(18)); + +#endif + // Block Entry Disabled out32(CME_LCL_FLAGS_CLR, BITS32(10, 2)); } |