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| author | Yue Du <daviddu@us.ibm.com> | 2017-07-10 23:25:45 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 18:27:45 -0500 |
| commit | 163b4a1ffb4f12707a8a2dbbc909d5ef737bddac (patch) | |
| tree | 4373376b3b92846725825939b8a83792c1b8785e /import/chips | |
| parent | a0488da1959604566126c97327649d60a13260df (diff) | |
| download | talos-hcode-163b4a1ffb4f12707a8a2dbbc909d5ef737bddac.tar.gz talos-hcode-163b4a1ffb4f12707a8a2dbbc909d5ef737bddac.zip | |
STOP: Fix block Entry and Exit
Change-Id: Ia825ed504f3ce156d0f46f18963690b528401361
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42966
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips')
4 files changed, 49 insertions, 10 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c index e060832f..c22c07b3 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c @@ -203,6 +203,9 @@ void pk_unified_irq_prty_mask_handler(void) bFound = 0; iPrtyLvl = 0; + PK_TRACE_DBG("DEBUG: Phantom IRQ Check, EISTR=%x %x.", + UPPER32(ext_irq_vector_pk), LOWER32(ext_irq_vector_pk)); + do { if (ext_irq_vectors_cme[iPrtyLvl][IDX_PRTY_VEC] & ext_irq_vector_pk) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 9b9a6ea4..17dbb0d9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -467,6 +467,8 @@ p9_cme_stop_exit() wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; core = ((wakeup >> 4) | (wakeup >> 2) | wakeup) & CME_MASK_BC; + PK_TRACE_DBG("DEBUG: Phantom Wakeup Check, Raw Wakeup[%x]", wakeup); + // ignore wakeup when it suppose to be handled by sgpe for (core_mask = 2; core_mask; core_mask--) { diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index c11bcb94..b387d73d 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -295,15 +295,16 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockwu |= CME_MASK_BC; g_eimr_override |= IRQ_VEC_WAKE_C0 | IRQ_VEC_WAKE_C1; +#if HW386841_NDD1_DSL_STOP1_FIX + // Set AUTO_STOP1_DISABLE out32(CME_LCL_LMCR_OR, BIT32(18)); +#endif + // Set PM_BLOCK_INTERRUPTS out32(CME_LCL_SICR_OR, BITS32(2, 2)); - // Clear PM_EXIT - out32(CME_LCL_SICR_CLR, BITS32(4, 2)); - // Block Exit Enabled out32(CME_LCL_FLAGS_OR, BITS32(8, 2)); } @@ -314,8 +315,12 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockey |= CME_MASK_BC; g_eimr_override |= IRQ_VEC_STOP_C0 | IRQ_VEC_STOP_C1; - // Clear PM_ENTRY_ACK - out32(CME_LCL_SICR_CLR, BITS32(0, 2)); +#if HW386841_NDD1_DSL_STOP1_FIX + + // Set AUTO_STOP1_DISABLE + out32(CME_LCL_LMCR_OR, BIT32(18)); + +#endif // Block Entry Enabled out32(CME_LCL_FLAGS_OR, BITS32(10, 2)); @@ -333,9 +338,13 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockwu &= ~CME_MASK_BC; g_eimr_override &= ~(IRQ_VEC_WAKE_C0 | IRQ_VEC_WAKE_C1); +#if HW386841_NDD1_DSL_STOP1_FIX + // Clear AUTO_STOP1_DISABLE out32(CME_LCL_LMCR_CLR, BIT32(18)); +#endif + // Clear PM_BLOCK_INTERRUPTS out32(CME_LCL_SICR_CLR, BITS32(2, 2)); @@ -349,6 +358,13 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) G_cme_stop_record.core_blockey &= ~CME_MASK_BC; g_eimr_override &= ~(IRQ_VEC_STOP_C0 | IRQ_VEC_STOP_C1); +#if HW386841_NDD1_DSL_STOP1_FIX + + // Clear AUTO_STOP1_DISABLE + out32(CME_LCL_LMCR_CLR, BIT32(18)); + +#endif + // Block Entry Disabled out32(CME_LCL_FLAGS_CLR, BITS32(10, 2)); } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index 0f4dd29a..829c1bee 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -492,11 +492,19 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) PK_TRACE_ERR("ERROR: Received Type2 Entry PIG When Wakeup_notify_select = 0. HALT SGPE!"); PK_PANIC(SGPE_PIG_TYPE2_ENTRY_WNS_CME); } + + PK_TRACE_INF("Core Request Entry via Type2"); + G_sgpe_stop_record.level[qloop][cloop] = + (cpayload_t2 & TYPE2_PAYLOAD_STOP_LEVEL); + + if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] & BIT32(qloop)) + { + PK_TRACE_DBG("Core is in Block Entry Mode, Ignore Now", cloop); + G_sgpe_stop_record.group.core[VECTOR_BLOCKE] |= + BIT32(((qloop << 2) + cloop)); + } else { - PK_TRACE_INF("Core Request Entry via Type2"); - G_sgpe_stop_record.level[qloop][cloop] = - (cpayload_t2 & TYPE2_PAYLOAD_STOP_LEVEL); G_sgpe_stop_record.group.core[VECTOR_ENTRY] |= BIT32(((qloop << 2) + cloop)); } @@ -513,8 +521,18 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) PK_TRACE_INF("Core Request Entry via Type3"); G_sgpe_stop_record.level[qloop][cloop] = (cpayload_t3 & TYPE2_PAYLOAD_STOP_LEVEL); - G_sgpe_stop_record.group.core[VECTOR_ENTRY] |= - BIT32(((qloop << 2) + cloop)); + + if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] & BIT32(qloop)) + { + PK_TRACE_DBG("Core is in Block Entry Mode, Ignore Now", cloop); + G_sgpe_stop_record.group.core[VECTOR_BLOCKE] |= + BIT32(((qloop << 2) + cloop)); + } + else + { + G_sgpe_stop_record.group.core[VECTOR_ENTRY] |= + BIT32(((qloop << 2) + cloop)); + } } // both exit or one exit + one empty else |
