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| author | Yue Du <daviddu@us.ibm.com> | 2017-01-04 14:18:01 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:00:10 -0500 |
| commit | 2759b443f4af85efe7cd6d50d457bcbe2ea7ae55 (patch) | |
| tree | 77eedcf7ada84e95be4ea01bfadfbb81f30d13e9 /import/chips/p9/procedures/ppe | |
| parent | bf1bf0b7bbe9d35014e01085085dee2cb95f8051 (diff) | |
| download | talos-hcode-2759b443f4af85efe7cd6d50d457bcbe2ea7ae55.tar.gz talos-hcode-2759b443f4af85efe7cd6d50d457bcbe2ea7ae55.zip | |
HW398189: mask SIBRC = 6 in CME MSR under NDD1
Change-Id: I19df802466d23c371b23971dce43a67ddc9cd60d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34373
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: JAMES DEZELLE <jdezelle@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe')
| -rw-r--r-- | import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h | 18 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h | 8 |
2 files changed, 26 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h index d7472a29..6acb3bb7 100644 --- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h +++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h @@ -299,13 +299,31 @@ popcount64(uint64_t x) #if defined(USE_PPE_IMPRECISE_MODE) +#if defined(MASK_MSR_SEM6) + +#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \ + (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_IPE | MSR_SEM6) + +#else + #define PK_THREAD_MACHINE_CONTEXT_DEFAULT \ (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_IPE) + +#endif /*MASK_MSR_SEM6*/ + +#else + +#if defined(MASK_MSR_SEM6) + +#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \ + (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2 | MSR_SEM6) + #else #define PK_THREAD_MACHINE_CONTEXT_DEFAULT \ (MSR_UIE | MSR_EE | MSR_ME | MSR_IS0 | MSR_IS1 | MSR_IS2) +#endif /*MASK_MSR_SEM6*/ #endif /*USE_PPE_IMPRECISE_MODE*/ #endif /*PK_THREAD_MACHINE_CONTEXT_DEFAULT*/ diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h index eab82e27..619f448b 100644 --- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h +++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h @@ -57,6 +57,14 @@ #define MSR_SEM_START_BIT 1 #define MSR_SEM_LEN 7 +#define MSR_SEM1 0x40000000 +#define MSR_SEM2 0x20000000 +#define MSR_SEM3 0x10000000 +#define MSR_SEM4 0x08000000 +#define MSR_SEM5 0x04000000 +#define MSR_SEM6 0x02000000 +#define MSR_SEM7 0x01000000 + #define MSR_SIBRC_START_BIT 9 #define MSR_SIBRC_LEN 3 |
