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| author | Rahul Batra <rbatra@us.ibm.com> | 2018-10-04 12:12:06 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-10-31 10:42:28 -0500 |
| commit | 888eabf3c65b0c018c84fcaab43ad70f5c7b021c (patch) | |
| tree | 4168ea68db6a5c532d1c7bf2f207f06f55cf6db6 /import/chips/p9/procedures/hwp/lib | |
| parent | 081daf6f62d2f04781ac05fce4c71c67042d47ce (diff) | |
| download | talos-hcode-888eabf3c65b0c018c84fcaab43ad70f5c7b021c.tar.gz talos-hcode-888eabf3c65b0c018c84fcaab43ad70f5c7b021c.zip | |
PM:Fill SGPE/PGPE regions fields in QPMR/PPMR(3/4)
3rd commit in series of 4 commits which combined moves SGPE/PGPE
SRAM regions, and also allows to do so easily in future.
Commit 1(Hcode): Adds fields to OCC Complex Shared SRAM for storing SGPE
and PGPE region addresses/size, image header and debug header.
Commit 2(Hostboot): Moves around SGPE/PGPE regions, and adds fields
to QPMR/PPMR for storing SGPE/PGPE region info
Commit 3(Hcode): Populates the newly added SGPE/PGPE region info
fields in QPMR/PPMR
Commit 4(Hostboot): Adds check for QPMR and PPMR fields in the Hostboot Code
Key_Cronus_Test=PM_REGRESS
Change-Id: Id9493ba0843c26975e1b72e558501df7140fa10c
CQ: SW447651
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67018
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/lib')
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index f81c6817..98d6aac2 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -367,8 +367,6 @@ HCD_HDR_UINT32(g_pgpe_core_throttle_deassert_cnt, 0 ); // Core throttle de- HCD_HDR_UINT32(g_pgpe_aux_controls, 0 ); // Auxiliary Controls HCD_HDR_UINT32(g_pgpe_doptrace_offset, 0 ); // Deep Operational Trace Main Memory Buffer Offset HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional Trace Main Memory Buffer Length -HCD_HDR_UINT32(g_pgpe_sram_region_start, 0 ); // -HCD_HDR_UINT32(g_pgpe_sram_region_size, 0 ); // #ifdef __ASSEMBLER__ .endm #else |
