PM:Fill SGPE/PGPE regions fields in QPMR/PPMR(3/4)

    3rd commit in series of 4 commits which combined moves SGPE/PGPE
    SRAM regions, and also allows to do so easily in future.

    Commit 1(Hcode): Adds fields to OCC Complex Shared SRAM for storing SGPE
    and PGPE region addresses/size, image header and debug header.

    Commit 2(Hostboot): Moves around SGPE/PGPE regions, and adds fields
    to QPMR/PPMR for storing SGPE/PGPE region info

    Commit 3(Hcode): Populates the newly added SGPE/PGPE region info
    fields in QPMR/PPMR

    Commit 4(Hostboot): Adds check for QPMR and PPMR fields in the Hostboot Code

    Key_Cronus_Test=PM_REGRESS

Change-Id: Id9493ba0843c26975e1b72e558501df7140fa10c
CQ: SW447651
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67018
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

7 files changed, 49 insertions, 16 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index f81c6817..98d6aac2 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -367,8 +367,6 @@ HCD_HDR_UINT32(g_pgpe_core_throttle_deassert_cnt, 0 );      // Core throttle de-
 HCD_HDR_UINT32(g_pgpe_aux_controls,             0 );        // Auxiliary Controls
 HCD_HDR_UINT32(g_pgpe_doptrace_offset,          0 );        // Deep Operational Trace Main Memory Buffer Offset
 HCD_HDR_UINT32(g_pgpe_doptrace_length,          0 );        // Deep Opeartional Trace Main Memory Buffer Length
-HCD_HDR_UINT32(g_pgpe_sram_region_start,        0 );        //
-HCD_HDR_UINT32(g_pgpe_sram_region_size,         0 );        //
 #ifdef __ASSEMBLER__
 .endm
 #else
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c
index ada004b6..ba843cbe 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_img_edit.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2015,2017                                                    */
+/* COPYRIGHT 2015,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -99,14 +99,14 @@ int main(int narg, char* argv[])
             printf("                    PGPE size: %d\n", size);
             //  populating PGPE Image Header
             //  populating RESET address
-            uint32_t l_reset_addr_pos = offsetof(PgpeHeader_t, g_pgpe_sys_reset_addr);
+            uint32_t l_reset_addr_pos = PGPE_HEADER_IMAGE_OFFSET + offsetof(PgpeHeader_t, g_pgpe_sys_reset_addr);
             fseek (pMainImage, l_reset_addr_pos, SEEK_SET);
-            temp = PGPE_HCODE_RESET_ADDR_VAL;
+            temp = OCC_SRAM_PGPE_HCODE_RESET_ADDR;
             temp = htonl(temp);
             fwrite(&(temp), sizeof(uint32_t), 1, pMainImage );
 
-            buildDatePos = offsetof(PgpeHeader_t, g_pgpe_build_date);
-            buildVerPos  = offsetof(PgpeHeader_t, g_pgpe_build_ver);
+            buildDatePos = PGPE_HEADER_IMAGE_OFFSET + offsetof(PgpeHeader_t, g_pgpe_build_date);
+            buildVerPos  = PGPE_HEADER_IMAGE_OFFSET + offsetof(PgpeHeader_t, g_pgpe_build_ver);
         }
 
         // build date
@@ -129,7 +129,7 @@ int main(int narg, char* argv[])
 
         if (imageType == PPMR_IMAGE)
         {
-            //SGPE HCODE offset in PPMR header
+            //PGPE HCODE offset in PPMR header
             uint32_t l_hcode_offset_pos = offsetof(PpmrHeader_t, g_ppmr_hcode_offset);
             fseek ( pMainImage , l_hcode_offset_pos, SEEK_SET );
             temp =  sizeof(PpmrHeader_t) +
@@ -139,13 +139,29 @@ int main(int narg, char* argv[])
             temp = htonl(temp);
             fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
 
-            //SGPE Hcode length in PPMR header
+            //PGPE Hcode length in PPMR header
             uint32_t l_hcode_length_pos = offsetof(PpmrHeader_t, g_ppmr_hcode_length);
             fseek ( pMainImage , l_hcode_length_pos, SEEK_SET );
             temp = l_ppmr_pgpe_hcode_len_val;
             printf("                    PPMR Hcode size:   0x%X (%d)\n", temp, temp);
             temp = htonl(temp);
             fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+            //PGPE SRAM Region Start
+            uint32_t l_pgpe_sram_region_start_offset = offsetof(PpmrHeader_t, g_ppmr_pgpe_sram_region_start);
+            fseek ( pMainImage , l_pgpe_sram_region_start_offset, SEEK_SET );
+            temp = OCC_SRAM_PGPE_BASE_ADDR;
+            printf("                    PPMR Pgpe Sram Region Start: 0x%X\n", temp);
+            temp = htonl(temp);
+            fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+            //PGPE SRAM Region Size
+            uint32_t l_pgpe_sram_region_size_offset = offsetof(PpmrHeader_t, g_ppmr_pgpe_sram_region_size);
+            fseek ( pMainImage , l_pgpe_sram_region_size_offset, SEEK_SET );
+            temp = OCC_SRAM_PGPE_REGION_SIZE;
+            printf("                    PPMR Pgpe Sram Region Size: 0x%X\n", temp);
+            temp = htonl(temp);
+            fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
         }
 
         fclose(pMainImage);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
index e53c1432..8488b442 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
@@ -316,7 +316,7 @@ main(int argc, char** argv)
 
     OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_sram_region_start = OCC_SRAM_PGPE_BASE_ADDR;
     OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_image_header_addr = OCC_SRAM_PGPE_BASE_ADDR + PGPE_HEADER_IMAGE_OFFSET;
-    OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_debug_header_addr = OCC_SRAM_PGPE_BASE_ADDR + SGPE_DEBUG_PTRS_OFFSET;
+    OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_debug_header_addr = OCC_SRAM_PGPE_BASE_ADDR + PGPE_DEBUG_PTRS_OFFSET;
 
     // Start running the highest priority thread.
     // This function never returns
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 560c4f25..3f6a5ffe 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -781,7 +781,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
         }
     }
 
-    //PK_TRACE_INF("PST: LowestDPLL:0x%x DPLL_PS0=0x%x", lowestDpll, G_gppb->dpll_pstate0_value);
+    PK_TRACE_INF("PST: LowestDPLL:0x%x DPLL_PS0=0x%x", lowestDpll, G_gppb->dpll_pstate0_value);
 
     //2. Determine Sync Pstate
     if (lowestDpll > G_gppb->dpll_pstate0_value)
@@ -898,7 +898,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
         //to PMCR, and then switching the owner to CHAR which enables PCB_TYPE1 interrupts
         //and allows CME to forward Pstate Requests
         p9_pgpe_pstate_set_pmcr_owner(PMCR_OWNER_OCC);
-        //PK_TRACE_INF("PST: OWNER_CHAR");
+        PK_TRACE_INF("PST: OWNER_CHAR");
         G_pgpe_pstate_record.pmcrOwner = PMCR_OWNER_CHAR;
         g_oimr_override &= ~(BIT64(46));
         out32(G_OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk
index 989b13d3..6e8376bf 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_common.mk
@@ -91,7 +91,7 @@ PSTATE_COMMONFLAGS+= -DPK_TRACE_SUPPORT=1
 PSTATE_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
 PSTATE_COMMONFLAGS+= -D__PPE_PLAT
 PSTATE_COMMONFLAGS+= -D__PK__=1
-PSTATE_COMMONFLAGS+= -DPK_TRACE_SZ=512
+PSTATE_COMMONFLAGS+= -DPK_TRACE_SZ=1024
 PSTATE_COMMONFLAGS+= -DPSTATE_GPE
 
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
index 9578d8d5..f7965d8f 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
@@ -94,7 +94,7 @@ $(IMAGE)_COMMONFLAGS+= -DUSE_PK_APP_CFG_H=1
 $(IMAGE)_COMMONFLAGS+= -D__PPE_PLAT
 $(IMAGE)_COMMONFLAGS+= -D__PK__=1
 #$(IMAGE)_COMMONFLAGS+= -fstack-usage
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SZ=512
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_SZ=1024
 
 # add include paths
 $(call ADD_PPEIMAGE_INCDIR,$(IMAGE),\
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c
index 46a64c16..dcc08e7f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_img_edit.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2015,2017                                                    */
+/* COPYRIGHT 2015,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -25,10 +25,12 @@
 
 #include <stdio.h>
 #include <stdint.h>
+#include <stddef.h>     /* offsetof */
 #include <netinet/in.h>
 #include <time.h>
 
 #include <p9_hcd_memmap_base.H>
+#include <p9_hcode_image_defines.H>
 
 enum
 {
@@ -98,7 +100,7 @@ int main(int narg, char* argv[])
             //  populating SGPE Image Header
             //  populating RESET address
             fseek (pMainImage, SGPE_RESET_ADDR_IMAGE_OFFSET, SEEK_SET);
-            temp = SGPE_HCODE_RESET_ADDR_VAL;
+            temp = OCC_SRAM_SGPE_HCODE_RESET_ADDR;
             temp = htonl(temp);
             fwrite(&(temp), sizeof(uint32_t), 1, pMainImage );
         }
@@ -131,6 +133,23 @@ int main(int narg, char* argv[])
             temp = QPMR_SGPE_HCODE_LEN_VAL;
             temp = htonl(temp);
             fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+            //SGPE SRAM Region Start
+            uint32_t l_sgpe_sram_region_start_offset = offsetof(QpmrHeaderLayout_t, sgpeSramRegionStart);
+            fseek ( pMainImage , l_sgpe_sram_region_start_offset, SEEK_SET );
+            temp = OCC_SRAM_SGPE_BASE_ADDR;
+            printf("                    QPMR Sgpe Sram Region Start: 0x%X\n", temp);
+            temp = htonl(temp);
+            fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
+            //SGPE SRAM Region Size
+            uint32_t l_sgpe_sram_region_size_offset = offsetof(QpmrHeaderLayout_t, sgpeSramRegionSize);
+            fseek ( pMainImage , l_sgpe_sram_region_size_offset, SEEK_SET );
+            temp = OCC_SRAM_SGPE_REGION_SIZE;
+            printf("                    QPMR Sgpe Sram Region Size: 0x%X\n", temp);
+            temp = htonl(temp);
+            fwrite(&temp, sizeof(uint32_t), 1, pMainImage );
+
         }
 
         fclose(pMainImage);