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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2018-09-17 02:10:38 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-09-26 10:45:16 -0500 |
| commit | 3061db3d69eef2467d489dc49ba59c27fac7587c (patch) | |
| tree | 3204a5f19a63b069a9088d01cda27ed403d39631 /import/chips/p9/procedures/hwp/lib | |
| parent | d7e8d78835772e050c45a2f54a3cba643112d8ae (diff) | |
| download | talos-hcode-3061db3d69eef2467d489dc49ba59c27fac7587c.tar.gz talos-hcode-3061db3d69eef2467d489dc49ba59c27fac7587c.zip | |
STOP API: Changes for SMF and SPR self save
Commit accomplishes following:
- Implementation of new self restore region memory layout
- Restore of SPRs pertaining to SMF
- Self save of SPRs
- Backward compatibility with old self restore layout
Key_Cronus_Test=PM_REGRESS
Change-Id: I11359e392102d32896251225907eb95a43ba6f78
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66212
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/lib')
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 9b3c2ffd..1f5355a5 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -311,6 +311,9 @@ HCD_CONST(CPMR_ATTN_WORD1_BYTE, 0x04) HCD_CONST(CPMR_MAGIC_NUMBER_BYTE, 0x08) HCD_CONST(CPMR_BUILD_DATE_BYTE, 0x10) HCD_CONST(CPMR_BUILD_VER_BYTE, 0x14) +HCD_CONST(CPMR_SELF_RESTORE_VER_BYTE, 0x1C) +HCD_CONST(CPMR_STOP_API_VER_BYTE, 0x1D) +HCD_CONST(CPMR_URMOR_FIX_BYTE, 0x1E) HCD_CONST(CPMR_CME_HCODE_OFFSET_BYTE, 0x20) HCD_CONST(CPMR_CME_HCODE_LENGTH_BYTE, 0x24) HCD_CONST(CPMR_CORE_COMMON_RING_OFFSET_BYTE, 0x28) @@ -325,7 +328,7 @@ HCD_CONST(CPMR_SELF_RESTORE_OFFSET_BYTE, 0x48) HCD_CONST(CPMR_SELF_RESTORE_LENGTH_BYTE, 0x4C) HCD_CONST(CPMR_MAX_SCOM_REST_PER_CORE_BYTE, 0x50) -/// Self Restore +/// Self Restore without SMF Support HCD_CONST(SELF_RESTORE_CPMR_OFFSET, CPMR_HEADER_SIZE) HCD_CONST(SELF_RESTORE_INT_SIZE, (8 * ONE_KB)) @@ -344,7 +347,25 @@ HCD_CONST(SELF_RESTORE_CORE_REGS_SIZE, HCD_CONST(SELF_RESTORE_SIZE_TOTAL, (SELF_RESTORE_CODE_SIZE + SELF_RESTORE_CORE_REGS_SIZE)) - +// Self Restore Region With SMF Support +HCD_CONST(SMF_THREAD_LAUNCHER_SIZE, 1024) +HCD_CONST(SMF_SELF_RESTORE_CODE_SIZE, + (SELF_RESTORE_INT_SIZE + SMF_THREAD_LAUNCHER_SIZE)) + +HCD_CONST(SMF_CORE_RESTORE_THREAD_AREA_SIZE, HALF_KB) +HCD_CONST(SMF_SELF_SAVE_THREAD_AREA_SIZE, 256) +HCD_CONST(SMF_CORE_RESTORE_CORE_AREA_SIZE, HALF_KB) +HCD_CONST(SMF_CORE_SAVE_CORE_AREA_SIZE, HALF_KB) + +HCD_CONST(SMF_SELF_RESTORE_CORE_REGS_SIZE, + MAX_CORES_PER_CHIP * ((SMF_CORE_RESTORE_THREAD_AREA_SIZE* MAX_THREADS_PER_CORE ) + + (SMF_SELF_SAVE_THREAD_AREA_SIZE* MAX_THREADS_PER_CORE ) + + SMF_CORE_RESTORE_CORE_AREA_SIZE + + SMF_CORE_SAVE_CORE_AREA_SIZE )) + +HCD_CONST(SMF_SELF_RESTORE_SIZE_TOTAL, + (SMF_SELF_RESTORE_CODE_SIZE + SMF_SELF_RESTORE_CORE_REGS_SIZE)) +HCD_CONST( EC_LEVEL_URMOR_FIX, 0x23 ) /// Core Scom HCD_CONST(CORE_SCOM_RESTORE_CPMR_OFFSET, (256 * ONE_KB)) |
