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| author | Rahul Batra <rbatra@us.ibm.com> | 2019-01-15 16:39:46 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2019-06-14 10:53:14 -0500 |
| commit | 2def3a70b164ef035b8a616a39d8597a22ab021f (patch) | |
| tree | a3a66665647f34205dd0e33c260f9ef6413e6ecc /import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | |
| parent | e9c438bf807bc6cc5fc734f35b4bf510e28a473a (diff) | |
| download | talos-hcode-2def3a70b164ef035b8a616a39d8597a22ab021f.tar.gz talos-hcode-2def3a70b164ef035b8a616a39d8597a22ab021f.zip | |
PM: WOV(OCS) HW Procedures Changes (1/2)
1st commit in the series of 2 commits for WOV(Over Current
Sampling, OCS)
Commit 1: WOV(OCS) HW procedures updates
Commit 2: WOV(OCS) PGPE Hcode updates
Key_Cronus_Test=PM_REGRESS
HW-Image-Prereq: Ieabbc383d2bbbd1df8cf5a2ed5b503c860518cd8
Change-Id: I6234f0f60b9ed57b8b144159f3fe9c0b756df1e3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70513
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H')
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index eeae5161..69acacb0 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -374,8 +374,10 @@ HCD_HDR_UINT32(g_wof_table_length, 0 ); // WOF Table length HCD_HDR_UINT32(g_pgpe_core_throttle_assert_cnt, 0 ); // Core throttle assert count HCD_HDR_UINT32(g_pgpe_core_throttle_deassert_cnt, 0 ); // Core throttle de-aasert count HCD_HDR_UINT32(g_pgpe_aux_controls, 0 ); // Auxiliary Controls +HCD_HDR_UINT32(g_pgpe_optrace_pointer, 0 ); // Operational Trace OCC SRAM Pointer HCD_HDR_UINT32(g_pgpe_doptrace_offset, 0 ); // Deep Operational Trace Main Memory Buffer Offset HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional Trace Main Memory Buffer Length +HCD_HDR_UINT32(g_pgpe_wof_values_address, 0 ); // SRAM address where PGPE Produced WOF values are located #ifdef __ASSEMBLER__ .endm #else |
